TW202343717A - 電子封裝件 - Google Patents

電子封裝件 Download PDF

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Publication number
TW202343717A
TW202343717A TW111115468A TW111115468A TW202343717A TW 202343717 A TW202343717 A TW 202343717A TW 111115468 A TW111115468 A TW 111115468A TW 111115468 A TW111115468 A TW 111115468A TW 202343717 A TW202343717 A TW 202343717A
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Taiwan
Prior art keywords
layer
electronic
electronic package
circuit
protective layer
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TW111115468A
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English (en)
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TWI790962B (zh
Inventor
鍾松樺
陳亮斌
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW111115468A priority Critical patent/TWI790962B/zh
Priority to CN202210480179.XA priority patent/CN116978884A/zh
Priority to US17/853,097 priority patent/US20230343691A1/en
Application granted granted Critical
Publication of TWI790962B publication Critical patent/TWI790962B/zh
Publication of TW202343717A publication Critical patent/TW202343717A/zh

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Abstract

一種電子封裝件，係於封裝層中嵌埋電子結構，且於該封裝層上結合保護層，並將絕緣層結合於該保護層上，並形成有至少一貫穿該絕緣層與該保護層之盲孔，使該電子結構外露於該盲孔，供後續形成於該絕緣層上之線路層延伸至該盲孔中以電性連接該電子結構，故藉由該絕緣層與保護層之雙層設計，使製程所產生之氣泡無法轉移至該絕緣層，避免該氣泡殘存於該線路層中。

Description

電子封裝件
本發明係有關一種半導體裝置，尤指一種可提升可靠度之電子封裝件。
為了確保電子產品和通信設備的持續小型化和多功能性，半導體封裝需朝尺寸微小化發展，以利於多引腳之連接，並具備高功能性。
圖1係為習知半導體封裝件1之剖面示意圖。首先，提供一具有相對之轉接側10a與置晶側10b之矽中介板(Through Silicon interposer，簡稱TSI)10，且該矽中介板10具有複數連通該置晶側10b與轉接側10a之導電矽穿孔(Through-silicon via，簡稱TSV)100，並於該置晶側10b上形成一如RDL(redistribution layer)型之線路結構11以供接置一具有較小銲錫凸塊150間距之半導體晶片15，再將該矽中介板10以其轉接側10a透過複數導電元件18設於一具有較大線距之封裝基板13上，並使該封裝基板13電性連接該些導電矽穿孔100。接著，形成封裝膠體16於該封裝基板13上，以令該封裝膠體16包覆該半導體晶片15與該矽中介板10。最後，形成複數銲球12於該封裝基板13之下側植球墊130，以供接置於一電路板1a上。
習知半導體封裝件1中，該半導體晶片15與該封裝基板13之間係藉由該線路結構11進行電源/訊號之傳輸。
惟，若需增加該半導體封裝件1之功能，需於單一矽中介板10上配置多個半導體晶片15，因而需增加該線路結構11之佈線之層數(如由圖1所示之一層介電層110增加為多層介電層)，導致因佈線之層數越多而製程良率越低之緣故，致使該半導體晶片15無法有效電性連接該線路結構11，造成該半導體封裝件1之良率與可靠度不佳等問題。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：封裝層，係具有相對之第一表面與第二表面；電子結構，係嵌埋於該封裝層中；保護層，係結合於該封裝層之第一表面上；絕緣層，係結合於該保護層上，並形成有至少一貫穿該絕緣層與該保護層之盲孔，使該電子結構外露於該盲孔；以及線路層，係形成於該絕緣層上並延伸至該盲孔中以電性連接該電子結構。
前述之電子封裝件中，該電子結構係具有複數導電體及包覆該複數導電體之包覆層。
前述之電子封裝件中，形成該保護層之材質係為絕緣材。
前述之電子封裝件中，該保護層之密度係至少為3(g/cc)以上。
前述之電子封裝件中，該保護層與該絕緣層之彈性模數不同。
前述之電子封裝件中，該絕緣層之彈性模數係小於該保護層之彈性模數。
前述之電子封裝件中，該保護層之彈性模數係至少為200Gpa以上。
前述之電子封裝件中，該絕緣層之厚度與該保護層之厚度的總和係等於該盲孔的深度。
前述之電子封裝件中，該保護層之厚度係至少為0.6微米。
前述之電子封裝件中，該絕緣層之厚度與該保護層之厚度的總和係至少為5微米以上。
前述之電子封裝件中，復包括嵌埋於該封裝層中且電性連接該線路層之複數導電柱。
前述之電子封裝件中，復包括形成於該封裝層之第二表面上且電性連接該複數導電體之線路結構。進一步，復包括至少一配置於該線路結構上且電性連接該線路結構之電子元件。例如，該線路結構上係配置複數該電子元件，使該電子結構作為橋接元件，以電性橋接至少二該電子元件。
前述之電子封裝件中，復包括形成於該線路層上且電性連接該線路層之複數導電元件。
前述之電子封裝件中，該電子結構係為半導體晶片，其具有複數電性連接該線路層之電極墊。
由上可知，本發明之電子封裝件中，主要藉由該絕緣層與保護層之設計，使該包覆層或封裝層所產生之氣泡無法轉移至該絕緣層，因而能避免該氣泡殘存於該線路層中，故本發明之電子封裝件能大幅提高該 線路層之製程良率，使該線路層有效電性連接該電子結構與該導電元件，因而有利於提升該電子封裝件之良率與可靠度。
再者，當需增加該電子封裝件之功能時，只需於單一線路結構上配置一個電子結構，而無需增加該線路結構之佈線之層數，故相較於習知技術，本發明可依需求控管該線路結構之佈線之層數而可提高製程良率，使該電子元件可有效電性連接該線路結構，以提升該電子封裝件之良率與可靠度。
1:半導體封裝件
1a:電路板
10:矽中介板
10a:轉接側
10b:置晶側
100:導電矽穿孔
11,20:線路結構
110:介電層
12,300:銲球
13,30:封裝基板
130:植球墊
15:半導體晶片
150:銲錫凸塊
16:封裝膠體
18,27:導電元件
2,4:電子封裝件
2a,40:電子結構
2b:佈線結構
200:介電層
201:線路重佈層
202:電性接觸墊
21:電子主體
21a:第一導電體
21b:第一包覆層
210:導電穿孔
22:線路部
22a:第二導電體
22b:第二包覆層
220:鈍化層
221:導電跡線
23:導電柱
24:絕緣層
240:盲孔
241:線路層
25:第一封裝層
25a,45a:第一表面
25b,45b:第二表面
26:電子元件
26a:導電凸塊
260:銲錫材料
262:底膠
270:金屬凸塊
271:銲錫材料
28:第二封裝層
29:保護層
31:強固件
40a:作用面
40b:非作用面
400:電極墊
45:封裝層
48:絕緣保護層
51:包覆層
52:導電體
h:深度
t1,t2:厚度
圖1係為習知半導體封裝件之剖視示意圖。
圖2A係為本發明之電子封裝件之第一實施例的剖視示意圖。
圖2B係為圖2A之局部放大剖視示意圖。
圖3係為圖2A之應用之剖視示意圖。
圖4係為本發明之電子封裝件之第二實施例的剖視示意圖。
圖5係為圖4之另一態樣的剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結 構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A係為本發明之電子封裝件2之第一實施例的剖面示意圖。如圖2A所示，所述之電子封裝件2係包括：一第一封裝層25、一嵌埋於該第一封裝層25中之電子結構2a、複數嵌埋於該第一封裝層25中之導電柱23、以及一形成於該第一封裝層25上之佈線結構2b。
所述之第一封裝層25係具有相對之第一表面25a與第二表面25b。
於本實施例中，該第一封裝層25係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如，該第一封裝層25之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成。
所述之電子結構2a係包含一電子主體21、一形成於該電子主體21上之線路部22、複數形成於該電子主體21上之第一導電體21a、及複數形成於該線路部22上且電性連接該線路部22之第二導電體22a，且藉由第一包覆層21b與第二包覆層22b包覆該複數第一導電體21a與該複數第二導電體22a。
於本實施例中，該電子主體21係為矽基材，如半導體晶片，其具有複數貫穿該電子主體21之導電穿孔210，如導電矽穿孔(Through- silicon via，簡稱TSV)，以電性連接位於該電子主體21不同側之該線路部22與該複數第一導電體21a。例如，該線路部22係包含至少一鈍化層220及結合該鈍化層220之導電跡線221，以令該導電跡線221電性連接該導電穿孔210與該複數第二導電體22a。應可理解地，有關具有該導電穿孔210之元件結構之態樣繁多，並無特別限制。
再者，該第一導電體21a與第二導電體22a係為如銅柱之金屬柱，且該第一包覆層21b與第二包覆層22b係為非導電膜(Non-Conductive Film，簡稱NCF)、底膠或其它絕緣材質。
所述之導電柱23係為如銅柱之金屬柱或銲錫球體，其電性連接該佈線結構2b。
於本實施例中，該第一封裝層25之第一表面25a齊平該導電柱23之端面與該第二導電體22a之端面，且該第一封裝層25之第二表面25b齊平該導電柱23之端面與該第一導電體21a之端面。
所述之佈線結構2b係包含一結合該第一封裝層25之保護層29、至少一結合該保護層29之絕緣層24、及結合該絕緣層24與該保護層29之線路層241，以令該線路層241電性連接該複數第二導電體22a與該複數導電柱23。
於本實施例中，該保護層29係為絕緣薄膜，如氮化矽(SiN)之氮化物或其它有機介電材，其密度係至少為3(g/cc)以上，且形成該絕緣層24之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材，並可採用線路重佈層(redistribution layer，簡稱RDL)製程形成該線路層241。
再者，該線路層241係貫穿該絕緣層24與保護層29以接觸該第二導電體22a。例如，先形成一貫穿該絕緣層24與保護層29之盲孔240，如圖2B所示，使該第二導電體22a外露於該盲孔240，再藉由電鍍或其它方式形成銅材於該盲孔240中，使該線路層241延伸至該盲孔240中以電性連接該第二導電體22a，其中，該絕緣層24之厚度t1與該保護層29之厚度t2的總和係等於該盲孔240的深度h。進一步，該保護層29之厚度t2係至少為0.6微米(um)。較佳者，該絕緣層24之厚度t1與該保護層29之厚度t2的總和係至少為5微米以上，以避免應力集中所產生之翹曲或其它問題。
又，該保護層29與該絕緣層24之彈性模數不同。例如，該絕緣層24之彈性模數(約5.2Gpa)係小於該保護層29之彈性模數(至少200Gpa以上)。
另外，可形成複數導電元件27於該佈線結構2b上，使該些導電元件27電性連接該線路層241。
於本實施例中，該導電元件27係包含一如銅材之金屬凸塊270及形成於該金屬凸塊270上之銲錫材料271。例如，該線路層241上可形成凸塊底下金屬層(Under Bump Metallization，簡稱UBM)(圖略)，以利於結合該金屬凸塊270。
因此，本發明之電子封裝件2主要藉由當製作單一線路層241時，於該第一封裝層25之第一表面25a上形成該絕緣層24與保護層29等多層結構，以增厚絕緣材，使該第二包覆層22b(NCF)於後續熱製程中所產生之氣泡(void)無法轉移至該絕緣層24，以避免該氣泡散逸至該盲孔240中而導致該線路層241之結構強度不足(即包含氣泡而非全部實心結構)之問題，故本發明之線路層241之製程良率能大幅提高，以有效電性 連接該電子結構2a與該導電元件27，因而有利於提升該電子封裝件2之良率與可靠度。
於其它實施例中，該電子封裝件2復可包括：一設於該第一封裝層25上之線路結構20、設於該線路結構20上之至少一(或複數)電子元件26、以及一包覆該電子元件26之第二封裝層28。
所述之線路結構20係形成於該第一封裝層25之第二表面25b上，以令該線路結構20電性連接該導電柱23與該複數第一導電體21a。
於本實施例中，該線路結構20係包括至少一介電層200及設於該介電層200上之線路重佈層(redistribution layer，簡稱RDL)201，使該線路重佈層201電性連接該複數導電柱23與該複數第一導電體21a，其中，最外層之介電層200可作為防銲層，且令最外層之線路重佈層201外露出該防銲層，俾供作為電性接觸墊202，如微墊(micro pad，俗稱μ-pad)。
再者，形成該線路重佈層201之材質係為銅，且形成該介電層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材、或如綠漆、油墨等之防銲材。
所述之電子元件26係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
於本實施例中，該電子元件26係例如為圖形處理器(graphics processing unit，簡稱GPU)、高頻寬記憶體(High Bandwidth Memory，簡稱HBM)等半導體晶片。例如，該電子元件26係可藉由覆晶方式、打 線方式、直接接觸該線路結構20或其它適當方式電性連接該線路重佈層201，並無特別限制。
再者，若該電子元件26採用覆晶方式，其可藉由複數如銅柱之導電凸塊26a配合銲錫材料260電性連接該電性接觸墊202。較佳者，可形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)(圖略)於該電性接觸墊202或該電子元件26上，以利於結合該銲錫材料260或該導電凸塊26a。
又，若該線路結構20上配置多個電子元件26，則可令該電子結構2a作為橋接元件(Bridge die)，使該電子結構2a藉由該些第一導電體21a電性連接該線路重佈層201，進而電性橋接至少二電子元件26。
所述之第二封裝層28係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該線路結構20上。應可理解地，該第二封裝層28與該第一封裝層25之材質可相同或相異。
於本實施例中，可先形成底膠262於該電子元件26與該線路結構20之間以包覆該些導電凸塊26a與銲錫材料260，再形成該第二封裝層28以包覆該底膠262與該電子元件26。或者，直接以該第二封裝層28同時包覆該電子元件26與該些導電凸塊26a及銲錫材料260。
再者，可藉由整平製程，如研磨方式，移除該第二封裝層28之部分材質，使該第二封裝層28之上表面齊平該電子元件26之上表面，如圖3所示，以令該電子元件26外露出該第二封裝層28。
因此，本發明藉由將該電子結構2a作為橋接元件，以電性橋接至少兩個電子元件26，因而當需增加該電子封裝件2之功能時，只需於 單一線路結構20上配置一個電子結構2a，而無需增加該線路重佈層201之層數，故相較於習知技術，本發明之線路結構20因該線路重佈層201可依需求控管層數而能提高製程良率，使該電子元件26能有效電性連接該線路重佈層201，以提升該電子封裝件2之良率與可靠度。
又，如圖3所示，該電子封裝件2可藉由該些導電元件27設置於一封裝基板30上。進一步，該封裝基板30下側進行植球製程以形成複數銲球300，供該封裝基板30以其下側之銲球300設於一電路板(圖略)上。
另外，該封裝基板30上可依需求設置一強固件31，如圖3所示之金屬框，以消除應力集中之問題而避免電子封裝件2發生翹曲之情況。
圖4係為本發明之電子封裝件4之第二實施例的剖面示意圖。如圖4所示，所述之電子封裝件4係採用扇出(fan out)式晶圓級晶片規格進行封裝，其包括：一封裝層45、一嵌埋於該封裝層45中之電子結構40、一結合於該封裝層上之保護層29、一結合於該保護層29上之絕緣層24以及一形成於該絕緣層24上之線路層241。
所述之封裝層45係具有相對之第一表面45a與第二表面45b，以令該保護層29結合於該封裝層45之第一表面45a上。
所述之電子結構40係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於本實施例中，該電子結構40係為半導體晶片，其具有相對之作用面40a與非作用面40b，該作用面40a具有複數電極墊400，且可依需求外露該非作用面40b(如圖5所示之該非作用面40b與該封裝層45之第二表面45b共平面)。
所述之絕緣層24係形成有至少一貫穿該絕緣層24與該保護層29之盲孔240，使該電子結構40之電極墊400外露於該盲孔240。
所述之線路層241係延伸至該盲孔240中以電性連接該電子結構40之電極墊400。於本實施例中，該線路層241上可形成複數導電元件27，以令該電子封裝件4藉由該複數導電元件27接置於一如圖3所示之封裝基板30上或電路板(圖略)上。進一步，可於該絕緣層24上形成一如防銲層之絕緣保護層48，其外露該線路層241之部分表面，以結合該導電元件27。
因此，本發明之電子封裝件4主要藉由當製作單一線路層241時，於該封裝層45之第一表面45a上形成該絕緣層24與保護層29等多層結構，以增厚絕緣材，使該封裝層45於後續熱製程中所產生之氣泡(void)無法轉移至該絕緣層24，以避免該氣泡散逸至該盲孔240中而導致該線路層241之結構強度不足(即包含氣泡而非全部實心結構)之問題，故本發明之線路層241之製程良率能大幅提高，以有效電性連接該電子結構40與該導電元件27，因而有利於提升該電子封裝件4之良率與可靠度。
應可理解地，有關扇出式晶圓級晶片規格之形式繁多，如圖5所示，其電子結構40之作用面40a之電極墊400上可配置如金屬柱之導電體52，並藉由一如膠膜之包覆層51包覆該些導電體52，故無特別限制該扇出式晶圓級晶片規格之形式。
綜上所述，本發明之電子封裝件，係藉由該絕緣層與保護層之設計，使該包覆層或第二包覆層(或第一封裝層、封裝層)所產生之氣泡無法轉移至該絕緣層，因而能避免該氣泡殘存於該線路層中，故本發明能大幅提高該線路層之製程良率，以有效電性連接該電子結構與該導電元件，因而有利於提升該電子封裝件之良率與可靠度。
再者，藉由該電子結構作為橋接元件，以電性橋接至少兩個電子元件，因而當需增加該電子封裝件之功能時，只需於單一線路結構上配置一個電子結構，而無需增加該線路重佈層之層數，故本發明可依需求控管該線路重佈層之層數而能提高製程良率，使該電子元件能有效電性連接該線路重佈層，以提升該電子封裝件之良率與可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:電子結構
2b:佈線結構
20:線路結構
21:電子主體
21a:第一導電體
22:線路部
22a:第二導電體
22b:第二包覆層
23:導電柱
24:絕緣層
241:線路層
25:第一封裝層
26:電子元件
27:導電元件
28:第二封裝層
29:保護層
30:封裝基板
300:銲球
31:強固件

Claims (16)

  1. 一種電子封裝件，係包括：
    封裝層，係具有相對之第一表面與第二表面；
    電子結構，係嵌埋於該封裝層中；
    保護層，係結合於該封裝層之第一表面上；
    絕緣層，係結合於該保護層上，並形成有至少一貫穿該絕緣層與該保護層之盲孔，使該電子結構外露於該盲孔；以及
    線路層，係形成於該絕緣層上並延伸至該盲孔中以電性連接該電子結構。
  2. 如請求項1所述之電子封裝件，其中，該電子結構係具有複數導電體及包覆該複數導電體之包覆層。
  3. 如請求項1所述之電子封裝件，其中，形成該保護層之材質係為絕緣材。
  4. 如請求項1所述之電子封裝件，其中，該保護層之密度係至少為3(g/cc)以上。
  5. 如請求項1所述之電子封裝件，其中，該保護層與該絕緣層之彈性模數不同。
  6. 如請求項1所述之電子封裝件，其中，該絕緣層之彈性模數係小於該保護層之彈性模數。
  7. 如請求項1所述之電子封裝件，其中，該保護層之彈性模數係至少為200Gpa以上。
  8. 如請求項1所述之電子封裝件，其中，該絕緣層之厚度與該保護層之厚度的總和係等於該盲孔的深度。
  9. 如請求項1所述之電子封裝件，其中，該保護層之厚度係至少為0.6微米。
  10. 如請求項1所述之電子封裝件，其中，該絕緣層之厚度與該保護層之厚度的總和係至少為5微米以上。
  11. 如請求項1所述之電子封裝件，復包括嵌埋於該封裝層中且電性連接該線路層之複數導電柱。
  12. 如請求項1所述之電子封裝件，復包括形成於該封裝層之第二表面上且電性連接該電子結構之線路結構。
  13. 如請求項12所述之電子封裝件，復包括至少一配置於該線路結構上且電性連接該線路結構之電子元件。
  14. 如請求項13所述之電子封裝件，其中，該線路結構上係配置複數該電子元件，使該電子結構作為橋接元件，以電性橋接至少二該電子元件。
  15. 如請求項1所述之電子封裝件，復包括形成於該線路層上且電性連接該線路層之複數導電元件。
  16. 如請求項1所述之電子封裝件，其中，該電子結構係為半導體晶片，其具有複數電性連接該線路層之電極墊。
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