CN116682802A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN116682802A
CN116682802A CN202210252528.2A CN202210252528A CN116682802A CN 116682802 A CN116682802 A CN 116682802A CN 202210252528 A CN202210252528 A CN 202210252528A CN 116682802 A CN116682802 A CN 116682802A
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circuit
layer
electronic
electrically connected
circuit member
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张立楚
许元鸿
江东昇
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

本发明涉及一种电子封装件及其制法，其制法包括于一具有线路层的承载结构的相对两侧上分别配置一线路构件以及多个电子元件，以经由该线路层及该线路构件，使该多个电子元件的任二者相互电性导通，其中，该承载结构的垂直投影面积大于该线路构件的垂直投影面积，并使该线路构件未伸出该承载结构的侧面，以经由该线路构件取代该承载结构的部分线路层的配置层数，以降低该承载结构制作该线路层的困难度。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体封装制程，尤指一种可提升良率的电子封装件及其制法。
背景技术
随着科技的演进，电子产品需求趋势朝向异质整合迈进，为此，多芯片封装结构(MCM/MCP)逐渐兴起。
图1为现有半导体封装件1的剖面示意图。如图1所示，该半导体封装件1将多个半导体芯片11以覆晶方式经由多个导电凸块12设于一扇出型(Fan-out，简称FO)重布线路层(redistribution layer，简称RDL)式线路结构10上，再以底胶13包覆该些导电凸块12，并以封装层18包覆该些半导体芯片11。之后，该线路结构10以多个焊球14设于一封装基板1a上，并以封装材15包覆该些焊球14。
现有半导体封装件1将多颗半导体芯片11封装整合成一颗芯片的功能特性，使该半导体封装件1具有较多的接点(I/O)数与扩充单颗芯片的功能，借此可大幅增加处理器的运算能力，以减少信号传递的延迟时间，故可应用于高密度线路/高传输速度/高叠层数/大尺寸设计的高阶产品。
然而，现有半导体封装件1随着半导体芯片11的整合数量增加，各半导体芯片11的接点(I/O)(即该导电凸块12)的数量会渐增，使各该导电凸块12之间的间距(pitch)渐小，故用以电性连接该些半导体芯片11的扇出型重布线路层式线路结构10的布线因需朝更细线路/细间距的规格制作而使制程困难度大幅提升，且该线路结构10的布线层数的需求也需一并增加，致使该半导体封装件1的整体制作成本随着该线路结构10的制作成本增加而大幅提高，并导致该半导体封装件1的产品良率不高。
因此，如何克服上述现有技术的问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件及其制法，可降低承载结构制作线路层的困难度。
本发明的电子封装件，包括：具有线路层的承载结构，定义有相对的两侧；线路构件，其设于该承载结构的其中一侧并电性连接该线路层，其中，该承载结构的垂直投影面积大于该线路构件的垂直投影面积，并使该线路构件未伸出该承载结构的侧面；以及多个电子元件，其设于该承载结构的另一侧并电性连接该线路层，以经由该线路层及该线路构件，使该多个电子元件的任二者相互电性导通。
本发明亦提供一种电子封装件的制法，包括：将具有线路层的承载结构结合于一线路构件上，其中，该承载结构的垂直投影面积大于该线路构件的垂直投影面积，并使该线路构件未伸出该承载结构的侧面；以及设置多个电子元件于该承载结构上，使该线路构件及该多个电子元件分别位于该承载结构的不同侧，且令该多个电子元件电性连接该线路层，以经由该线路层及该线路构件，使该多个电子元件的任二者相互电性导通。
前述的电子封装件及其制法中，该线路构件为无核心层形式的布线结构。
前述的电子封装件及其制法中，该线路构件的线路配置层数大于该承载结构的线路层的配置层数。
前述的电子封装件及其制法中，该线路构件的线路配置层数至少五层。
前述的电子封装件及其制法中，该多个电子元件具有多个电极垫，且该线路构件的布设位置对应其所电性连接的该多个电子元件的电极垫的分布密集区域。
前述的电子封装件及其制法中，该线路构件相对该承载结构的垂直投影面积小于该多个电子元件中电性连接该线路构件的任一者相对该承载结构的垂直投影面积。
前述的电子封装件及其制法中，该线路构件于相对该承载结构的垂直方向上重叠该多个电子元件中电性连接该线路构件的任一者的部分区域。
前述的电子封装件及其制法中，还包括于该承载结构上配置多个导电柱，其位于该线路构件周围且电性连接该线路层。又包括先以包覆层包覆该线路构件与该多个导电柱，再将该承载结构形成于该包覆层上。进一步，还包括于该包覆层上形成多个电性连接该导电柱及/或该线路构件的导电元件。
由上可知，本发明的电子封装件及其制法中，主要经由该线路构件的设计，以满足任两个电子元件的电极垫的间距较小处需布设高层数线路层的布线需求，故相比于现有技术，本发明以小面积的该线路构件取代该承载结构的部分线路配置层数，以降低大面积的该承载结构制作该线路层的困难度，因而能达到降低制作成本及大幅提升良率的目的。
再者，本发明经由在该线路构件的周围以该包覆层填补整体结构强度，故能避免发生翘曲的问题。
另外，采用该线路构件配合该承载结构的布线设计，以减少该承载结构的线路层的配置层数，因而能有效降低整体制程难度及降低制作成本。
另外，经由该线路构件电性连接该导电元件，使该电子元件可通过该线路构件对外进行信号传递，以缩短电性路径，故可提升该电子封装件的电性表现。
附图说明
图1为现有半导体封装件的剖视示意图。
图2A至图2G为本发明的电子封装件的制法的剖视示意图。
图3为图2G的另一实施例的剖视示意图。
主要组件符号说明
1 半导体封装件
1a 封装基板
10 线路结构
11 半导体芯片
12,271 导电凸块
13,272 底胶
14 焊球
15 封装材
18,28 封装层
2,3 电子封装件
2a 线路板
20 电子装置
21,31 线路构件
210 线路重布层
211 绝缘体
212 保护膜
213 电性接触垫
22,32 导电体
22a,23a 端面
23 导电柱
24,34 结合层
25 包覆层
26 承载结构
26c 侧面
260 介电层
261 线路层
262 电性接触垫
263 凸块底下金属层
27 电子元件
27a 作用面
27b 非作用面
270 电极垫
29 导电元件
29a 焊锡材料
290 金属体
291 铜柱
9 承载件
90 离型层
91 粘着层
92 金属层
93 绝缘层
R1,R2,R3 垂直投影面积
P 分布密集区域
L,S 切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2G为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，提供一包含有多个线路构件21的线路板2a，再沿切割路径L切割该线路板2a，以获取多个线路构件21。
于本实施例中，该线路构件21为如具有核心层与布线结构的封装基板(substrate)或无核心层(coreless)形式的布线结构(图中呈现coreless型式)，其具有绝缘体211及结合该绝缘体211的多个(本实施例的线路配置层数为至少五层)扇出(fan out)型线路重布层(redistribution layer，简称RDL)210，其中，形成该绝缘体211的材料为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材。应可理解地，该线路构件21亦可为其它配置布线的板体，如有机板材(organic material)、半导体板材(silicon)、陶瓷板材(ceramic)或其它具有金属布线(routing)的载板，并不限于上述。
再者，该线路构件21的其中一侧结合并电性连接多个导电体22，且该导电体22为如导电线路、焊球的圆球状、或如铜柱、焊锡凸块等金属材的柱状、或焊线机制作的钉状(stud)，但不限于此。进一步，该导电体22形成于最外层的线路重布层210的电性接触垫213上，且该线路构件21的表面可形成有一如绝缘材的保护膜212，以包覆该些导电体22的部分表面，并使该导电体22的端面齐平及外露于该保护膜212。
如图2B所示，将至少一线路构件21设于一承载件9上，且于该承载件9上形成多个导电柱23，其中，该线路构件21与该导电柱23的设置顺序可依需求选择先后顺序，且该多个导电柱23位于该线路构件21周围。
于本实施例中，该承载件9例如为半导体材料(如硅或玻璃)的板体，其上以例如涂布方式依序形成有一离型层90、一粘着层91、一金属层92与一如介电材的绝缘层93。例如，形成该绝缘层93的材料如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材。
再者，形成该导电柱23的材料为如铜的金属材或焊锡材，且该导电柱23延伸穿过该绝缘层93以接触该金属层92。例如，经由曝光显影方式，于该绝缘层93上形成多个外露该金属层92的开口，以经由该金属层92从该开口中电镀形成该些导电柱23。
另外，该线路构件21以其另一侧经由一如芯片粘结薄膜(Die Attach Film，简称DAF)的结合层24粘固于该绝缘层93上。
如图2C所示，形成一包覆层25于该绝缘层93上，以令该包覆层25包覆该线路构件21、结合层24、该保护膜212与该多个导电柱23，再经由整平制程，令该导电柱23的端面23a与该导电体22的端面22a外露于该包覆层25，使该包覆层25的外表面齐平该导电柱23的端面23a与该导电体22的端面22a。
于本实施例中，该包覆层25为绝缘材，如环氧树脂的封装胶体，其可用压合(lamination)或模压(molding)的方式形成于该承载件9上。
再者，该整平制程经由研磨方式，移除该导电柱23的部分材料、该导电体22的部分材料、该保护膜212的部分材料与该包覆层25的部分材料。
如图2D所示，将一具有线路层261的承载结构26形成于该包覆层25上，且该承载结构26的线路层261电性连接该多个导电柱23与该线路构件21的多个导电体22。
于本实施例中，该承载结构26包括多个介电层260及设于该介电层260上的多个RDL规格的线路层261，且最外层的介电层260可作为防焊层，且令最外层的线路层261外露于该防焊层，以供作为电性接触垫262，如微垫(micro pad，俗称μ-pad)。或者，该承载结构26亦可仅包括单一介电层260及单一线路层261。例如，该线路构件21的线路配置层数(至少五层)大于该承载结构26的线路层261的配置层数(如本实施例图示的三层)。因此，经由小面积的该线路构件21可调配大面积或晶圆级(wafer form)的该线路层261的配置层数，使大面积的该线路层261的配置层数降低，以提高大面积的该承载结构26的制作良率。
再者，形成该线路层261的材料为铜，且形成该介电层260的材料为如聚对二唑苯(PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材、或如绿漆、油墨等的防焊材。
如图2E所示，于该承载结构26的最外层的线路层261上接置多个电子元件27，且该多个电子元件27电性连接该线路层261，以经由该线路层261及该线路构件21，使该多个电子元件27的任二者相互电性导通，即该线路构件21电性桥接任二电子元件27，其中，该线路构件21相对该承载结构26的垂直投影面积R1小于该多个电子元件27中电性连接该线路构件21的任一电子元件27相对该承载结构26的垂直投影面积R2。之后，再以一封装层28包覆该些电子元件27。
于本实施例中，该电子元件27为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该电子元件27为半导体芯片，其具有相对的作用面27a与非作用面27b，且以其作用面27a的电极垫270经由多个如焊锡材料的导电凸块271采用覆晶方式设于该电性接触垫262上并电性连接该线路层261，并可形成一凸块底下金属层(Under Bump Metallurgy，简称UBM)263于该电性接触垫262上，以利于结合该导电凸块271；或者，该电子元件27以其非作用面27b设于该承载结构26上，并可经由多个焊线(图略)以打线方式电性连接该电性接触垫262；亦或通过如导电胶或焊锡等导电材料(图略)电性连接该线路层261。然而，有关该电子元件27电性连接该线路层261的方式不限于上述。
另外，该封装层28为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该承载结构26上。应可理解地，形成该包覆层25及封装层28的材料可相同或相异。
另外，该封装层28可直接包覆该些导电凸块271；或者，可先形成底胶272于该电子元件27与该承载结构26之间以包覆该些导电凸块271，再形成该封装层28以包覆该底胶272与该电子元件27。
如图2F所示，剥除该承载件9及其上的离型层90，再蚀刻移除该粘着层91与金属层92，以令该多个导电柱23外露于该绝缘层93，供设置多个导电元件29于该多个导电柱23上，使该多个导电元件29电性连接该多个导电柱23，其中，该导电元件29包含一形成于该绝缘层93上以接触该些导电柱23的垫状金属体(如UBM)290、及多个设结合该金属体290的铜柱291，以于该铜柱291的端面上形成如焊锡凸块或焊球的焊锡材料29a。
于本实施例中，该线路构件21的布设位置对应其所电性连接的该多个电子元件27的电极垫270的分布密集区域P，使该线路构件21的线路重布层210的线宽小于2微米。例如，该线路构件21的布线规格为至多2微米的线宽/线距(L/S)(即L/S≦2/2μm)，且该电子元件27作为接点(I/O)的电极垫270的数量较多且密集之处定义为分布密集区域P，并使该分布密集区域P的电极垫270电性连接该线路构件21。
再者，该线路构件21于相对该承载结构26的垂直方向上重叠该多个电子元件27中电性连接该线路构件21的任一电子元件27的部分区域。例如，该线路构件21重叠其所电性桥接的该电子元件27的部分区域，以令该线路构件21相对该电子元件27的配置位置可对应叠合于该电子元件27的电极垫270的分布密集区域P上。
如图2G所示，沿如图2F所示的切割路径S进行切单制程，以形成一电子封装件2，且于后续制程中，该电子封装件2可经由该些导电元件29接置于一如封装基板或如电路板的电子装置20上。
于本实施例中，该承载结构26的垂直投影面积R3大于该线路构件21(或多个线路构件21的任一者)的垂直投影面积R1，并使该线路构件21(或多个线路构件21的任一者)未伸出该承载结构26的侧面26c。
因此，本发明的制法中，主要经由该线路构件21的细线路设计，使该些电子元件27中较小间距的接点(I/O)(即该分布密集区域P的电极垫270)能通过该线路构件21与该承载结构26的配合作为该些电子元件27相互电性导通的路径，以满足任两个电子元件27中的电极垫270的间距较小处需布设高层数的RDL结构(如该线路构件21的五层线路配置层数)的布线需求，故相比于现有技术的一次需铺设整面式的扇出型重布线路层的电性导通的设计，本发明的制法以小面积的该线路构件21取代大面积的该承载结构26的部分线路层261，以降低用以接置该分布密集区域P的大面积线路层261的RDL布线层数，进而降低制作困难度，因而能达到降低制作成本及大幅提升良率的目的。
再者，经由该线路构件21的尺寸为可调式的设计，可平衡该电子封装件2的应力分布，故相比于现有技术，本发明采用局部(partial)RDL规格的线路构件21，以于切割该线路板2a时，即可配合结构需求的翘曲(warpage)程度来调整该线路构件21的尺寸，因而当该电子封装件2的面积为大尺寸规格时，能明显改善该电子封装件2的翘曲(warpage)程度，以提升该电子封装件2的可靠度。另外，为了进一步提升该电子封装件2的可靠度，可在该线路构件21周围经由强度较高的材料(即该包覆层25)填补整体结构强度，以进一步降低发生翘曲(warpage)的风险。
另外，由于该些电子元件27中较大间距的接点(即该分布密集区域P以外的其它区域的电极垫270)之处只需低层数的布线需求，因而通过该承载结构26与导电柱23的配合，即可进行电性传递，故本发明的制法采用局部高配置层数(线路构件21)配合局部低配置层数(承载结构26)的布线设计(即该线路构件21取代该承载结构26的部分RDL形式线路层261)，使该承载结构26不仅得以维持较高良率的大规格L/S的线路层261(如L/S为10/10微米)，也可减少该线路层261的配置层数(如少于五层线路层261)，以提升该承载结构26(或RDL)的制程良率，因而有效降低整体制程难度(或有效提高整体良率)及降低制作成本。
于另一实施例中，如图3所示的电子封装件3，其线路构件31的相对两侧结合并电性连接多个导电体22,32，且其中一侧形成有保护膜212，以令该保护膜212包覆该些导电体22，而另一侧形成如非导电膜(Non-Conductive Film，简称NCF)的结合层34，以令该结合层34包覆该些导电体32，故当移除该承载件9及其上的离型层90、粘着层91与金属层92后，于该绝缘层93上经由雷射方式进行开孔制程，以令该些导电体32外露于该绝缘层93的开孔，并可设置多个导电元件29于该线路构件31的导电体32及多个导电柱23上，使该多个导电元件29电性连接该多个导电柱23及该线路构件31，其中，部分该金属体290可形成于该开孔中，以接触该些导电体32。
因此，该线路构件31可设计为相对两侧皆有对外的接点，以令该线路构件31电性连接该导电元件29，使该电子元件27的部分电性路径(即该分布密集区域P以外的其它区域的电极垫270，如电源信号埠)亦可通过该线路构件31直接上下传递至该电子装置20，以缩短电性路径而提升电性表现。
本发明亦提供一种电子封装件2,3，包括：具有线路层261的承载结构26、线路构件21,31以及多个电子元件27。
所述的承载结构26定义有相对的两侧。
所述的线路构件21,31设于该承载结构26的其中一侧并电性连接该线路层261，其中，该承载结构26的垂直投影面积R3大于该线路构件21,31的垂直投影面积R1，并使该线路构件21,31未伸出该承载结构26的侧面26c。
所述的电子元件27设于该承载结构26的另一侧并电性连接该线路层261，以经由该线路层261及该线路构件21,31，使该多个电子元件27的任二者相互电性导通。
于一实施例中，该线路构件21,31为无核心层形式的布线结构。
于一实施例中，该线路构件21,31的线路配置层数大于该承载结构26的线路层261的配置层数。
于一实施例中，该线路构件21,31的线路配置层数为至少五层。
于一实施例中，该多个电子元件27具有多个电极垫270，且该线路构件21,31的布设位置对应其所电性连接的该多个电子元件27的电极垫270的分布密集区域P。
于一实施例中，该线路构件21,31相对该承载结构26的垂直投影面积R1小于该多个电子元件27中电性连接该线路构件21,31的任一电子元件27相对该承载结构26的垂直投影面积R2。
于一实施例中，该线路构件21,31于相对该承载结构26的垂直方向上重叠该多个电子元件27中电性连接该线路构件21,31的任一电子元件27的部分区域。
于一实施例中，所述的电子封装件2,3还包括多个设于该承载结构26上的导电柱23，其位于该线路构件21,31周围且电性连接该线路层261。进一步，所述的电子封装件2,3还包括一包覆该线路构件21,31与该多个导电柱23的包覆层25，且该承载结构26结合该包覆层25。例如，该包覆层25上形成有多个电性连接该导电柱23及/或该线路构件31的导电元件29。
综上所述，本发明的电子封装件及其制法中，经由该线路构件的细线路设计，以满足任两个电子元件的电极垫的间距较小处需布设高层数的RDL结构的布线需求，故本发明以小面积的该线路构件取代大面积的该承载结构的部分线路配置层数，以降低大面积的该承载结构的线路层制作的困难度，因而能达到降低制作成本及大幅提升良率的目的。
再者，经由在该线路构件周围以该包覆层填补整体结构强度，故能避免发生翘曲的问题。
另外，采用局部高配置层数(即该线路构件)配合局部低配置层数(即该承载结构)的布线设计，以减少该承载结构的线路层的配置层数，因而能有效降低整体制程难度及降低制作成本。
另外，经由进一步将该线路构件设计为上下导通的电性传递路径，以电性连接(或串接)该电子元件与该导电元件，使该电子元件可通过该线路构件对外进行信号传递，以缩短电性路径，故可提升该电子封装件的电性表现。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种电子封装件，包括：
具有线路层的承载结构，其定义有相对的两侧；
线路构件，其设于该承载结构的其中一侧并电性连接该线路层，其中，该承载结构的垂直投影面积大于该线路构件的垂直投影面积，而使该线路构件未伸出该承载结构的侧面；以及
多个电子元件，其设于该承载结构的另一侧并电性连接该线路层，以经由该线路层及该线路构件，使该多个电子元件的任二者相互电性导通。
2.如权利要求1所述的电子封装件，其中，该线路构件为无核心层形式的布线结构。
3.如权利要求1所述的电子封装件，其中，该线路构件的线路配置层数大于该承载结构的线路层的配置层数。
4.如权利要求1所述的电子封装件，其中，该线路构件的线路配置层数为至少五层。
5.如权利要求1所述的电子封装件，其中，该多个电子元件具有多个电极垫，且该线路构件的布设位置对应其所电性连接的该多个电子元件的电极垫的分布密集区域。
6.如权利要求1所述的电子封装件，其中，该线路构件相对该承载结构的垂直投影面积小于该多个电子元件中电性连接该线路构件的任一者相对该承载结构的垂直投影面积。
7.如权利要求1所述的电子封装件，其中，该线路构件于相对该承载结构的垂直方向上重叠该多个电子元件中电性连接该线路构件的任一者的部分区域。
8.如权利要求1所述的电子封装件，其中，该电子封装件还包括设于该承载结构的多个导电柱，其位于该线路构件周围且电性连接该线路层。
9.如权利要求8所述的电子封装件，其中，该电子封装件还包括一结合于该承载结构且包覆该线路构件与该多个导电柱的包覆层。
10.如权利要求9所述的电子封装件，其中，该包覆层上形成有电性连接该多个导电柱及/或该线路构件的多个导电元件。
11.一种电子封装件的制法，包括：
将具有线路层的承载结构结合于一线路构件上，其中，该承载结构的垂直投影面积大于该线路构件的垂直投影面积，而使该线路构件未伸出该承载结构的侧面；以及
设置多个电子元件于该承载结构上，使该线路构件及该多个电子元件分别位于该承载结构的不同侧，且令该多个电子元件电性连接该线路层，以经由该线路层及该线路构件，使该多个电子元件的任二者相互电性导通。
12.如权利要求11所述的电子封装件的制法，其中，该线路构件为无核心层形式的布线结构。
13.如权利要求11所述的电子封装件的制法，其中，该线路构件的线路配置层数大于该承载结构的线路层的配置层数。
14.如权利要求11所述的电子封装件的制法，其中，该线路构件的线路配置层数至少五层。
15.如权利要求11所述的电子封装件的制法，其中，该多个电子元件具有多个电极垫，且该线路构件的布设位置对应其所电性连接的该多个电子元件的电极垫的分布密集区域。
16.如权利要求11所述的电子封装件的制法，其中，该线路构件相对该承载结构的垂直投影面积小于该多个电子元件中电性连接该线路构件的任一者相对该承载结构的垂直投影面积。
17.如权利要求11所述的电子封装件的制法，其中，该线路构件于相对该承载结构的垂直方向上重叠该多个电子元件中电性连接该线路构件的任一者的部分区域。
18.如权利要求11所述的电子封装件的制法，其中，该制法还包括于该线路构件周围配置多个导电柱，且令该多个导电柱电性连接该承载结构的线路层。
19.如权利要求18所述的电子封装件的制法，其中，该制法还包括先以包覆层包覆该线路构件与该多个导电柱，再于该包覆层上形成该承载结构。
20.如权利要求19所述的电子封装件的制法，其中，该制法还包括于该包覆层上形成电性连接该多个导电柱及/或该线路构件的多个导电元件。
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