TWI788230B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TWI788230B
TWI788230B TW111106567A TW111106567A TWI788230B TW I788230 B TWI788230 B TW I788230B TW 111106567 A TW111106567 A TW 111106567A TW 111106567 A TW111106567 A TW 111106567A TW I788230 B TWI788230 B TW I788230B
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circuit
layer
electrically connected
circuit member
electronic package
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TW111106567A
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TW202335224A (zh
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張立楚
許元鴻
江東昇
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矽品精密工業股份有限公司
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Priority to TW111106567A priority Critical patent/TWI788230B/zh
Priority to CN202210252528.2A priority patent/CN116682802A/zh
Priority to US17/750,931 priority patent/US20230268262A1/en
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Publication of TWI788230B publication Critical patent/TWI788230B/zh
Publication of TW202335224A publication Critical patent/TW202335224A/zh

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Abstract

一種電子封裝件，其製法係於一具有線路層之承載結構之相對兩側上分別配置一線路構件以及複數電子元件，以藉由該線路層及該線路構件，使該複數電子元件之任二者相互電性導通，其中，該承載結構之垂直投影面積係大於該線路構件之垂直投影面積，並使該線路構件未伸出該承載結構之側面，俾藉由該線路構件取代該承載結構之部分線路層之配置層數，以降低該承載結構製作該線路層之困難度。

Description

電子封裝件及其製法
本發明係有關一種半導體封裝製程，尤指一種可提升良率之電子封裝件及其製法。
隨著科技的演進，電子產品需求趨勢朝向異質整合邁進，為此，多晶片封裝結構(MCM/MCP)逐漸興起。
圖1係習知半導體封裝件1之剖面示意圖。如圖1所示，該半導體封裝件1係將複數半導體晶片11以覆晶方式藉由複數導電凸塊12設於一扇出型(Fan-out，簡稱FO)重佈線路層(redistribution layer，簡稱RDL)式線路結構10上，再以底膠13包覆該些導電凸塊12，並以封裝層18包覆該些半導體晶片11。之後，該線路結構10以複數銲球14設於一封裝基板1a上，並以封裝材15包覆該些銲球14。
習知半導體封裝件1係將多顆半導體晶片11封裝整合成一顆晶片的功能特性，使該半導體封裝件1具有較多的接點(I/O)數與擴充單顆晶片的功能，藉此可大幅增加處理器的運算能力，以減少訊號傳遞的延遲時間，故可應用於高密度線路/高傳輸速度/高疊層數/大尺寸設計之高階產品。
惟，習知半導體封裝件1隨著半導體晶片11之整合數量增加，各半導體晶片11之接點(I/O)(即該導電凸塊12)之數量會漸增，使各該導電凸塊12之間的間距(pitch)漸小，故用以電性連接該些半導體晶片11之扇出型重佈線路層式線路結構10之佈線因需朝更細線路/細間距之規格製作而使製程困難度大幅提升，且該線路結構10之佈線層數之需求也需一併增加，致使該半導體封裝件1之整體製作成本隨著該線路結構10之製作成本增加而大幅提高，並導致該半導體封裝件1之產品良率不高。
因此，如何克服上述習知技術之問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：具有線路層之承載結構，係定義有相對之兩側；線路構件，係設於該承載結構之其中一側並電性連接該線路層，其中，該承載結構之垂直投影面積係大於該線路構件之垂直投影面積，並使該線路構件未伸出該承載結構之側面；以及複數電子元件，係設於該承載結構之另一側並電性連接該線路層，以藉由該線路層及該線路構件，使該複數電子元件之任二者相互電性導通。
本發明亦提供一種電子封裝件之製法，係包括：將具有線路層之承載結構結合於一線路構件上，其中，該承載結構之垂直投影面積係大於該線路構件之垂直投影面積，並使該線路構件未伸出該承載結構之側面；以及設置複數電子元件於該承載結構上，使該線路構件及該複數電子元件分別位於該承載結 構之不同側，且令該複數電子元件電性連接該線路層，以藉由該線路層及該線路構件，使該複數電子元件之任二者相互電性導通。
前述之電子封裝件及其製法中，該線路構件係為無核心層形式之佈線結構。
前述之電子封裝件及其製法中，該線路構件之線路配置層數係大於該承載結構之線路層之配置層數。
前述之電子封裝件及其製法中，該線路構件之線路配置層數係至少五層。
前述之電子封裝件及其製法中，該複數電子元件具有複數電極墊，且該線路構件之佈設位置係對應其所電性連接之該複數電子元件之電極墊之分佈密集區域。
前述之電子封裝件及其製法中，該線路構件相對該承載結構之垂直投影面積係小於該複數電子元件中電性連接該線路構件之任一者相對該承載結構之垂直投影面積。
前述之電子封裝件及其製法中，該線路構件於相對該承載結構之垂直方向上係重疊該複數電子元件中電性連接該線路構件之任一者的部分區域。
前述之電子封裝件及其製法中，復包括於該承載結構上配置複數導電柱，其位於該線路構件周圍且電性連接該線路層。又包括先以包覆層包覆該線路構件與該複數導電柱，再將該承載結構形成於該包覆層上。進一步，復包括於該包覆層上形成複數電性連接該導電柱及/或該線路構件之導電元件。
由上可知，本發明之電子封裝件及其製法中，主要藉由該線路構件之設計，以滿足任兩個電子元件的電極墊的間距較小處需佈設高層數線路層 之佈線需求，故相較於習知技術，本發明以小面積的該線路構件取代該承載結構之部分線路配置層數，以降低大面積的該承載結構製作該線路層之困難度，因而能達到降低製作成本及大幅提升良率之目的。
再者，本發明藉由在該線路構件之周圍以該包覆層填補整體結構強度，故能避免發生翹曲的問題。
又，採用該線路構件配合該承載結構的佈線設計，以減少該承載結構之線路層之配置層數，因而能有效降低整體製程難度及降低製作成本。
另外，藉由該線路構件電性連接該導電元件，使該電子元件可透過該線路構件對外進行訊號傳遞，以縮短電性路徑，故可提升該電子封裝件之電性表現。
1:半導體封裝件
1a:封裝基板
10:線路結構
11:半導體晶片
12,271:導電凸塊
13,272:底膠
14:銲球
15:封裝材
18,28:封裝層
2,3:電子封裝件
2a:線路板
20:電子裝置
21,31:線路構件
210:線路重佈層
211:絕緣體
212:保護膜
213:電性接觸墊
22,32:導電體
22a,23a:端面
23:導電柱
24,34:結合層
25:包覆層
26:承載結構
26c:側面
260:介電層
261:線路層
262:電性接觸墊
263:凸塊底下金屬層
27:電子元件
27a:作用面
27b:非作用面
270:電極墊
29:導電元件
29a:銲錫材料
290:金屬體
291:銅柱
9:承載件
90:離型層
91:黏著層
92:金屬層
93:絕緣層
R1,R2,R3:垂直投影面積
P:分佈密集區域
L,S:切割路徑
圖1係為習知半導體封裝件之剖視示意圖。
圖2A至圖2G係為本發明之電子封裝件之製法之剖視示意圖。
圖3係為圖2G之另一實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例 關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2G係為本發明之電子封裝件2之製法的剖面示意圖。
如圖2A所示，提供一包含有複數線路構件21之線路板2a，再沿切割路徑L切割該線路板2a，以獲取複數線路構件21。
於本實施例中，該線路構件21係為如具有核心層與佈線結構之封裝基板(substrate)或無核心層(coreless)形式之佈線結構(圖中係呈現coreless型式)，其具有絕緣體211及結合該絕緣體211之複數(本實施例之線路配置層數係至少五層)扇出(fan out)型線路重佈層(redistribution layer，簡稱RDL)210，其中，形成該絕緣體211之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材。應可理解地，該線路構件21亦可為其它配置佈線之板體，如有機板材(organic material)、半導體板材(silicon)、陶瓷板材(ceramic)或其它具有金屬佈線(routing)之載板，並不限於上述。
再者，該線路構件21之其中一側係結合並電性連接複數導電體22，且該導電體22係為如導電線路、銲球之圓球狀、或如銅柱、銲錫凸塊等金屬材之柱狀、或銲線機製作之釘狀(stud)，但不限於此。進一步，該導電體22形成於最外層之線路重佈層210之電性接觸墊213上，且該線路構件21之表面可形 成有一如絕緣材之保護膜212，以包覆該些導電體22之部分表面，並使該導電體22之端面齊平及外露於該保護膜212。
如圖2B所示，將至少一線路構件21設於一承載件9上，且於該承載件9上形成複數導電柱23，其中，該線路構件21與該導電柱23之設置順序可依需求選擇先後順序，且該複數導電柱23係位於該線路構件21周圍。
於本實施例中，該承載件9例如為半導體材質(如矽或玻璃)之板體，其上以例如塗佈方式依序形成有一離型層90、一黏著層91、一金屬層92與一如介電材之絕緣層93。例如，形成該絕緣層93之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材。
再者，形成該導電柱23之材質係為如銅之金屬材或銲錫材，且該導電柱23係延伸穿過該絕緣層93以接觸該金屬層92。例如，藉由曝光顯影方式，於該絕緣層93上係形成複數外露該金屬層92之開口，以藉由該金屬層92從該開口中電鍍形成該些導電柱23。
另外，該線路構件21係以其另一側藉由一如晶片黏結薄膜(Die Attach Film，簡稱DAF)之結合層24黏固於該絕緣層93上。
如圖2C所示，形成一包覆層25於該絕緣層93上，以令該包覆層25包覆該線路構件21、結合層24、該保護膜212與該複數導電柱23，再藉由整平製程，令該導電柱23之端面23a與該導電體22之端面22a外露於該包覆層25，使該包覆層25之外表面齊平該導電柱23之端面23a與該導電體22之端面22a。
於本實施例中，該包覆層25係為絕緣材，如環氧樹脂之封裝膠體，其可用壓合(lamination)或模壓(molding)之方式形成於該承載件9上。
再者，該整平製程係藉由研磨方式，移除該導電柱23之部分材質、該導電體22之部分材質、該保護膜212之部分材質與該包覆層25之部分材質。
如圖2D所示，將一具有線路層261之承載結構26形成於該包覆層25上，且該承載結構26之線路層261電性連接該複數導電柱23與該線路構件21之複數導電體22。
於本實施例中，該承載結構26係包括複數介電層260及設於該介電層260上之複數RDL規格之線路層261，且最外層之介電層260可作為防銲層，且令最外層之線路層261外露於該防銲層，俾供作為電性接觸墊262，如微墊(micro pad，俗稱μ-pad)。或者，該承載結構26亦可僅包括單一介電層260及單一線路層261。例如，該線路構件21之線路配置層數(至少五層)係大於該承載結構26之線路層261之配置層數(如本實施例圖示之三層)。因此，藉由小面積的該線路構件21係可調配大面積或晶圓級(wafer form)的該線路層261之配置層數，使大面積的該線路層261之配置層數降低，以提高大面積的該承載結構26之製作良率。
再者，形成該線路層261之材質係為銅，且形成該介電層260之材質係為如聚對二唑苯(PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材、或如綠漆、油墨等之防銲材。
如圖2E所示，於該承載結構26之最外層之線路層261上接置複數電子元件27，且該複數電子元件27電性連接該線路層261，以藉由該線路層261及該線路構件21，使該複數電子元件27之任二者相互電性導通，即該線路構件21係電性橋接任二電子元件27，其中，該線路構件21相對該承載結構26之垂直投影面 積R1係小於該複數電子元件27中電性連接該線路構件21之任一電子元件27相對該承載結構26之垂直投影面積R2。之後，再以一封裝層28包覆該些電子元件27。
於本實施例中，該電子元件27係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該電子元件27係為半導體晶片，其具有相對之作用面27a與非作用面27b，且以其作用面27a之電極墊270藉由複數如銲錫材料之導電凸塊271採用覆晶方式設於該電性接觸墊262上並電性連接該線路層261，並可形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)263於該電性接觸墊262上，以利於結合該導電凸塊271；或者，該電子元件27以其非作用面27b設於該承載結構26上，並可藉由複數銲線(圖略)以打線方式電性連接該電性接觸墊262；亦或透過如導電膠或銲錫等導電材料(圖略)電性連接該線路層261。然而，有關該電子元件27電性連接該線路層261之方式不限於上述。
又，該封裝層28係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該承載結構26上。應可理解地，形成該包覆層25及封裝層28之材質可相同或相異。
另外，該封裝層28可直接包覆該些導電凸塊271；或者，可先形成底膠272於該電子元件27與該承載結構26之間以包覆該些導電凸塊271，再形成該封裝層28以包覆該底膠272與該電子元件27。
如圖2F所示，剝除該承載件9及其上之離型層90，再蝕刻移除該黏著層91與金屬層92，以令該複數導電柱23外露於該絕緣層93，供設置複數導電元件29於該複數導電柱23上，使該複數導電元件29電性連接該複數導電柱23，其 中，該導電元件29係包含一形成於該絕緣層93上以接觸該些導電柱23之墊狀金屬體(如UBM)290、及複數設結合該金屬體290之銅柱291，以於該銅柱291之端面上形成如銲錫凸塊或銲球之銲錫材料29a。
於本實施例中，該線路構件21之佈設位置係對應其所電性連接之該複數電子元件27之電極墊270之分佈密集區域P，使該線路構件21之線路重佈層210之線寬小於2微米。例如，該線路構件21之佈線規格係為至多2微米的線寬/線距(L/S)(即L/S≦2/2μm)，且該電子元件27作為接點(I/O)之電極墊270之數量較多且密集之處係定義為分佈密集區域P，並使該分佈密集區域P之電極墊270電性連接該線路構件21。
再者，該線路構件21於相對該承載結構26之垂直方向上係重疊該複數電子元件27中電性連接該線路構件21之任一電子元件27的部分區域。例如，該線路構件21係重疊其所電性橋接之該電子元件27之部分區域，以令該線路構件21相對該電子元件27的配置位置可對應疊合於該電子元件27之電極墊270之分佈密集區域P上。
如圖2G所示，沿如圖2F所示之切割路徑S進行切單製程，以形成一電子封裝件2，且於後續製程中，該電子封裝件2可藉由該些導電元件29接置於一如封裝基板或如電路板之電子裝置20上。
於本實施例中，該承載結構26之垂直投影面積R3係大於該線路構件21(或多個線路構件21之任一者)之垂直投影面積R1，並使該線路構件21(或多個線路構件21之任一者)未伸出該承載結構26之側面26c。
因此，本發明之製法中，主要藉由該線路構件21之細線路設計，使該些電子元件27中較小間距的接點(I/O)(即該分佈密集區域P之電極墊270)能 透過該線路構件21與該承載結構26之配合作為該些電子元件27相互電性導通的路徑，以滿足任兩個電子元件27中的電極墊270的間距較小處需佈設高層數的RDL結構(如該線路構件21之五層線路配置層數)之佈線需求，故相較於習知技術之一次需鋪設整面式的扇出型重佈線路層的電性導通之設計，本發明之製法以小面積的該線路構件21取代大面積的該承載結構26之部分線路層261，以降低用以接置該分佈密集區域P的大面積線路層261之RDL佈線層數，進而降低製作困難度，因而能達到降低製作成本及大幅提升良率之目的。
再者，藉由該線路構件21的尺寸為可調式之設計，可平衡該電子封裝件2之應力分佈，故相較於習知技術，本發明採用局部(partial)RDL規格之線路構件21，以於切割該線路板2a時，即可配合結構需求的翹曲(warpage)程度來調整該線路構件21的尺寸，因而當該電子封裝件2之面積為大尺寸規格時，能明顯改善該電子封裝件2的翹曲(warpage)程度，以提升該電子封裝件2之可靠度。另外，為了進一步提升該電子封裝件2之可靠度，可在該線路構件21周圍藉由強度較高的材質(即該包覆層25)填補整體結構強度，以進一步降低發生翹曲(warpage)的風險。
又，由於該些電子元件27中較大間距的接點(即該分佈密集區域P以外之其它區域之電極墊270)之處只需低層數之佈線需求，因而透過該承載結構26與導電柱23之配合，即可進行電性傳遞，故本發明之製法係採用局部高配置層數(線路構件21)配合局部低配置層數(承載結構26)的佈線設計(即該線路構件21取代該承載結構26之部分RDL形式線路層261)，使該承載結構26不僅得以維持較高良率的大規格L/S之線路層261(如L/S為10/10微米)，也可減少該線路層261之配置層數(如少於五層線路層261)，以提升該承載結構26(或RDL) 的製程良率，因而有效降低整體製程難度(或有效提高整體良率)及降低製作成本。
於另一實施例中，如圖3所示之電子封裝件3，其線路構件31之相對兩側係結合並電性連接複數導電體22,32，且其中一側形成有保護膜212，以令該保護膜212包覆該些導電體22，而另一側形成如非導電膜(Non-Conductive Film，簡稱NCF)之結合層34，以令該結合層34包覆該些導電體32，故當移除該承載件9及其上之離型層90、黏著層91與金屬層92後，於該絕緣層93上藉由雷射方式進行開孔製程，以令該些導電體32外露於該絕緣層93之開孔，並可設置複數導電元件29於該線路構件31之導電體32及複數導電柱23上，使該複數導電元件29電性連接該複數導電柱23及該線路構件31，其中，部分該金屬體290可形成於該開孔中，以接觸該些導電體32。
因此，該線路構件31可設計為相對兩側皆有對外之接點，以令該線路構件31電性連接該導電元件29，使該電子元件27之部分電性路徑(即該分佈密集區域P以外之其它區域之電極墊270，如電源訊號埠)亦可透過該線路構件31直接上下傳遞至該電子裝置20，以縮短電性路徑而提升電性表現。
本發明亦提供一種電子封裝件2,3，係包括：具有線路層261之承載結構26、線路構件21,31以及複數電子元件27。
所述之承載結構26係定義有相對之兩側。
所述之線路構件21,31係設於該承載結構26之其中一側並電性連接該線路層261，其中，該承載結構26之垂直投影面積R3係大於該線路構件21,31之垂直投影面積R1，並使該線路構件21,31未伸出該承載結構26之側面26c。
所述之電子元件27係設於該承載結構26之另一側並電性連接該線路層261，以藉由該線路層261及該線路構件21,31，使該複數電子元件27之任二者相互電性導通。
於一實施例中，該線路構件21,31係為無核心層形式之佈線結構。
於一實施例中，該線路構件21,31之線路配置層數係大於該承載結構26之線路層261之配置層數。
於一實施例中，該線路構件21,31之線路配置層數係至少五層。
於一實施例中，該複數電子元件27具有複數電極墊270，且該線路構件21,31之佈設位置係對應其所電性連接之該複數電子元件27之電極墊270之分佈密集區域P。
於一實施例中，該線路構件21,31相對該承載結構26之垂直投影面積R1係小於該複數電子元件27中電性連接該線路構件21,31之任一電子元件27相對該承載結構26之垂直投影面積R2。
於一實施例中，該線路構件21,31於相對該承載結構26之垂直方向上係重疊該複數電子元件27中電性連接該線路構件21,31之任一電子元件27的部分區域。
於一實施例中，所述之電子封裝件2,3復包括複數設於該承載結構26上之導電柱23，其位於該線路構件21,31周圍且電性連接該線路層261。進一步，所述之電子封裝件2,3復包括一包覆該線路構件21,31與該複數導電柱23之包覆層25，且該承載結構26係結合該包覆層25。例如，該包覆層25上係形成有複數電性連接該導電柱23及/或該線路構件31之導電元件29。
綜上所述，本發明之電子封裝件及其製法中，係藉由該線路構件之細線路設計，以滿足任兩個電子元件的電極墊的間距較小處需佈設高層數的RDL結構之佈線需求，故本發明以小面積的該線路構件取代大面積的該承載結構之部分線路配置層數，以降低大面積的該承載結構之線路層製作之困難度，因而能達到降低製作成本及大幅提升良率之目的。
再者，藉由在該線路構件周圍以該包覆層填補整體結構強度，故能避免發生翹曲的問題。
又，採用局部高配置層數(即該線路構件)配合局部低配置層數(即該承載結構)的佈線設計，以減少該承載結構之線路層之配置層數，因而能有效降低整體製程難度及降低製作成本。
另外，藉由進一步將該線路構件設計為上下導通的電性傳遞路徑，以電性連接(或串接)該電子元件與該導電元件，使該電子元件可透過該線路構件對外進行訊號傳遞，以縮短電性路徑，故可提升該電子封裝件之電性表現。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
20:電子裝置
21:線路構件
22:導電體
23:導電柱
24:結合層
25:包覆層
26:承載結構
26c:側面
261:線路層
27:電子元件
28:封裝層
29:導電元件
29a:銲錫材料
93:絕緣層
R1,R3:垂直投影面積

Claims (18)

  1. 一種電子封裝件，係包括：具有線路層之承載結構，係定義有相對之兩側；線路構件，係設於該承載結構之其中一側並電性連接該線路層，其中，該承載結構之垂直投影面積係大於該線路構件之垂直投影面積，而使該線路構件未伸出該承載結構之側面；以及複數電子元件，係設於該承載結構之另一側並電性連接該線路層，以藉由該線路層及該線路構件，使該複數電子元件之任二者相互電性導通，其中，該複數電子元件具有複數電極墊，且該線路構件之佈設位置係對應其所電性連接之該複數電子元件之該複數電極墊之分佈密集區域。
  2. 如請求項1所述之電子封裝件，其中，該線路構件係為無核心層形式之佈線結構。
  3. 如請求項1所述之電子封裝件，其中，該線路構件之線路配置層數係大於該承載結構之線路層之配置層數。
  4. 如請求項1所述之電子封裝件，其中，該線路構件之線路配置層數係至少五層。
  5. 如請求項1所述之電子封裝件，其中，該線路構件相對該承載結構之垂直投影面積係小於該複數電子元件中電性連接該線路構件之任一者相對該承載結構之垂直投影面積。
  6. 如請求項1所述之電子封裝件，其中，該線路構件於相對該承載結構之垂直方向上係重疊該複數電子元件中電性連接該線路構件之任一者的部分區域。
  7. 如請求項1所述之電子封裝件，復包括設於該承載結構之複數導電柱，其位於該線路構件周圍且電性連接該線路層。
  8. 如請求項7所述之電子封裝件，復包括一結合於該承載結構且包覆該線路構件與該複數導電柱之包覆層。
  9. 如請求項8所述之電子封裝件，其中，該包覆層上係形成有電性連接該複數導電柱及/或該線路構件之複數導電元件。
  10. 一種電子封裝件之製法，係包括：將具有線路層之承載結構結合於一線路構件上，其中，該承載結構之垂直投影面積係大於該線路構件之垂直投影面積，而使該線路構件未伸出該承載結構之側面；以及設置複數電子元件於該承載結構上，使該線路構件及該複數電子元件分別位於該承載結構之不同側，且令該複數電子元件電性連接該線路層，以藉由該線路層及該線路構件，使該複數電子元件之任二者相互電性導通，其中，該複數電子元件具有複數電極墊，且該線路構件之佈設位置係對應其所電性連接之該複數電子元件之該複數電極墊之分佈密集區域。
  11. 如請求項10所述之電子封裝件之製法，其中，該線路構件係為無核心層形式之佈線結構。
  12. 如請求項10所述之電子封裝件之製法，其中，該線路構件之線路配置層數係大於該承載結構之線路層之配置層數。
  13. 如請求項10所述之電子封裝件之製法，其中，該線路構件之線路配置層數係至少五層。
  14. 如請求項10所述之電子封裝件之製法，其中，該線路構件相對該承載結構之垂直投影面積係小於該複數電子元件中電性連接該線路構件之任一者相對該承載結構之垂直投影面積。
  15. 如請求項10所述之電子封裝件之製法，其中，該線路構件於相對該承載結構之垂直方向上係重疊該複數電子元件中電性連接該線路構件之任一者的部分區域。
  16. 如請求項10所述之電子封裝件之製法，復包括於該線路構件周圍配置複數導電柱，且令該複數導電柱電性連接該承載結構之線路層。
  17. 如請求項16所述之電子封裝件之製法，復包括先以包覆層包覆該線路構件與該複數導電柱，再於該包覆層上形成該承載結構。
  18. 如請求項17所述之電子封裝件之製法，復包括於該包覆層上形成電性連接該複數導電柱及/或該線路構件之複數導電元件。
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TW201820579A (zh) * 2016-11-16 2018-06-01 矽品精密工業股份有限公司 電子裝置及其製法與基板結構
TW202042368A (zh) * 2019-05-03 2020-11-16 矽品精密工業股份有限公司 電子封裝件及其承載基板與製法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201820579A (zh) * 2016-11-16 2018-06-01 矽品精密工業股份有限公司 電子裝置及其製法與基板結構
TW202042368A (zh) * 2019-05-03 2020-11-16 矽品精密工業股份有限公司 電子封裝件及其承載基板與製法

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