TW202115855A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW202115855A
TW202115855A TW108136264A TW108136264A TW202115855A TW 202115855 A TW202115855 A TW 202115855A TW 108136264 A TW108136264 A TW 108136264A TW 108136264 A TW108136264 A TW 108136264A TW 202115855 A TW202115855 A TW 202115855A
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Taiwan
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electronic
circuit layer
electronic component
electrically connected
package
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TW108136264A
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English (en)
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TWI766192B (zh
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廖信一
張正楷
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矽品精密工業股份有限公司
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Priority to TW108136264A priority Critical patent/TWI766192B/zh
Priority to CN201911010459.9A priority patent/CN112701101A/zh
Priority to US16/686,995 priority patent/US11114412B2/en
Publication of TW202115855A publication Critical patent/TW202115855A/zh
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Publication of TWI766192B publication Critical patent/TWI766192B/zh

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Abstract

一種電子封裝件係包括：一具有第一線路層之第一承載結構、配置於該第一承載結構上且電性連接該第一線路層之封裝模組、配置於該第一承載結構上且電性連接該第一線路層之第一電子元件、以及堆疊於該第一電子元件上且電性連接該第一電子元件之第二電子元件，以藉由該第一電子元件與第二電子元件相堆疊之設計，而減少該些電子元件佔用該第一承載結構之表面面積，故能有足夠的空間放置該封裝模組。本發明復提供一種電子封裝件之製法。

Description

電子封裝件及其製法
本發明係關於一種半導體封裝製程，特別是關於一種電子封裝件及其製法。
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態。為滿足半導體裝置之高積集度(Integration)、微型化(Miniaturization)以及高電路效能等需求，遂而發展出覆晶(Flip chip)接合封裝技術。
覆晶接合封裝技術係為一種以晶片(或其它半導體結構)的作用面上形成複數金屬凸塊，以藉由該些金屬凸塊使該晶片的作用面得電性連接至外部電子裝置或封裝基板，此種設計可大幅縮減整體封裝件的體積。
如第1A及1B圖所示，於習知覆晶式半導體封裝件1之製程中，係先將一半導體晶片11藉由複數銲錫凸塊13結合至一封裝基板10上，再形成底膠12於該半導體晶片11與該封裝基板10之間，以包覆該些 銲錫凸塊13。之後，於該封裝基板10下側植設複數銲球14以接置於電子產品之運算主板(major board)8上。
惟，習知半導體封裝件1中，該封裝基板10的表面若需同時水平排設許多半導體晶片11，將佔據該封裝基板10過多之表面面積，故無法有足夠的空間放置其它封裝模組。另一方面，若將該封裝基板10的表面面積擴增，將迫使該半導體封裝件1的體積增大，導致該半導體封裝件1不符合輕薄短小之發展潮流。
再者，該封裝基板10係為一般有機基板或核心基板，其受限於製程，而只能製作單一線寬/線距規格之線路，故難以同時滿足不同電子元件所需之不同線路規格。例如，微小化功能晶片需配置於較細小之線寬/線距規格之線路上，電源埠與接地埠需形成於較寬大之線寬/線距規格之線路上。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種電子封裝件，係包括：第一承載結構，係定義有相對之第一表面與第二表面並具有第一線路層；封裝模組，係配置於該第一承載結構之第一表面上且電性連接該第一線路層；第一電子元件，係配置於該第一承載結構之第一表面上且電性連接該第一線路層；以及第二電子元件，係堆疊於該第一電子元件上且電性連接該第一電子元件。
本發明復提供一種電子封裝件之製法，係包括：提供一第一承載結構，其具有第一線路層並定義有相對之第一表面與第二表面；以及將封裝模組、第一電子元件與第二電子元件配置於該第一承載結構之第一表面上，其中，該封裝模組與該第一電子元件係電性連接該第一線路層，且該第二電子元件係堆疊於該第一電子元件上並電性連接該第一電子元件。
前述之電子封裝件及其製法中，該封裝模組係包含：具有第二線路層之第二承載結構，係藉由複數導電體設於該第一承載結構之第一表面上，且該複數導電體電性連接該第一線路層與第二線路層；至少一功能電子元件，係配置於該第二承載結構上且電性連接該第二線路層；以及封裝層，係包覆該功能電子元件。例如，該第一線路層之線路規格不同於該第二線路層之線路規格。或者，該第一線路層之線寬/線距係大於該第二線路層之線寬/線距。
前述之電子封裝件及其製法中，該第一電子元件係藉由銲線電性連接該第一線路層。
前述之電子封裝件及其製法中，該第二電子元件係藉由導電凸塊電性連接該第一電子元件。
前述之電子封裝件及其製法中，復包括形成包覆層於該第一承載結構之第一表面上，以令該包覆層包覆該第一電子元件與第二電子元件。例如，該第二電子元件之部分表面外露於該包覆層。或者，該包覆層復包覆該封裝模組。
前述之電子封裝件及其製法中，復包括形成複數導電元件於該第一承載結構之第二表面上，且該複數導電元件電性連接該第一線路層。
由上可知，本發明之電子封裝件及其製法中，主要藉由將該第一電子元件與該第二電子元件相堆疊，以減少該些電子元件佔用該第一承載結構的第一表面之面積，故相較於習知技術，本發明之電子封裝件不僅能有足夠的空間放置封裝模組，且有利於縮減應用該電子封裝件之電子產品之體積，使該電子產品符合輕薄短小之發展趨勢。
再者，藉由形成兩種線路規格之第一線路層與該第二線路層，使微小化晶片規格之功能電子元件能藉由該第二線路層電性連接至第一線路層。
又，本發明之製法係將該第一線路層製作成電源接點與接地接點所需之線寬/線距，因而該第一電子元件可電性連接該第一線路層，而無需將所有線路製作成如第二線路層之線寬/線距，故相較於習知技術之單一線路規格，本發明之製法較節省成本。
另外，該第一電子元件與第二電子元件係以「作用面相接」之方式相互電性連接，以縮短電性傳輸路徑，故本發明之電子封裝件能增快訊號傳輸速度。
1‧‧‧半導體封裝件
10‧‧‧封裝基板
11‧‧‧半導體晶片
12‧‧‧底膠
13‧‧‧銲錫凸塊
14‧‧‧銲球
2,2’,2”‧‧‧電子封裝件
2a‧‧‧封裝模組
20‧‧‧第一承載結構
20a‧‧‧第一表面
20b‧‧‧第二表面
200‧‧‧絕緣層
201‧‧‧第一線路層
21‧‧‧第二承載結構
210‧‧‧絕緣體
211‧‧‧第二線路層
22‧‧‧功能電子元件
220‧‧‧導電凸塊
23‧‧‧封裝層
24‧‧‧導電體
240‧‧‧結合材
25‧‧‧第一電子元件
25a,26a‧‧‧作用面
25b,26b‧‧‧非作用面
250,250’,260‧‧‧電極墊
251‧‧‧黏著材
26‧‧‧第二電子元件
27a‧‧‧銲線
27b‧‧‧導電凸塊
28‧‧‧包覆層
28a‧‧‧表面
29‧‧‧導電元件
8‧‧‧運算主板
9‧‧‧支撐件
第1A至1B圖係為習知覆晶式半導體封裝件之製法之剖視示意圖。
第2A至2E圖係為本發明之電子封裝件之製法之剖面示意圖。
第2C’圖係為第2C圖之另一製程之剖面示意圖。
第2E’及2E”圖係為第2E圖之其它實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之電子封裝件2之製法之剖視示意圖。
如第2A圖所示，提供一第一承載結構20，例如，該第一承載結構20係設於一支撐件9上。
於本實施例中，該第一承載結構20係為整版面基板形式，即該整版面基板包含複數基板單元，該第一承載結構20例如為具有核心層與線路結構之封裝基板或無核心層(coreless)之線路結構，其具有相對之第一表面20a與第二表面20b，且該線路結構係包含至少一絕緣層200及至少一結合該絕緣層200之第一線路層201，如至少一扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)。應可理解地，該第一承載結構20亦 可為其它承載晶片之板材，如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之載板等，並不限於上述。
於本實施例中，該第一承載結構20之製程方式繁多，例如，可採用晶圓製程製作線路層，而以化學氣相沉積(Chemical vapor deposition，簡稱CVD)形成氮化矽或氧化矽以作為絕緣層；或者，可採用一般非晶圓製程方式形成線路層，即採用成本較低之高分子介電材作為絕緣層，如聚醯亞胺(Polyimide，簡稱PI)、聚對二唑苯(Polybenzoxazole，簡稱PBO)、預浸材(Prepreg，簡稱PP)、封裝膠體(molding compound)、感光型介電層或其它材質等以塗佈方式形成之。
又，該第一線路層201之線路規格係為線寬及線距(L/S)大於2微米(um)以上。
另外，該支撐件9係為玻璃板、晶圓板或其它適當板體。
如第2B圖所示，將一封裝模組2a設於該第一承載結構20之第一表面20a上，且令該封裝模組2a電性連接該第一線路層201。
於本實施例中，該封裝模組2a係包含一第二承載結構21、至少一設於該第二承載結構21之功能電子元件22、及一包覆該功能電子元件22之封裝層23，且該第二承載結構21藉由複數導電體24設於該第一承載結構20之第一表面20a上並藉由該些導電體24電性連接該第一線路層201。
所述之第二承載結構21係例如為具有核心層與線路結構之封裝基板或無核心層(coreless)之線路結構，其包含有絕緣體210及結合該絕緣體210之第二線路層211(如至少一扇出(fan out)型重佈線路層(RDL))。應可理解地，該第二承載結構21亦可為其它承載晶片之板材，如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之載板等，並不限於上述。具體地，該第二承載結構21之製程方式繁多，例如， 可採用晶圓製程製作線路層，而以化學氣相沉積(CVD)形成氮化矽或氧化矽以作為絕緣層；或者，可採用一般非晶圓製程方式形成線路層，即採用成本較低之高分子介電材作為絕緣體，如聚醯亞胺(PI)、聚對二唑苯(PBO)、預浸材(PP)、封裝膠體、感光型介電層或其它等以塗佈方式形成之。
再者，該第一線路層201之線路規格不同於該第二線路層211之線路規格。例如，該第二線路層211係以重佈線路(Redistribution Layers，簡稱RDL)製程製作，其線寬/線距係為小於或等於2um，故該第一線路層201之線寬/線距係大於該第二線路層211之線寬/線距。
所述之功能電子元件22係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該功能電子元件22係為半導體晶片，其可藉由複數如銲錫材料、金屬柱(pillar)或其它等之導電凸塊220以覆晶方式設於該第二承載結構21上側並電性連接該第二線路層211；或者，該功能電子元件22可藉由複數銲線以打線方式電性連接該第二線路層211；亦或，該功能電子元件22可直接接觸該第二線路層211。
所述之封裝層23復包覆該些導電凸塊220，且該封裝層23係為絕緣材，如聚醯亞胺(PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)、塗佈(coating)或模壓(molding)之方式形成於該第二承載結構21上。例如，該封裝層23可露出(如第2B圖所示)或覆蓋(圖未示)該功能電子元件22。
所述之導電體24係為如銅柱狀之金屬凸塊、銲錫材、金屬針或其它導電構造，其形成於該第二承載結構21下側，並於該第一承載結 構20與第二承載結構21之間形成如底膠之結合材240以包覆該些導電體24並固定該封裝模組2a。
如第2C圖所示，設置第一電子元件25與第二電子元件26於該第一承載結構20之第一表面20a上。
於本實施例中，該第二電子元件26係堆疊於該第一電子元件25上。
所述之第一電子元件25係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第一電子元件25係為半導體晶片，其具有相對之作用面25a與非作用面25b，其以非作用面25b藉由黏著材251設於該第一承載結構20之第一表面20a上，並於該作用面25a之部分電極墊250上藉由複數銲線27a以打線方式電性連接該第一線路層201。
所述之第二電子元件26係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第二電子元件26係為半導體晶片，其具有相對之作用面26a與非作用面26b，其以作用面26a設於該第一電子元件25之作用面25a上，並使其電極墊260藉由複數導電凸塊27b以覆晶方式電性連接該第一電子元件25之其它電極墊250’。於其他實施例中，第二電子元件26的電極墊260與第一電子元件25的電極墊250’可直接接合而無需導電凸塊。
因此，該第一電子元件25與第二電子元件26係以「作用面25a,26a相接」之方式相互疊置。
再者，該第一電子元件25與第二電子元件26之設置方式繁多。具體地，如第2C’圖所示，可先將該第一電子元件25與第二電子元件26 相互接合，再設於該第一承載結構20上，之後再進行打線作業。或者，可先將該第一電子元件25與第二電子元件26依序配置，且於配置該第二電子元件26之前或之後，進行打線作業。
又，於其它實施例中，該第一電子元件25亦可以覆晶方式電性連接該第一線路層201，而該第二電子元件26亦可以打線方式電性連接該第一電子元件25。
應可理解地，可於該第一承載結構20之第一表面20a與第二表面20b接置任意形式、種類或數量之電子元件，以提升其電性功能，且有關電子元件之電性連接方式繁多，並不限於上述。
同理地，有關該封裝模組2a、第一電子元件25與第二電子元件26之配置順序亦可依需求設計，其製程之先後順序並不限於上述。
如第2D圖所示，形成一包覆層28於該第一承載結構20之第一表面20a上，以令該包覆層28包覆該第一電子元件25、第二電子元件26、銲線27a與導電凸塊27b。
於本實施例中，該包覆層28接觸該第一承載結構20之第一表面20a，且形成該包覆層28之材質係為絕緣材，如聚醯亞胺(PI)、環氧樹脂(epoxy)之封裝膠體或封裝材，其可用模壓(molding)方式形成。
再者，形成該包覆層28之材質係相同或不同形成該封裝層23之材質。
又，該第二電子元件26未外露於該包覆層28之表面28a，但可依需求移除該包覆層28之部分材質，以露出該第二電子元件26之非作用面26b。例如，藉由如研磨方式之整平製程移除該包覆層28之部分材質，使該第二電子元件26之非作用面26b齊平該包覆層28之表面28a，如第2E’圖所示之電子封裝件2’。或者，以如雷射之鑽孔方式於該包覆層28之表面28a 上形成複數外露該第二電子元件26之開孔。亦或，可於移除該包覆層28之部分材質後，使該第二電子元件26之非作用面26b凸出該包覆層28之表面28a。應可理解地，有關該電子元件外露出該包覆層28之方式繁多，並不限於上述。
另外，由於該封裝模組2a已配置有該封裝層23，故該包覆層28未包覆該封裝模組2a。然而，於另一實施例中，如第2E”圖所示，亦可依需求令該包覆層28包覆該封裝模組2a。
如第2E圖所示，移除該支撐件9，以外露出該第一承載結構20之第二表面20b，且可依需求進行切單製程，以得到電子封裝件2，並形成複數導電元件29於該第一承載結構20之第二表面20b上，以供該電子封裝件2接置於一如電路板之電子裝置(圖略)。
於本實施例中，該導電元件29係電性連接該第一承載結構20之第一線路層201，其可為如銅柱之金屬柱、包覆有絕緣塊之金屬凸塊、銲球(solder ball)、具有核心銅球(Cu core ball)之銲球或其它適當導電構造等，且其形狀並未有特殊限制，如圓柱體、橢圓柱體或多邊形柱體皆可。
本發明之電子封裝件2,2’,2”之製法中，主要藉由將該第一電子元件25與該第二電子元件26相堆疊，以減少該些電子元件佔用該第一承載結構20的第一表面20a之面積，故相較於習知技術，本發明之電子封裝件2,2’,2”不僅能有足夠的空間放置封裝模組2a或其它分立元件(discrete component)(圖未示)，且有利於縮減應用該電子封裝件2,2’之電子產品之體積，使該電子產品符合輕薄短小之發展趨勢。
再者，藉由兩次扇出型之線路重佈層製程(即該第一線路層201與該第二線路層211)，使微小化晶片(即符合微小化之規格需求之功能電子元件22)能藉由該第二線路層211電性連接至第一線路層201。
又，本發明之製法係將該第一線路層201製作成電源接點與接地接點所需之線寬/線距，因而該第一電子元件25可電性連接該第一線路層201(線寬/線距為2~10um)，而無需將所有線路製作成如第二線路層211之線寬/線距(其為2um以內)，故相較習知技術之所有線路層之線寬/線距皆為2um以內，本發明之製法較節省成本。
另外，該第一電子元件25與第二電子元件26係以「作用面25a,26a相接」之方式相互電性連接，以縮短電性傳輸路徑，故相較於習知技術，本發明之電子封裝件2,2’,2”能增快訊號傳輸速度。
本發明復提供一種電子封裝件2,2’,2”，其包括：一具有第一線路層201之第一承載結構20、一封裝模組2a、一第一電子元件25以及一第二電子元件26。
所述之第一承載結構20係定義有相對之第一表面20a與第二表面20b。
所述之封裝模組2a係配置於該第一承載結構20之第一表面20a上且電性連接該第一線路層201，其中，該封裝模組2a係包含：一具有第二線路層211之第二承載結構21，係藉由複數導電體24設於該第一承載結構20之第一表面20a上，且該複數導電體24電性連接該第一線路層201與第二線路層211；至少一功能電子元件22，係配置於該第二承載結構21上且電性連接該第二線路層211；以及一封裝層23，係包覆該功能電子元件22。
所述之第一電子元件25係配置於該第一承載結構20之第一表面20a上且電性連接該第一線路層201。
所述之第二電子元件26係堆疊於該第一電子元件25上且電性連接該第一電子元件25。
於一實施例中，該第一線路層201之線路規格不同於該第二線路層211之線路規格。
於一實施例中，該第一線路層201之線寬/線距係大於該第二線路層211之線寬/線距。
於一實施例中，該第一電子元件25係藉由複數銲線27a電性連接該第一線路層201。
於一實施例中，該第二電子元件26係藉由複數導電凸塊27b電性連接該第一電子元件25。
於一實施例中，所述之電子封裝件2,2’,2”復包括一包覆層28，係形成於該第一承載結構20之第一表面20a上以包覆該第一電子元件25與第二電子元件26。例如，該電子封裝件2’之第二電子元件26之非作用面26b外露於該包覆層28。或者，於該電子封裝件2”中，該包覆層28復包覆該封裝模組2a。
於一實施例中，所述之電子封裝件2,2’,2”復包括複數導電元件29，係形成於該第一承載結構20之第二表面20b上且電性連接該第一線路層201。
綜上所述，本發明之電子封裝件及其製法，主要藉由將該第一電子元件與該第二電子元件相堆疊，以減少該些電子元件佔用該第一承載結構的第一表面之面積，故本發明之電子封裝件不僅能有足夠的空間放 置封裝模組，且有利於縮減應用該電子封裝件之電子產品之體積，使該電子產品符合輕薄短小之發展趨勢。
再者，藉由形成兩種線路規格之第一線路層與該第二線路層，使微小化晶片規格之功能電子元件能藉由該第二線路層電性連接至第一線路層。
又，本發明之製法係將該第一線路層製作成電源接點與接地接點所需之線寬/線距，因而該第一電子元件可電性連接該第一線路層，而無需將所有線路製作成如第二線路層之線寬/線距，故本發明之製法較節省成本。
另外，該第一電子元件與第二電子元件係以「作用面相接」之方式相互電性連接，以縮短電性傳輸路徑，故本發明之電子封裝件能增快訊號傳輸速度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
2a‧‧‧封裝模組
20‧‧‧第一承載結構
20a‧‧‧第一表面
20b‧‧‧第二表面
201‧‧‧第一線路層
25‧‧‧第一電子元件
26‧‧‧第二電子元件
28‧‧‧包覆層
29‧‧‧導電元件

Claims (20)

  1. 一種電子封裝件，係包括：第一承載結構，係定義有相對之第一表面與第二表面並具有第一線路層；封裝模組，係配置於該第一承載結構之第一表面上且電性連接該第一線路層；第一電子元件，係配置於該第一承載結構之第一表面上且電性連接該第一線路層；以及第二電子元件，係堆疊於該第一電子元件上且電性連接該第一電子元件。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該封裝模組係包含：第二承載結構，係具有第二線路層並藉由複數導電體設於該第一承載結構之第一表面上，且該複數導電體電性連接該第一線路層與第二線路層；至少一功能電子元件，係配置於該第二承載結構上且電性連接該第二線路層；以及封裝層，係包覆該功能電子元件。
  3. 如申請專利範圍第2項所述之電子封裝件，其中，該第一線路層之線路規格不同於該第二線路層之線路規格。
  4. 如申請專利範圍第2項所述之電子封裝件，其中，該第一線路層之線寬/線距係大於該第二線路層之線寬/線距。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該第一 電子元件係藉由銲線電性連接該第一線路層。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該第二電子元件係藉由導電凸塊電性連接該第一電子元件。
  7. 如申請專利範圍第1項所述之電子封裝件，復包括包覆層，係形成於該第一承載結構之第一表面上以包覆該第一電子元件與第二電子元件。
  8. 如申請專利範圍第7項所述之電子封裝件，其中，該第二電子元件之部分表面外露於該包覆層。
  9. 如申請專利範圍第7項所述之電子封裝件，其中，該包覆層復包覆該封裝模組。
  10. 如申請專利範圍第1項所述之電子封裝件，復包括複數導電元件，係形成於該第一承載結構之第二表面上且電性連接該第一線路層。
  11. 一種電子封裝件之製法，係包括：提供一具有第一線路層並定義有相對之第一表面與第二表面之第一承載結構；以及將封裝模組、第一電子元件與第二電子元件配置於該第一承載結構之第一表面上，其中，該封裝模組與該第一電子元件係電性連接該第一線路層，且該第二電子元件係堆疊於該第一電子元件上並電性連接該第一電子元件。
  12. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該封裝模組係包含：第二承載結構，係具有第二線路層並藉由複數導電體設於該第一承載 結構之第一表面上，且該複數導電體電性連接該第一線路層與第二線路層；至少一功能電子元件，係配置於該第二承載結構上且電性連接該第二線路層；以及封裝層，係包覆該功能電子元件。
  13. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該第一線路層之線路規格不同於該第二線路層之線路規格。
  14. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該第一線路層之線寬/線距係大於該第二線路層之線寬/線距。
  15. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該第一電子元件係藉由銲線電性連接該第一線路層。
  16. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該第二電子元件係藉由導電凸塊電性連接該第一電子元件。
  17. 如申請專利範圍第11項所述之電子封裝件之製法，復包括形成包覆層於該第一承載結構之第一表面上，以令該包覆層包覆該第一電子元件與第二電子元件。
  18. 如申請專利範圍第17項所述之電子封裝件之製法，其中，該第二電子元件之部分表面外露於該包覆層。
  19. 如申請專利範圍第17項所述之電子封裝件之製法，其中，該包覆層復包覆該封裝模組。
  20. 如申請專利範圍第11項所述之電子封裝件之製法，復包括形成複數導電元件於該第一承載結構之第二表面上，且該複數導電元件電性連接該第一線路層。
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