CN112701101A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN112701101A
CN112701101A CN201911010459.9A CN201911010459A CN112701101A CN 112701101 A CN112701101 A CN 112701101A CN 201911010459 A CN201911010459 A CN 201911010459A CN 112701101 A CN112701101 A CN 112701101A
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China
Prior art keywords
electronic
circuit layer
electrically connected
layer
package
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CN201911010459.9A
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English (en)
Inventor
廖信一
张正楷
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN112701101A publication Critical patent/CN112701101A/zh
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Abstract

一种电子封装件及其制法，包括：一具有第一线路层的第一承载结构、配置于该第一承载结构上且电性连接该第一线路层的封装模块、配置于该第一承载结构上且电性连接该第一线路层的第一电子元件、以及堆叠于该第一电子元件上且电性连接该第一电子元件的第二电子元件，以经由该第一电子元件与第二电子元件相堆叠的设计，而减少所述电子元件占用该第一承载结构的表面面积，故能有足够的空间放置该封装模块。

Description

电子封装件及其制法
技术领域
本发明关于一种半导体封装制程，特别是关于一种电子封装件及其制法。
背景技术
随着电子产业的发达，现今的电子产品已趋向轻薄短小与功能多样化的方向设计，半导体封装技术也随之开发出不同的封装型态。为满足半导体装置的高集成度(Integration)、微型化(Miniaturization)以及高电路效能等需求，遂而发展出覆晶(Flipchip)接合封装技术。
覆晶接合封装技术为一种以芯片(或其它半导体结构)的作用面上形成多个金属凸块，以经由所述金属凸块使该芯片的作用面得电性连接至外部电子装置或封装基板，此种设计可大幅缩减整体封装件的体积。
如图1A及图1B所示，于悉知覆晶式半导体封装件1的制程中，先将一半导体芯片11经由多个焊锡凸块13结合至一封装基板10上，再形成底胶12于该半导体芯片11与该封装基板10之间，以包覆所述焊锡凸块13。之后，于该封装基板10下侧植设多个焊球14以接置于电子产品的运算主板(major board)8上。
但是，悉知半导体封装件1中，该封装基板10的表面若需同时水平排设许多半导体芯片11，将占据该封装基板10过多的表面面积，故无法有足够的空间放置其它封装模块。另一方面，若将该封装基板10的表面面积扩增，将迫使该半导体封装件1的体积增大，导致该半导体封装件1不符合轻薄短小的发展潮流。
此外，该封装基板10为一般有机基板或核心基板，其受限于制程，而只能制作单一线宽/线距规格的线路，故难以同时满足不同电子元件所需的不同线路规格。例如，微小化功能芯片需配置于较细小的线宽/线距规格的线路上，电源插口与接地插口需形成于较宽大的线宽/线距规格的线路上。
因此，如何克服上述悉知技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述悉知技术的缺陷，本发明提供一种电子封装件及其制法，利于缩减应用该电子封装件的电子产品的体积。
本发明的电子封装件包括：第一承载结构，其定义有相对的第一表面与第二表面并具有第一线路层；封装模块，其配置于该第一承载结构的第一表面上且电性连接该第一线路层；第一电子元件，其配置于该第一承载结构的第一表面上且电性连接该第一线路层；以及第二电子元件，其堆叠于该第一电子元件上且电性连接该第一电子元件。
本发明还提供一种电子封装件的制法，其包括：提供一第一承载结构，其具有第一线路层并定义有相对的第一表面与第二表面；以及将封装模块、第一电子元件与第二电子元件配置于该第一承载结构的第一表面上，其中，该封装模块与该第一电子元件电性连接该第一线路层，且该第二电子元件堆叠于该第一电子元件上并电性连接该第一电子元件。
前述的电子封装件及其制法中，该封装模块包含：具有第二线路层的第二承载结构，其经由多个导电体设于该第一承载结构的第一表面上，且该多个导电体电性连接该第一线路层与第二线路层；至少一功能电子元件，其配置于该第二承载结构上且电性连接该第二线路层；以及封装层，其包覆该功能电子元件。例如，该第一线路层的线路规格不同于该第二线路层的线路规格。或者，该第一线路层的线宽/线距大于该第二线路层的线宽/线距。
前述的电子封装件及其制法中，该第一电子元件经由焊线电性连接该第一线路层。
前述的电子封装件及其制法中，该第二电子元件经由导电凸块电性连接该第一电子元件。
前述的电子封装件及其制法中，还包括形成包覆层于该第一承载结构的第一表面上，以令该包覆层包覆该第一电子元件与第二电子元件。例如，该第二电子元件的部分表面外露于该包覆层。或者，该包覆层还包覆该封装模块。
前述的电子封装件及其制法中，还包括形成多个导电元件于该第一承载结构的第二表面上，且该多个导电元件电性连接该第一线路层。
由上可知，本发明的电子封装件及其制法中，主要经由将该第一电子元件与该第二电子元件相堆叠，以减少所述电子元件占用该第一承载结构的第一表面的面积，故相比于悉知技术，本发明的电子封装件不仅能有足够的空间放置封装模块，且有利于缩减应用该电子封装件的电子产品的体积，使该电子产品符合轻薄短小的发展趋势。
此外，经由形成两种线路规格的第一线路层与该第二线路层，使微小化芯片规格的功能电子元件能经由该第二线路层电性连接至第一线路层。
另外，本发明的制法通过将该第一线路层制作成电源接点与接地接点所需的线宽/线距，因而该第一电子元件可电性连接该第一线路层，而无需将所有线路制作成如第二线路层的线宽/线距，故相比于悉知技术的单一线路规格，本发明的制法较节省成本。
另外，该第一电子元件与第二电子元件以“作用面相接”的方式相互电性连接，以缩短电性传输路径，故本发明的电子封装件能增快信号传输速度。
附图说明
图1A至图1B为悉知覆晶式半导体封装件的制法的剖视示意图。
图2A至图2E为本发明的电子封装件的制法的剖面示意图。
图2C’为图2C的另一制程的剖面示意图。
图2E’及图2E”为图2E的其它实施例的剖面示意图。
附图标记说明
1 半导体封装件 10 封装基板
11 半导体芯片 12 底胶
13 焊锡凸块 14 焊球
2,2’,2” 电子封装件 2a 封装模块
20 第一承载结构 20a 第一表面
20b 第二表面 200 绝缘层
201 第一线路层 21 第二承载结构
210 绝缘体 211 第二线路层
22 功能电子元件 220 导电凸块
23 封装层 24 导电体
240 结合材 25 第一电子元件
25a,26a 作用面 25b,26b 非作用面
250,250’,260 电极垫 251 粘着材
26 第二电子元件 27a 焊线
27b 导电凸块 28 包覆层
28a 表面 29 导电元件
8 运算主板 9 支撑件。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“第一”、“第二”、及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2E为本发明的电子封装件2的制法的剖视示意图。
如图2A所示，提供一第一承载结构20，例如，该第一承载结构20设于一支撑件9上。
于本实施例中，该第一承载结构20为整版面基板形式，即该整版面基板包含多个基板单元，该第一承载结构20例如为具有核心层与线路结构的封装基板或无核心层(coreless)的线路结构，其具有相对的第一表面20a与第二表面20b，且该线路结构包含至少一绝缘层200及至少一结合该绝缘层200的第一线路层201，如至少一扇出(fan out)型重布线路层(redistribution layer，简称RDL)。应可理解地，该第一承载结构20也可为其它承载芯片的板材，如导线架(lead frame)、晶圆(wafer)、或其它具有金属布线(routing)的载板等，并不限于上述。
于本实施例中，该第一承载结构20的制程方式繁多，例如，可采用晶圆制程制作线路层，而以化学气相沉积(Chemical vapor deposition，简称CVD)形成氮化硅或氧化硅以作为绝缘层；或者，可采用一般非晶圆制程方式形成线路层，即采用成本较低的高分子介电材作为绝缘层，如聚酰亚胺(Polyimide，简称PI)、聚对二唑苯(Polybenzoxazole，简称PBO)、预浸材(Prepreg，简称PP)、封装胶体(molding compound)、感光型介电层或其它材料等以涂布方式形成。
另外，该第一线路层201的线路规格为线宽及线距(L/S)大于2微米(um)以上。
另外，该支撑件9为玻璃板、晶圆板或其它适当板体。
如图2B所示，将一封装模块2a设于该第一承载结构20的第一表面20a上，且令该封装模块2a电性连接该第一线路层201。
于本实施例中，该封装模块2a包含一第二承载结构21、至少一设于该第二承载结构21的功能电子元件22、及一包覆该功能电子元件22的封装层23，且该第二承载结构21经由多个导电体24设于该第一承载结构20的第一表面20a上并经由所述导电体24电性连接该第一线路层201。
所述的第二承载结构21例如为具有核心层与线路结构的封装基板或无核心层(coreless)的线路结构，其包含有绝缘体210及结合该绝缘体210的第二线路层211(如至少一扇出(fan out)型重布线路层(RDL))。应可理解地，该第二承载结构21也可为其它承载芯片的板材，如导线架(lead frame)、晶圆(wafer)、或其它具有金属布线(routing)的载板等，并不限于上述。具体地，该第二承载结构21的制程方式繁多，例如，可采用晶圆制程制作线路层，而以化学气相沉积(CVD)形成氮化硅或氧化硅以作为绝缘层；或者，可采用一般非晶圆制程方式形成线路层，即采用成本较低的高分子介电材作为绝缘体，如聚酰亚胺(PI)、聚对二唑苯(PBO)、预浸材(PP)、封装胶体、感光型介电层或其它等以涂布方式形成。
此外，该第一线路层201的线路规格不同于该第二线路层211的线路规格。例如，该第二线路层211以重布线路(Redistribution Layers，简称RDL)制程制作，其线宽/线距为小于或等于2um，故该第一线路层201的线宽/线距大于该第二线路层211的线宽/线距。
所述的功能电子元件22为主动元件、被动元件或其组合者，其中，该主动元件例如为半导体芯片，而该被动元件例如为电阻、电容及电感。例如，该功能电子元件22为半导体芯片，其可经由多个如焊锡材料、金属柱(pillar)或其它等的导电凸块220以覆晶方式设于该第二承载结构21上侧并电性连接该第二线路层211；或者，该功能电子元件22可经由多个焊线以打线方式电性连接该第二线路层211；亦或，该功能电子元件22可直接接触该第二线路层211。
所述的封装层23还包覆所述导电凸块220，且该封装层23为绝缘材，如聚酰亚胺(PI)、干膜(dry film)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)，其可用压合(lamination)、涂布(coating)或模压(molding)的方式形成于该第二承载结构21上。例如，该封装层23可露出(如图2B所示)或覆盖(图未示)该功能电子元件22。
所述的导电体24为如铜柱状的金属凸块、焊锡材、金属针或其它导电构造，其形成于该第二承载结构21下侧，并于该第一承载结构20与第二承载结构21之间形成如底胶的结合材240以包覆所述导电体24并固定该封装模块2a。
如图2C所示，设置第一电子元件25与第二电子元件26于该第一承载结构20的第一表面20a上。
于本实施例中，该第二电子元件26堆叠于该第一电子元件25上。
所述的第一电子元件25为主动元件、被动元件或其组合者，其中，该主动元件例如为半导体芯片，而该被动元件例如为电阻、电容及电感。例如，该第一电子元件25为半导体芯片，其具有相对的作用面25a与非作用面25b，其以非作用面25b经由粘着材251设于该第一承载结构20的第一表面20a上，并于该作用面25a的部分电极垫250上经由多个焊线27a以打线方式电性连接该第一线路层201。
所述的第二电子元件26为主动元件、被动元件或其组合者，其中，该主动元件例如为半导体芯片，而该被动元件例如为电阻、电容及电感。例如，该第二电子元件26为半导体芯片，其具有相对的作用面26a与非作用面26b，其以作用面26a设于该第一电子元件25的作用面25a上，并使其电极垫260经由多个导电凸块27b以覆晶方式电性连接该第一电子元件25的其它电极垫250’。于其他实施例中，第二电子元件26的电极垫260与第一电子元件25的电极垫250’可直接接合而无需导电凸块。
因此，该第一电子元件25与第二电子元件26以“作用面25a,26a相接”的方式相互叠置。
此外，该第一电子元件25与第二电子元件26的设置方式繁多。具体地，如图2C’所示，可先将该第一电子元件25与第二电子元件26相互接合，再设于该第一承载结构20上，之后再进行打线作业。或者，可先将该第一电子元件25与第二电子元件26依序配置，且于配置该第二电子元件26之前或之后，进行打线作业。
另外，于其它实施例中，该第一电子元件25也可以覆晶方式电性连接该第一线路层201，而该第二电子元件26也可以打线方式电性连接该第一电子元件25。
应可理解地，可于该第一承载结构20的第一表面20a与第二表面20b接置任意形式、种类或数量的电子元件，以提升其电性功能，且有关电子元件的电性连接方式繁多，并不限于上述。
同理地，有关该封装模块2a、第一电子元件25与第二电子元件26的配置顺序也可依需求设计，其制程的先后顺序并不限于上述。
如图2D所示，形成一包覆层28于该第一承载结构20的第一表面20a上，以令该包覆层28包覆该第一电子元件25、第二电子元件26、焊线27a与导电凸块27b。
于本实施例中，该包覆层28接触该第一承载结构20的第一表面20a，且形成该包覆层28的材料为绝缘材，如聚酰亚胺(PI)、环氧树脂(epoxy)的封装胶体或封装材，其可用模压(molding)方式形成。
此外，形成该包覆层28的材料为相同或不同形成该封装层23的材料。
另外，该第二电子元件26未外露于该包覆层28的表面28a，但可依需求移除该包覆层28的部分材料，以露出该第二电子元件26的非作用面26b。例如，经由如研磨方式的整平制程移除该包覆层28的部分材料，使该第二电子元件26的非作用面26b齐平该包覆层28的表面28a，如图2E’所示的电子封装件2’。或者，以如激光的钻孔方式于该包覆层28的表面28a上形成多个外露该第二电子元件26的开孔。亦或，可于移除该包覆层28的部分材料后，使该第二电子元件26的非作用面26b凸出该包覆层28的表面28a。应可理解地，有关该电子元件外露出该包覆层28的方式繁多，并不限于上述。
另外，由于该封装模块2a已配置有该封装层23，故该包覆层28未包覆该封装模块2a。然而，于另一实施例中，如图2E”所示，也可依需求令该包覆层28包覆该封装模块2a。
如图2E所示，移除该支撑件9，以外露出该第一承载结构20的第二表面20b，且可依需求进行切单制程，以得到电子封装件2，并形成多个导电元件29于该第一承载结构20的第二表面20b上，以供该电子封装件2接置于一如电路板的电子装置(图略)。
于本实施例中，该导电元件29电性连接该第一承载结构20的第一线路层201，其可为如铜柱的金属柱、包覆有绝缘块的金属凸块、焊球(solder ball)、具有核心铜球(Cucore ball)的焊球或其它适当导电构造等，且其形状并未有特殊限制，如圆柱体、椭圆柱体或多边形柱体皆可。
本发明的电子封装件2,2’,2”的制法中，主要经由将该第一电子元件25与该第二电子元件26相堆叠，以减少所述电子元件占用该第一承载结构20的第一表面20a的面积，故相比于悉知技术，本发明的电子封装件2,2’,2”不仅能有足够的空间放置封装模块2a或其它分立元件(discrete component)(图未示)，且有利于缩减应用该电子封装件2,2’的电子产品的体积，使该电子产品符合轻薄短小的发展趋势。
此外，经由两次扇出型的线路重布层制程(即该第一线路层201与该第二线路层211)，使微小化芯片(即符合微小化的规格需求的功能电子元件22)能经由该第二线路层211电性连接至第一线路层201。
另外，本发明的制法将该第一线路层201制作成电源接点与接地接点所需的线宽/线距，因而该第一电子元件25可电性连接该第一线路层201(线宽/线距为2～10um)，而无需将所有线路制作成如第二线路层211的线宽/线距(其为2um以内)，故相较悉知技术的所有线路层的线宽/线距皆为2um以内，本发明的制法较节省成本。
另外，该第一电子元件25与第二电子元件26以“作用面25a,26a相接”的方式相互电性连接，以缩短电性传输路径，故相比于悉知技术，本发明的电子封装件2,2’,2”能增快信号传输速度。
本发明还提供一种电子封装件2,2’,2”，其包括：一具有第一线路层201的第一承载结构20、一封装模块2a、一第一电子元件25以及一第二电子元件26。
所述的第一承载结构20定义有相对的第一表面20a与第二表面20b。
所述的封装模块2a配置于该第一承载结构20的第一表面20a上且电性连接该第一线路层201，其中，该封装模块2a包含：一具有第二线路层211的第二承载结构21，其经由多个导电体24设于该第一承载结构20的第一表面20a上，且该多个导电体24电性连接该第一线路层201与第二线路层211；至少一功能电子元件22，其配置于该第二承载结构21上且电性连接该第二线路层211；以及一封装层23，其包覆该功能电子元件22。
所述的第一电子元件25配置于该第一承载结构20的第一表面20a上且电性连接该第一线路层201。
所述的第二电子元件26堆叠于该第一电子元件25上且电性连接该第一电子元件25。
于一实施例中，该第一线路层201的线路规格不同于该第二线路层211的线路规格。
于一实施例中，该第一线路层201的线宽/线距大于该第二线路层211的线宽/线距。
于一实施例中，该第一电子元件25经由多个焊线27a电性连接该第一线路层201。
于一实施例中，该第二电子元件26经由多个导电凸块27b电性连接该第一电子元件25。
于一实施例中，所述的电子封装件2,2’,2”还包括一包覆层28，其形成于该第一承载结构20的第一表面20a上以包覆该第一电子元件25与第二电子元件26。例如，该电子封装件2’的第二电子元件26的非作用面26b外露于该包覆层28。或者，于该电子封装件2”中，该包覆层28还包覆该封装模块2a。
于一实施例中，所述的电子封装件2,2’,2”还包括多个导电元件29，其形成于该第一承载结构20的第二表面20b上且电性连接该第一线路层201。
综上所述，本发明的电子封装件及其制法，主要经由将该第一电子元件与该第二电子元件相堆叠，以减少所述电子元件占用该第一承载结构的第一表面的面积，故本发明的电子封装件不仅能有足够的空间放置封装模块，且有利于缩减应用该电子封装件的电子产品的体积，使该电子产品符合轻薄短小的发展趋势。
此外，经由形成两种线路规格的第一线路层与该第二线路层，使微小化芯片规格的功能电子元件能经由该第二线路层电性连接至第一线路层。
另外，本发明的制法通过将该第一线路层制作成电源接点与接地接点所需的线宽/线距，因而该第一电子元件可电性连接该第一线路层，而无需将所有线路制作成如第二线路层的线宽/线距，故本发明的制法较节省成本。
另外，该第一电子元件与第二电子元件以“作用面相接”的方式相互电性连接，以缩短电性传输路径，故本发明的电子封装件能增快信号传输速度。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种电子封装件，其特征在于，包括：
第一承载结构，其定义有相对的第一表面与第二表面并具有第一线路层；
封装模块，其配置于该第一承载结构的第一表面上且电性连接该第一线路层；
第一电子元件，其配置于该第一承载结构的第一表面上且电性连接该第一线路层；以及
第二电子元件，其堆叠于该第一电子元件上且电性连接该第一电子元件。
2.根据权利要求1所述的电子封装件，其特征在于，该封装模块包含：
第二承载结构，其具有第二线路层并经由多个导电体设于该第一承载结构的第一表面上，且该多个导电体电性连接该第一线路层与第二线路层；
至少一功能电子元件，其配置于该第二承载结构上且电性连接该第二线路层；以及
封装层，其包覆该功能电子元件。
3.根据权利要求2所述的电子封装件，其特征在于，该第一线路层的线路规格不同于该第二线路层的线路规格。
4.根据权利要求2所述的电子封装件，其特征在于，该第一线路层的线宽/线距大于该第二线路层的线宽/线距。
5.根据权利要求1所述的电子封装件，其特征在于，该第一电子元件经由焊线电性连接该第一线路层。
6.根据权利要求1所述的电子封装件，其特征在于，该第二电子元件经由导电凸块电性连接该第一电子元件。
7.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括包覆层，其形成于该第一承载结构的第一表面上以包覆该第一电子元件与第二电子元件。
8.根据权利要求7所述的电子封装件，其特征在于，该第二电子元件的部分表面外露于该包覆层。
9.根据权利要求7所述的电子封装件，其特征在于，该包覆层还包覆该封装模块。
10.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括多个导电元件，其形成于该第一承载结构的第二表面上且电性连接该第一线路层。
11.一种电子封装件的制法，其特征在于，包括：
提供一具有第一线路层并定义有相对的第一表面与第二表面的第一承载结构；以及
将封装模块、第一电子元件与第二电子元件配置于该第一承载结构的第一表面上，其中，该封装模块与该第一电子元件电性连接该第一线路层，且该第二电子元件堆叠于该第一电子元件上并电性连接该第一电子元件。
12.根据权利要求11所述的电子封装件的制法，其特征在于，该封装模块包含：
第二承载结构，其具有第二线路层并经由多个导电体设于该第一承载结构的第一表面上，且该多个导电体电性连接该第一线路层与第二线路层；
至少一功能电子元件，其配置于该第二承载结构上且电性连接该第二线路层；以及
封装层，其包覆该功能电子元件。
13.根据权利要求12所述的电子封装件的制法，其特征在于，该第一线路层的线路规格不同于该第二线路层的线路规格。
14.根据权利要求12所述的电子封装件的制法，其特征在于，该第一线路层的线宽/线距大于该第二线路层的线宽/线距。
15.根据权利要求11所述的电子封装件的制法，其特征在于，该第一电子元件经由焊线电性连接该第一线路层。
16.根据权利要求11所述的电子封装件的制法，其特征在于，该第二电子元件经由导电凸块电性连接该第一电子元件。
17.根据权利要求11所述的电子封装件的制法，其特征在于，该制法还包括形成包覆层于该第一承载结构的第一表面上，以令该包覆层包覆该第一电子元件与第二电子元件。
18.根据权利要求17所述的电子封装件的制法，其特征在于，该第二电子元件的部分表面外露于该包覆层。
19.根据权利要求17所述的电子封装件的制法，其特征在于，该包覆层还包覆该封装模块。
20.根据权利要求11所述的电子封装件的制法，其特征在于，该制法还包括形成多个导电元件于该第一承载结构的第二表面上，且该多个导电元件电性连接该第一线路层。
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