CN110797293A - 封装堆叠结构及其制法暨封装结构 - Google Patents

封装堆叠结构及其制法暨封装结构 Download PDF

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Publication number
CN110797293A
CN110797293A CN201811140146.0A CN201811140146A CN110797293A CN 110797293 A CN110797293 A CN 110797293A CN 201811140146 A CN201811140146 A CN 201811140146A CN 110797293 A CN110797293 A CN 110797293A
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Prior art keywords
carrier
circuit
circuit structure
package
layer
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CN201811140146.0A
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Inventor
林长甫
陈汉宏
萧人杰
林荣政
余国华
张宏达
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Priority claimed from TW107132430A external-priority patent/TWI710032B/zh
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN110797293A publication Critical patent/CN110797293A/zh
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Abstract

一种封装堆叠结构及其制法暨封装结构，先提供一设有承载件的线路结构及一设有电子元件的承载结构，再将该线路结构以多个导电元件结合至该承载结构上，且形成封装层于该线路结构与该承载结构之间，以令该封装层包覆该些导电元件与该电子元件，之后移除该承载件，俾经由该承载件的配置，以强化该线路结构的结构强度，因而于堆叠该线路结构至该承载结构前，能避免该线路结构发生翘曲的问题。

Description

封装堆叠结构及其制法暨封装结构
技术领域
本发明有关一种半导体封装制程，尤指一种封装堆叠结构及其制法暨封装结构。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductor device)已开发出不同的封装型态，而为提升电性功能及节省封装空间，业界遂发展出堆叠多个封装结构以形成封装堆叠结构(Package on
Package，简称POP)的封装型态，此种封装型态能发挥系统封装(SiP)异质整合特性，可将不同功用的电子元件，例如：记忆体、中央处理器、绘图处理器、影像应用处理器等，经由堆叠设计达到系统的整合，而适用于各种轻薄短小型电子产品。
图1为悉知封装堆叠结构1的剖面示意图。如图1所示，该封装堆叠结构1包含有第一半导体元件10、第一封装基板11、第二封装基板12、多个焊球13、第二半导体元件14以及封装胶体15。该第一封装基板11具有核心层110与多个线路层111，且该第二封装基板12具有核心层120与多个线路层121。该第一半导体元件10以覆晶方式设于该第一封装基板11上，且该第二半导体元件14也以覆晶方式设于该第二封装基板12上。该些焊球13用以连结且电性耦接该第一封装基板11与该第二封装基板12。该封装胶体15包覆该些焊球13与该第一半导体元件10。可选择性地，形成底胶16于该第一半导体元件10与该第一封装基板11之间。
惟，前述悉知封装堆叠结构1中，第一封装基板11与第二封装基板12皆具有核心层110,120，导致其制作成本高，且该封装堆叠结构1的厚度H约为620微米，不符现今产品轻薄短小化的需求。
因此，如何克服上述悉知技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述悉知技术的缺失，本发明提供一种封装堆叠结构及其制法暨封装结构，能避免该线路结构发生翘曲的问题。
本发明的封装堆叠结构，包括：承载结构，其定义有相对的第一侧与第二侧，其中，该承载结构的第一侧设有至少一电子元件；以及线路结构，其具有相对的第一表面与第二表面，且该第一表面设有承载件，而该第二表面以多个导电元件结合至该承载结构的第一侧上。
前述的封装堆叠结构中，复包括封装层，其形成于该线路结构与该承载结构之间，以包覆该些导电元件与该电子元件。
本发明还提供一种封装堆叠结构的制法，包括：提供一设有承载件的线路结构及一承载结构，其中，该承载结构定义有相对的第一侧与第二侧，且该承载结构的第一侧设有至少一电子元件；将该线路结构以多个导电元件结合至该承载结构的第一侧上，且形成封装层于该线路结构与该承载结构之间，以令该封装层包覆该些导电元件与该电子元件；以及移除该承载件。
前述的制法中，该些导电元件先设于该线路结构上，再将该线路结构以该些导电元件结合至该承载结构上。
前述的制法中，该些导电元件先设于该承载结构上，再将该线路结构以该些导电元件结合至该承载结构上。
前述的制法中，该线路结构于结合该承载结构前为已切单型态，该承载结构于结合该线路结构前为整版面型态。
前述的制法中，该线路结构于结合该承载结构前为整版面型态，该承载结构于结合该线路结构前为整版面型态。
前述的制法中，该线路结构于结合该承载结构前为整版面型态，该承载结构于结合该线路结构前为已切单型态。
前述的制法中，于移除该承载件后，进行切单。
前述的制法中，该线路结构于结合该承载结构前为已切单型态，该承载结构于结合该线路结构前为已切单型态。
前述的封装堆叠结构及其制法中，该承载件为硅晶圆，其接触结合该线路结构的介电材。例如，以研磨方式移除该承载件。
前述的封装堆叠结构及其制法中，该线路结构为线路重布层结构。
前述的封装堆叠结构及其制法中，该线路结构具有相对的第一表面与第二表面，且该第一表面结合于该承载件上，而该第二表面配置有多个堆叠接点，以结合该些导电元件。
前述的封装堆叠结构及其制法中，该承载件为玻璃，其以结合层接触结合该线路结构的介电材。例如，以剥离方式移除该承载件及该结合层。
前述的封装堆叠结构及其制法中，该线路结构具有相对的第一表面与第二表面，且该第二表面结合于该承载件上，而该第一表面配置有多个堆叠接点，以结合该些导电元件。
前述的封装堆叠结构及其制法中，该导电元件为焊球、金属柱或包覆有绝缘块的金属凸块。
本发明还提供一种封装结构，包括：线路结构，其具有相对的两侧；承载件，其设于该线路结构的其中一侧；以及导电元件，其设于该线路结构的另一侧以电性连接该线路结构。
前述的封装结构中，该承载件为硅晶圆，其接触结合该线路结构的介电材。
前述的封装结构中，该承载件为玻璃，其以结合层接触结合该线路结构的介电材。
前述的封装结构中，该线路结构为线路重布层结构。
前述的封装结构中，该导电元件为焊球、金属柱或包覆有绝缘块的金属凸块。
由上可知，本发明的封装堆叠结构及其制法暨封装结构，主要经由该承载件的配置，以强化该线路结构的结构强度，故相较于悉知技术，若将本发明的线路结构设计为无核心层式，不仅能大幅降低该封装堆叠结构的整体厚度，且于堆叠该线路结构至该承载结构前，能避免该线路结构发生翘曲的问题。
附图说明
图1为悉知封装堆叠结构的剖面示意图。
图2A至图2F为本发明的封装堆叠结构的制法的第一实施例的剖视示意图。
图2A’及图2A”为图2A的不同实施例的局部放大示意图。
图2B’为图2B的另一实施例的局部放大示意图。
图2C’至2E’为图2C至图2E的另一实施例。
图3A至图3E为本发明的封装堆叠结构的制法的第二实施例的剖视示意图。
图3B’及图3B”为图3B的不同实施例。
图3C’至图3D’为图3B’的后续制程。
图4A至图4D为本发明的封装堆叠结构的制法的第三实施例的剖视示意图。
图5A至图5C为本发明的封装堆叠结构的制法的第四实施例的剖视示意图。
符号说明
1,2,2’,4,4’,4” 封装堆叠结构 10 第一半导体元件
11 第一封装基板 110,120 核心层
111,121 线路层 12 第二封装基板
13 焊球 14 第二半导体元件
15 封装胶体 16 底胶
2” 封装结构 2a,2a’ 线路结构
20 第一承载件 20’ 第二承载件
20a 离形层 20b 结合层
200 介电层 200’ 沟槽
21 线路部 21a 第一表面
21b 第二表面 210 介电体
211 线路层 212,212’ 堆叠接点
212a 导电层 212b 金属块
22 金属层 29,29’,29” 金属结构
29a 第一金属层 29b 第二金属层
29c 第三金属层 290 堆叠接点
3,3’ 封装组件 3a,3a’ 承载结构
30a 第一侧 30b 第二侧
32 绝缘层 33 布线层
330 电性连接垫 34 绝缘保护层
35 导电凸块 40,44 电子元件
40a 作用面 40b 非作用面
400 电极垫 41 封装层
42 外接元件 43 焊锡材料
45 导电元件 H,L,T 厚度
S,D 切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“第一”、“第二”、“上”、及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2F，其为本发明的封装堆叠结构2,2’的制法的第一实施例的剖视示意图。
如图2A所示，形成一介电层200于一第一承载件20上，再形成多个金属结构29于该介电层200上。
于本实施例中，该第一承载件20为半导体板体，例如暂时性整版面硅晶圆(Siwafer)。
如图2A’所示，该金属结构29可包含多层金属层，例如，先于第一承载件20上形成具有多个开孔的介电层200，再将第一金属层29a形成于该介电层200上与开孔中，接着形成第二金属层29b于部分该第一金属层29a上，之后移除该第一金属层29a未覆盖有该第二金属层29b的部分，使相叠的第一与第二金属层29a,29b作为该金属结构29’。或者，如图2A”所示，于移除该第一金属层29a未覆盖有该第二金属层29b的部分后，再于该第二金属层29b上形成第三金属层29c，使相叠的第一至第三金属层29a,29b,29c作为该金属结构29”。
如图2B所示，形成一线路部21于该介电层200与该金属结构29上，以令该线路部21、介电层200与该金属结构29构成一整版面的线路结构2a。
于本实施例中，该线路部21具有相对的第一表面21a与第二表面21b，并以该第一表面21a结合该介电层200与该金属结构29，且该线路部21具有介电体210及结合该介电体210并电性连接该金属结构29的线路层211，且最外侧的线路层211上可形成有凸块底下金属层(Under Bump Metallurgy，简称UBM)，以作为堆叠接点212；或者，最外侧的线路层211形成BOT(Bump on trace)型金属凸块，以作为堆叠接点212’，如图2B’所示的导电层212a与金属块212b所构成。
此外，该线路部21可由线路重布层(Redistribution layer，简称RDL)制程完成。例如，由于晶圆制程中为形成线路层所用的介电层需以化学气相沉积(Chemical vapordeposition，简称CVD)形成氮化硅或氧化硅，其成本较高，故可采用一般非晶圆制程方式形成线路，即采用成本较低的高分子介电层，如聚酰亚胺(Polyimide，简称PI)、聚对二唑苯(Polybenzoxazole，简称PBO)以涂布方式形成于线路层之间进行绝缘。
如图2C所示，于该整版面的线路结构2a的堆叠接点212上结合导电元件45以形成封装结构2”，且提供一封装组件3，其包含一整版面的承载结构3a及结合该承载结构3a的电子元件40，且该承载结构3a定义有相对的第一侧30a与第二侧30b。
于本实施例中，该承载结构3a为具有核心层或无核心层(coreless)的线路结构，如封装基板(substrate)，其具有如扇出(fan out)型重布线路层(redistribution layer，简称RDL)的线路配置。具体地，该承载结构3a包含多个绝缘层32、及设于该绝缘层32上的布线层33，且形成该绝缘层32的材质如预浸材(prepreg)、封装胶体(moldingcompound)或感光型介电层，但不限于此，并可于该承载结构3a的第一侧30a上形成一如防焊层的绝缘保护层34，使该布线层33的部分表面外露于该绝缘保护层34，以作为电性连接垫330。应可理解地，该承载结构3a也可为其它承载芯片的板材，如导线架(leadframe)、晶圆(wafer)、或其它具有金属布线(routing)的载板等，并不限于上述。
此外，该电子元件40为主动元件、被动元件或其二者组合，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该电子元件40为半导体芯片，其具有相对的作用面40a与非作用面40b，该作用面40a具有多个电极垫400，且该电极垫400以覆晶方式经由多个导电凸块35设于该承载结构3a的第一侧30a上并电性连接部分该布线层33。
或者，该电子元件40可经由多个焊线(图略)以打线方式电性连接该承载结构3a；亦或，该电子元件40可直接接触该承载结构3a的线路，如该电子元件40嵌埋于该承载结构3a中。
应可理解地，有关该电子元件40电性连接该承载结构3a的方式繁多，并不限于上述。
如图2D所示，将该整版面的线路结构2a以其堆叠接点212经由该些导电元件45结合于该整版面的承载结构3a的电性连接垫330上。接着，形成一封装层41于该整版面的线路结构2a与该整版面的承载结构3a之间，以令该封装层41包覆该电子元件40、该些导电元件45与该些导电凸块35。
于本实施例中，该导电元件45为包覆有绝缘块的金属凸块、如铜柱的金属柱、焊球(solder ball)或具有核心铜球(Cu core ball)的焊球等，其形状并未有特殊限制，可为圆柱体、椭圆柱体或多边形柱体皆可。
此外，于其它实施例中，该导电元件45也可先形成于该承载结构3a上，再结合该线路结构2a；或者，可于该承载结构3a上也形成另一导电元件，再将该封装结构2”的导电元件45结合该承载结构3a的导电元件。
又，该封装层41为绝缘材，如环氧树脂的封装胶体，并无特别限制。
另外，于结合该线路结构2a与该承载结构3a之前，可先形成底胶(图略)于该电子元件40与该承载结构3a之间，以包覆该些导电凸块35。
如图2E所示，透过如研磨的制程移除该第一承载件20，以露出该金属结构29及介电层200，并形成多个外接元件42于该承载结构3a的第二侧30b上以电性连接该布线层33。
于本实施例中，该外接元件42为例如焊球或其它金属体，以于后续制程中用以接置一如电路板的电子装置(图略)。
如图2F所示，沿图2E所示的切割路径S进行切单制程，以获取封装堆叠结构2’，且经由其金属结构29结合如焊锡材料43的导电材料，以接合另一如记忆体芯片的电子元件44(见图2F)。
于另一实施例中，如图2C’所示，可先将整版面的线路结构2a进行预切作业，以获取多个已切单的线路结构2a’，再将各该已切单的线路结构2a’透过导电元件45堆叠于该整版面的承载结构3a上。接着，如图2D’所示，形成一封装层41于该已切单的线路结构2a’与该整版面的承载结构3a之间，以令该封装层41包覆该电子元件40、该些导电元件45、该些导电凸块35与该已切单的线路结构2a’。之后，如图2E’所示，先透过如研磨的制程移除该第一承载件20，再沿图2D’所示的切割路径S进行切单制程，以获取如图2F所示的封装堆叠结构2’。
请参阅图3A至图3E，其为接续图2B的制程的封装堆叠结构4,4’的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于线路结构的制程，其它制程大致相同，故以下仅说明相异处，而不再赘述相同处。
如图3A所示，提供一如玻璃的第一承载件20，且于其上形成有离形层20a，以制作介电层200、金属结构29与堆叠接点212，并于形成线路结构2a后，设置一第二承载件20’于该线路结构2a的第二表面21b上。
于本实施例中，该第二承载件20’也为整版面玻璃，其经由结合层20b(如粘胶)结合于该线路结构2a的第二表面21b上，且该结合层20b包覆该堆叠接点212。
如图3B所示，移除该第一承载件20及其离形层20a，以外露该金属结构29与介电层200。
于本实施例中，该金属结构29外露于该介电层200的表面作为堆叠接点290。
此外，于另一实施例中，如图3B’所示，可利用电镀方式形成一金属层22于该金属结构29上，使该金属层22电性连接线路结构2a’的线路层211，其中，该金属层22为例如电性接触垫或另一凸块底下金属层以作为堆叠接点。
又，可依需求进行预切作业。如图3B’所示，当该第二承载件20’为单元条(stripunit)型(如矩形条状，其结合多个已切单的线路结构2a’)时，可直接进行切单制程，以获取多个预制组件(其包含已切单的线路结构2a’及结合该线路结构2a’的已切单的第二承载件20’)。或者，如图3B”所示，当该第二承载件20’为晶圆型(如整版面圆形状，其结合多个该线路结构2a)时，可于该第二承载件20’上切割出沟槽200’(未延伸至该线路结构2a)。
如图3C所示，接续图3B所示的制程，将该线路结构2a以其金属层22(或堆叠接点290)结合多个导电元件45以作为封装结构，再将该封装结构以该导电元件45结合于如图2C的承载结构3a的电性连接垫330上。接着，形成一封装层41于该线路结构2a与该承载结构3a之间，以令该封装层41包覆该电子元件40、该些导电元件45与该些导电凸块35。
如图3D所示，移除该第二承载件20’及其结合层20b以外露出该堆叠接点212，且形成多个外接元件42于该承载结构3a的第二侧30b上以电性连接该布线层33。
于本实施例中，该外接元件42为例如焊球或其它金属体，以于后续制程中用以接置一如电路板的电子装置(图略)。
如图3E所示，沿图3D所示的切割路径S进行切单制程，以获取封装堆叠结构4’，且可经由其堆叠接点212结合如焊锡材料43的导电材料，以接合另一如记忆体芯片的电子元件44。
于本实施例中，当该第二承载件20’为单元条型(如图3B或图3B’所示)时，可以加热方式或照光方式(如UV光)，使该结合层20b失去部分粘性，以移除该第二承载件20’及其结合层20b。
于其它实施例中，如图3C’所示，其接续图3B’所示的制程，将已切单的线路结构2a’结合于该整版面的承载结构3a上，且于后续沿如图3C’所示的切割路径D进行半切制程后，再移除该第二承载件20’及其结合层20b，之后沿如图3C’所示的切割路径S进行切单制程，以形成如图3D’所示的结构。
于另一实施例中，当该第二承载件20’为晶圆型玻璃(如图3B”所示)时，该封装层41会填入该第二承载件20’的沟槽200’中，故可将该沟槽200’中的封装层41作为切割路径D,S，以进行半切制程、移除该第二承载件20’及其结合层20b及切单制程等制程。
请参阅图4A至图4D，其为接续图2B的制程的封装堆叠结构的制法的第三实施例的剖面示意图。本实施例与第一实施例的主要差异在于封装组件3’的制程，其它制程大致相同，故以下仅说明相异处，而不再赘述相同处。
如图4A至图4B所示，提供一封装组件3’，其包含一已切单的承载结构3a’及结合该承载结构3a’的电子元件40，再将该封装组件3’透过多个导电元件45堆叠于该整版面的线路结构2a上，并形成多个外接元件42于该承载结构3a’的第二侧30b上以电性连接该承载结构3a’的布线层33。
如图4C所示，形成一封装层41于该整版面的线路结构2a上，以令该封装层41包覆该电子元件40、该些导电元件45、该些导电凸块35、该外接元件42的部分侧面与该已切单的承载结构3a’。
如图4D所示，透过如研磨的制程移除该第一承载件20，且沿图4C所示的切割路径S进行切单制程，以获取封装堆叠结构4”。
请参阅图5A至图5C，其为接续图2B的制程的封装堆叠结构的制法的第四实施例的剖面示意图。本实施例与第一实施例的差异在于封装组件3’的制程，其它制程大致相同，故以下仅说明相异处，而不再赘述相同处。
如图5A所示，提供一封装组件3’，其包含一已切单的承载结构3a’及结合该承载结构3a’的电子元件40，再将该封装组件3’透过多个导电元件45堆叠于已切单的线路结构2a’上。
如图5B所示，形成一封装层41于该已切单的线路结构2a’与该已切单的承载结构3a’之间，以令该封装层41包覆该电子元件40、该些导电元件45、该些导电凸块35、该已切单的线路结构2a’与该已切单的承载结构3a’。
如图5C所示，透过如研磨的制程移除该第一承载件20，且沿图5B所示的切割路径S进行切单制程，以获取如图2F所示的封装堆叠结构2’。
本发明的制法经由无核心层式(coreless)线路结构2a,2a’的设计，以减少该封装堆叠结构2’,4’的厚度L，且经由承载件(即该第一承载件20或第二承载件20’)的配置，以强化该线路结构2a,2a’的结构强度，例如，该线路结构2a2a’的厚度T最薄为20微米，且该封装堆叠结构2’,4’,4”的厚度L最小可为410微米，故相较于悉知技术，本发明的制法不仅能大幅降低该封装堆叠结构2’,4’,4”的整体厚度，以符合电子产品轻薄短小的趋势，且于堆叠该线路结构2a,2a’至该承载结构3a,3a’前，能避免该线路结构2a,2a’发生翘曲的问题。
本发明还提供一种封装堆叠结构2,2’,4,4’,4”，包括：一承载结构3a,3a’、一线路结构2a,2a’以及一封装层41。
所述的承载结构3a,3a’定义有相对的第一侧30a与第二侧30b，其中，该承载结构3a,3a’的第一侧30a设有至少一电子元件40。
所述的线路结构2a,2a’的其中一侧设有承载件(即该第一承载件20或第二承载件20’)，而另一侧以多个导电元件45结合至该承载结构3a,3a’的第一侧30a上。
所述的封装层41形成于该线路结构2a,2a’与该承载结构3a,3a’的第一侧30a之间，以包覆该些导电元件45与该电子元件40。
于一实施例中，该承载件(即该第一承载件20)为硅晶圆，其接触结合该线路结构2a,2a’的介电材(即该介电层200)。
于一实施例中，该线路结构2a,2a’具有相对的第一表面21a与第二表面21b，且该第一表面21a结合于该承载件(即该第一承载件20)上，而该第二表面21b配置有多个堆叠接点212,212’，以结合该些导电元件45。
于一实施例中，该承载件(即该第二承载件20’)为玻璃，其以结合层20b接触结合该线路结构2a的介电材(即该介电体210)。
于一实施例中，该线路结构2a,2a’具有相对的第一表面21a与第二表面21b，且该第二表面21b结合于该承载件(即该第二承载件20’)上，而该第一表面21a配置有多个堆叠接点290(或该金属层22)，以结合该些导电元件45。
综上所述，本发明的封装堆叠结构及其制法暨封装结构，经由无核心层式线路结构的设计，以减少该封装堆叠结构的厚度，且经由将承载件配置于线路结构上，以强化该线路结构的结构强度，故本发明不仅能大幅降低该封装堆叠结构的整体厚度，且能避免该线路结构发生翘曲的问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (28)

1.一种封装堆叠结构，其特征在于，该封装堆叠结构包括：
承载结构，其定义有相对的第一侧与第二侧，其中，该承载结构的第一侧设有至少一电子元件；以及
线路结构，其具有相对的第一表面与第二表面，且该第一表面设有承载件，而该第二表面以多个导电元件结合至该承载结构的第一侧上。
2.根据权利要求1所述的封装堆叠结构，其特征在于，该承载件为硅晶圆，其接触结合该线路结构的介电材。
3.根据权利要求1所述的封装堆叠结构，其特征在于，该线路结构为线路重布层结构。
4.根据权利要求1所述的封装堆叠结构，其特征在于，该线路结构的第二表面配置有多个堆叠接点，以结合该些导电元件。
5.根据权利要求1所述的封装堆叠结构，其特征在于，该承载件为玻璃，其以结合层接触结合该线路结构的介电材。
6.根据权利要求1所述的封装堆叠结构，其特征在于，该封装堆叠结构还包括封装层，其形成于该线路结构与该承载结构之间，以包覆该些导电元件与该电子元件。
7.根据权利要求1所述的封装堆叠结构，其特征在于，该导电元件为焊球、金属柱或包覆有绝缘块的金属凸块。
8.一种封装堆叠结构的制法，其特征在于，该制法包括：
提供一设有承载件的线路结构及一承载结构，其中，该承载结构定义有相对的第一侧与第二侧，且该承载结构的第一侧设有至少一电子元件；
将该线路结构以多个导电元件结合至该承载结构的第一侧上，且形成封装层于该线路结构与该承载结构之间，以令该封装层包覆该些导电元件与该电子元件；以及
移除该承载件。
9.根据权利要求8所述的封装堆叠结构的制法，其特征在于，该些导电元件先设于该线路结构上，再将该线路结构以该些导电元件结合至该承载结构上。
10.根据权利要求8所述的封装堆叠结构的制法，其特征在于，该些导电元件先设于该承载结构上，再将该线路结构以该些导电元件结合至该承载结构上。
11.根据权利要求8所述的封装堆叠结构的制法，其特征在于，该承载件为硅晶圆，其接触结合该线路结构的介电材。
12.根据权利要求11所述的封装堆叠结构的制法，其特征在于，该承载件的移除以研磨方式为之。
13.根据权利要求8所述的封装堆叠结构的制法，其特征在于，该线路结构为线路重布层结构。
14.根据权利要求8所述的封装堆叠结构的制法，其特征在于，该线路结构具有相对的第一表面与第二表面，且该第一表面结合于该承载件上，而该第二表面配置有多个堆叠接点，以结合该些导电元件。
15.根据权利要求8所述的封装堆叠结构的制法，其特征在于，该承载件为玻璃，其以结合层接触结合该线路结构的介电材。
16.根据权利要求15所述的封装堆叠结构的制法，其特征在于，其以剥离方式移除该承载件及该结合层。
17.根据权利要求16所述的封装堆叠结构的制法，其特征在于，该线路结构于结合该承载结构前为已切单型态，且于移除该承载件前，进行半切。
18.根据权利要求8所述的封装堆叠结构的制法，其特征在于，该导电元件为焊球、金属柱或包覆有绝缘块的金属凸块。
19.根据权利要求8所述的封装堆叠结构的制法，其特征在于，该线路结构于结合该承载结构前为已切单型态，该承载结构于结合该线路结构前为整版面型态。
20.根据权利要求8所述的封装堆叠结构的制法，其特征在于，该线路结构于结合该承载结构前为整版面型态，该承载结构于结合该线路结构前为整版面型态。
21.根据权利要求8所述的封装堆叠结构的制法，其特征在于，该线路结构于结合该承载结构前为已切单型态，该承载结构于结合该线路结构前为已切单型态。
22.根据权利要求8所述的封装堆叠结构的制法，其特征在于，该线路结构于结合该承载结构前为整版面型态，该承载结构于结合该线路结构前为已切单型态。
23.根据权利要求18、19或22所述的其中一者的封装堆叠结构的制法，其特征在于，于移除该承载件后，进行切单。
24.一种封装结构，其特征在于，该封装结构包括：
线路结构，其具有相对的两侧；
承载件，其设于该线路结构的其中一侧；以及
导电元件，其设于该线路结构的另一侧以电性连接该线路结构。
25.根据权利要求24项所述的封装结构，其特征在于，该线路结构为线路重布层结构。
26.根据权利要求24项所述的封装结构，其特征在于，该承载件为硅晶圆，其接触结合该线路结构的介电材。
27.根据权利要求24项所述的封装结构，其特征在于，该承载件为玻璃，其以结合层接触结合该线路结构的介电材。
28.根据权利要求24项所述的封装结构，其特征在于，该导电元件为焊球、金属柱或包覆有绝缘块的金属凸块。
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