TWI689067B - 電子封裝件及其製法 - Google Patents
電子封裝件及其製法 Download PDFInfo
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- TWI689067B TWI689067B TW107131134A TW107131134A TWI689067B TW I689067 B TWI689067 B TW I689067B TW 107131134 A TW107131134 A TW 107131134A TW 107131134 A TW107131134 A TW 107131134A TW I689067 B TWI689067 B TW I689067B
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- 238000000034 method Methods 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 28
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 239000012790 adhesive layer Substances 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 7
- 239000008393 encapsulating agent Substances 0.000 abstract description 4
- 239000011295 pitch Substances 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 28
- 239000010410 layer Substances 0.000 description 17
- 229910000679 solder Inorganic materials 0.000 description 13
- 235000012431 wafers Nutrition 0.000 description 9
- 239000004593 Epoxy Substances 0.000 description 7
- 238000000465 moulding Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000000945 filler Substances 0.000 description 5
- 239000000047 product Substances 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000005266 casting Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/53204—Conductive materials
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- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
一種電子封裝件,係於一側設有第一電子元件之線路結構之另一側上設置第二電子元件與導電柱,且藉由封裝體包覆該第二電子元件與導電柱,令該導電柱之一端面外露於該封裝體,以藉由該導電柱之外露端面外接一電路板,故藉由該導電柱之端面作為接點,以利於細間距之封裝需求,並且藉由該導電柱呈高腳結構所提供的充足空間特徵,得以令該第二電子元件不用薄型化而能保有適當的厚度以確保其結構強度及滿足大電壓、大電流的使用功能需求。本發明復提供該電子封裝件之製法。
Description
本發明係有關一種半導體封裝技術,尤指一種多晶片型電子封裝件及其製法。
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足電子封裝件微型化(miniaturization)的封裝需求,係發展出晶片級封裝(Chip Scale Package,簡稱CSP)的技術。
第1A至1E圖係為習知半導體封裝件1之製法之剖面示意圖。
如第1A圖所示,形成一離形層100於一承載件10上。接著,置放複數半導體晶片11於該離形層100上,該些半導體晶片11具有相對之作用面11a與非作用面11b,該作用面11a上均具有複數電極墊110,且該作用面11a黏貼於該離形層100上。
如第1B圖所示,形成一封裝膠體14於該離形層100上,以包覆該些半導體晶片11。
如第1C圖所示,移除該離形層100與該承載件10,
使該些半導體晶片11之作用面11a外露。
如第1D圖所示,形成一線路結構16於該封裝膠體14與該些半導體晶片11之作用面11a上,令該線路結構16電性連接該電極墊110。接著,形成一絕緣保護層18於該線路結構16上,且該絕緣保護層18外露該線路結構16之部分表面,以供結合焊錫凸塊17。
如第1E圖所示,沿如第1D圖所示之切割路徑L進行切單製程,以獲取複數個半導體封裝件1,俾藉由回焊該焊錫凸塊17而電性連接於一電路板(圖略)上。
惟,習知半導體封裝件1為了符合微小化之需求,該線路結構16之線路間距愈來愈小,致使該些焊錫凸塊17的間距也縮小,故於回焊該焊錫凸塊17後,相鄰的焊錫凸塊17容易橋接(bridge)而發生短路,導致產品良率下降及可靠度不佳。
再者,習知半導體封裝件1為了符合終端產品之多功能及高功效之需求,故於切單製程時,係將複數個半導體晶片11形成於同一平面上(如第1E圖所示),因而該半導體封裝件1之整體結構之平面面積過大,進而難以縮小終端產品之體積。
又,為了滿足該半導體封裝件1之薄型化整體封裝厚度的需求,因而會薄化該半導體晶片11,但薄化後的半導體晶片11的結構強度往往不足,致使該半導體晶片11容易碎裂,且薄型半導體晶片11的積體電路佈設空間有限,致使該半導體晶片11無法滿足大電壓大電流的使用功能
需求。
因此,如何縮小習知多晶片之半導體封裝件的佔用面積,確保晶片的結構強度,以及滿足大電壓、大電流的使用需求,實已成目前亟欲解決的課題。
鑒於上述習知技術之缺失,本發明提供一種電子封裝件,係包括:線路結構,係具有相對之第一側與第二側;第一電子元件,係設於該線路結構之第一側上;第一封裝體,係包覆該第一電子元件;第二電子元件,係設於該線路結構之第二側上;複數導電柱,係形成於該線路結構之第二側上且電性連接該線路結構;以及第二封裝體,係包覆該第二電子元件與該導電柱,且該第二封裝體具有一結合該線路結構之第一表面與一相對該第一表面之第二表面,令該導電柱之一端面外露於該第二封裝體之第二表面。
本發明亦提供一種電子封裝件之製法,係包括:提供一封裝組件,係包含有具相對之第一側與第二側之線路結構、設於該線路結構之第一側上之第一電子元件及包覆該第一電子元件之第一封裝體;於該線路結構之第二側上設置第二電子元件,且於該線路結構之第二側上形成複數電性連接該線路結構之導電柱;於該線路結構之第二側上形成第二封裝體,以令該第二封裝體包覆該第二電子元件與該導電柱,其中,該第二封裝體具有一結合該線路結構之第一表面與一相對該第一表面之第二表面;以及移除部分該第二封裝體,以令該導電柱之端面外露於該第二封裝體
之第二表面。
前述之電子封裝件及其製法中,該線路結構係包含有複數電性連接該第一電子元件之導電盲孔柱。
前述之電子封裝件及其製法中,該第一電子元件係具有相對之作用面與非作用面,且該作用面電性連接該線路結構。例如,該第一電子元件之非作用面係外露於該第一封裝體。
前述之電子封裝件及其製法中,該第二電子元件係具有相對之作用面與非作用面,且該作用面電性連接該線路結構。例如,該第二電子元件係以覆晶方式電性連接該線路結構。或者,該第二電子元件之非作用面外露於該第二封裝體之第二表面。
前述之電子封裝件及其製法中,該導電柱係為銅柱。
前述之電子封裝件及其製法中,該導電柱與線路結構第二側之間係設有一導電黏著層。
前述之電子封裝件及其製法中,復包括形成導電元件於該導電柱之端面上。
由上可知,本發明之電子封裝件及其製法,主要藉由該導電柱作為接點結構,且該導電柱所佔的空間較焊球小,故相較於習知技術,本發明之電子封裝件有利於細間距之封裝需求,並能避免焊料橋接之問題,更可藉由導電柱高腳結構所提供的充足空間,令晶片不用薄型化而能保有適當的厚度藉以提供足夠的積體電路佈設空間及維持其結構強度,以滿足大電壓、大電流之使用功能需求,更因而能
提高產品良率。
再者,該線路結構之第一側與第二側上分別設有第一電子元件與第二電子元件,以形成立體式堆疊設計,故相較於習知多晶片平面佈設之設計,本發明可大幅縮小該電子封裝件之平面面積,且符合多功能及高功效之需求。
1,2,2’,2”‧‧‧半導體封裝件
10‧‧‧承載件
100‧‧‧離形層
11‧‧‧半導體晶片
11a‧‧‧作用面
11b‧‧‧非作用面
110‧‧‧電極墊
14‧‧‧封裝膠體
16‧‧‧線路結構
17‧‧‧焊錫凸塊
18‧‧‧絕緣保護層
2a‧‧‧封裝組件
20‧‧‧線路結構
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧絕緣層
201‧‧‧線路層
202‧‧‧導電盲孔柱
203‧‧‧第一電性接觸墊
204‧‧‧第二電性接觸墊
21‧‧‧第一電子元件
21a,22a‧‧‧作用面
21b,22b‧‧‧非作用面
210,220‧‧‧電極墊
22‧‧‧第二電子元件
221‧‧‧導電凸塊
23‧‧‧導電柱
23a‧‧‧端面
24‧‧‧第一封裝體
24a‧‧‧表面
25‧‧‧第二封裝體
25a‧‧‧第一表面
25b,25b’‧‧‧第二表面
27‧‧‧導電元件
3‧‧‧電子裝置
L‧‧‧切割路徑
第1A至1E圖係為習知半導體封裝件之製法之剖面示意圖。
第2A至2D圖係為本發明之電子封裝件之製法的剖面示意圖。
第2C’及2C”圖係為第2C圖之其它不同實施例的剖面示意圖。
第2D’及2D”圖係為第2D圖之其它不同實施例的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術
內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示,提供一封裝組件2a,其包含一線路結構20、至少一第一電子元件21及一第一封裝體24。
於本實施例中,該封裝組件2a之製法可參考如第1A至1E圖所示之製法,但不限於此述。
所述之線路結構20具有相對之第一側20a與第二側20b。於本實施例中,該線路結構20係包括至少一絕緣層200、設於該絕緣層200上之線路層201、及複數設於該絕緣層200中並電性連接該線路層201之導電盲孔柱202。例如,形成該線路層201之材質例如是金、銀、銅或其它類似之導電材質,且形成該絕緣層200之材質係如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等之介電材。
再者,於該線路結構20之第二側20b之部分該線路層201係定義為第一電性接觸墊203與第二電性接觸墊204。
所述之第一電子元件21係結合於該線路結構20之第一側20a上,且該第一電子元件21係為主動元件、被動元件或其二者組合,其中,該主動元件係例如半導體晶片,
而該被動元件係例如電阻、電容及電感。例如,該第一電子元件21係為半導體晶片,其具有相對之作用面21a與非作用面21b,該作用面21a具有複數電極墊210以電性連接該導電盲孔柱202。或者,該第一電子元件21以其作用面21a可藉由覆晶方式電性連接該線路層201;亦或,該第一電子元件21可藉由複數銲線(圖略)以打線方式電性連接該線路層201。然而,有關該第一電子元件21電性連接該線路結構20之方式不限於上述。
所述之第一封裝體24係以鑄模方式、塗佈方式或壓合方式形成於該線路結構20之第一側20a上,且形成該第一封裝體24之材質係為介電材料,該介電材料可為環氧樹脂(Epoxy),且該環氧樹脂更包含鑄模化合物(Molding Compound)或底層塗料(Primer),如環氧模壓樹脂(Epoxy Molding Compound,簡稱EMC),其中,該環氧模壓樹脂係含有充填物(filler),且該充填物含量為70至90wt%。
如第2B圖所示,設置第二電子元件22於該線路結構20之第一電性接觸墊203上,且於該線路結構20之第二側20b上形成複數導電柱23。
於本實施例中,該第二電子元件22係為主動元件、被動元件或其二者組合,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。例如,該第二電子元件22係為半導體晶片,其具有相對之作用面22a與非作用面22b,該作用面22a具有複數電極墊220,且該些電極墊220上係結合複數導電凸塊221以覆晶方式電性連接
該些第一電性接觸墊203,其中,該導電凸塊221係如焊球、銅柱、焊錫凸塊等金屬材,但不限於此。或者,該第二電子元件22可直接接觸該些第一電性接觸墊203。然而,有關該第二電子元件22電性連接該些第一電性接觸墊203之方式不限於上述。
再者,該導電柱23係如銅柱或其它金屬材之柱體,其接觸結合及電性連接該第二電性接觸墊204。
又,該導電柱23可配合該第二電性接觸墊204之形狀或其它設計需求而呈現圓形柱、矩形柱或其它任意形狀柱體,但不以上述為限。
另外,該導電柱23可藉由電鍍或其他沉積方式直接形成於該第二電性接觸墊204上。或者,該導電柱23可先預製成型,再藉一如銀膠或銅膏之導電黏著層(圖略)接合於該第二電性接觸墊204上。因此,有關該導電柱23之製程並無特別限制。
如第2C圖所示,形成一第二封裝體25於該線路結構20之第二側20b上,以令該第二封裝體25包覆該第二電子元件22與該些導電柱23,其中,該第二封裝體25具有一結合該線路結構20之第一表面25a與一相對該第一表面25a之第二表面25b。接著,移除部分該第二封裝體25,使該些導電柱23之一端面23a外露出於該第二封裝體25之第二表面25b。
於本實施例中,形成該第二封裝體25之材質係為介電材料,該介電材料可為環氧樹脂(Epoxy),且該環氧樹脂更
包含鑄模化合物(Molding Compound)或底層塗料(Primer),如環氧模壓樹脂(Epoxy Molding Compound,簡稱EMC),其中,該環氧模壓樹脂係含有充填物(filler),且該充填物含量為70至90wt%。
再者,該第一封裝體24之材質與該第二封裝體25之材質可相同或不相同。
又,藉由整平製程,使該第二電子元件22之非作用面22b與該些導電柱23之一端面23a同時外露於該第二封裝體25之第二表面25b’,如第2C’圖所示。
另外,於其它實施例中,亦可藉由整平製程(如研磨方式),使該第一電子元件21之非作用面21b外露於該第一封裝體24,如第2C”圖所示。
如第2D圖所示,接續第2C圖所示之製程,形成複數如焊球之導電元件27於該些導電柱23之外露端面23a上,俾供後續接置於如封裝結構、電路板或晶片等之電子裝置3上。同理可知,接續第2C’及2C”圖所示之製程,亦可形成複數導電元件27於該些導電柱23之外露端面23a上,俾供後續接置於電子裝置3上,如第2D’及2D”圖所示。
因此,本發明之電子封裝件2,2’,2”之製法係藉由該導電柱23之端面23a外露出該第二封裝體25之第二表面25b,25b’,以令該端面23a作為接點結構,且該導電柱23所佔的空間較焊球小,故相較於習知技術,本發明之電子封裝件2有利於細間距(fine pitch)之封裝需求,並能避免焊料橋接之問題,又可藉由導電柱23高腳結構所提供的充
足空間,令第二電子元件22能保有適當的厚度而維持結構強度及增加積體電路佈設之空間,以滿足大電壓、大電流之使用功能需求,更因而能提高產品良率。
再者,該線路結構20之第一側20a與第二側20b上分別設有第一電子元件21與第二電子元件22,以形成立體式堆疊設計,故相較於習知半導體封裝件之多晶片平面佈設之設計,本發明之製法可大幅縮小該電子封裝件2之平面面積,且符合多功能及高功效之需求。
本發明亦提供一種電子封裝件2,2’,2”(請配合參閱第2D、2D’及2D”圖所示),其包括:一線路結構20、至少一第一電子元件21、一第一封裝體24、至少一第二電子元件22、一第二封裝體25以及複數導電柱23。
所述之線路結構20係具有相對之第一側20a與第二側20b。
所述之第一電子元件21係結合於該線路結構20之第一側20a上。
所述之第一封裝體24係形成於該線路結構20之第一側20a上,以令該第一封裝體24包覆該第一電子元件21。
所述之第二電子元件22係設於該線路結構20之第二側20b上。
所述之導電柱23係形成於該線路結構20之第二側20b上並電性連接該線路結構20。
所述之第二封裝體25係形成於該線路結構20之第二側20b上,以包覆該第二電子元件22與該些導電柱23,
且該第二封裝體25具有一結合該線路結構20之第一表面25a與一相對該第一表面25a之第二表面25b,25b’,令該導電柱23之端面23a外露於該第二封裝體25之第二表面25b,25b’。
於一實施例中,該線路結構20係包含有複數電性連接該第一電子元件21之導電盲孔柱202。
於一實施例中,該第一電子元件21係具有相對之作用面21a與非作用面21b,且該作用面21a電性連接該線路結構20。例如,於第2C”及2D”圖所示之電子封裝件2”中,該第一電子元件21之非作用面21b係外露於該第一封裝體24之表面24a。
於一實施例中,該第二電子元件22係具有相對之作用面22a與非作用面22b,且該作用面22a電性連接該線路結構20。例如,該第二電子元件22係以覆晶方式電性連接該線路結構20。或者,於第2C’、2D’及2C”、2D”圖所示之電子封裝件2’,2”中,該第二電子元件22之非作用面22b外露於該第二封裝體25之第二表面25b’。
於一實施例中,該導電柱23係為銅柱。
於一實施例中,該導電柱23之端面23a係外露於該第二封裝體25之第二表面25b,25b’。
於一實施例中,該電子封裝件2,2’,2”復包括複數導電元件27,係形成於該導電柱23之端面23a上。
於一實施例中,該導電柱23與該線路結構20第二側20b之第二電性接觸墊204之間係設有一導電黏著層(如
銅膏或銀膠)。
綜上所述,本發明之電子封裝件及其製法,係藉由該導電柱之設計,以利於細間距之封裝需求,以及令晶片不用薄型化而能保有適當的厚度藉以提供足夠的積體電路佈設空間及維持其結構強度,進而滿足大電壓、大電流之使用功能需求,且能提高產品良率。
再者,該線路結構之第一側與第二側上分別設有第一電子元件與第二電子元件,以形成立體式堆疊設計,故能大幅縮小該電子封裝件之平面面積,且符合多功能及高功效之需求。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
20‧‧‧線路結構
20a‧‧‧第一側
20b‧‧‧第二側
21‧‧‧第一電子元件
22‧‧‧第二電子元件
23‧‧‧導電柱
23a‧‧‧端面
24‧‧‧第一封裝體
25‧‧‧第二封裝體
25a‧‧‧第一表面
25b‧‧‧第二表面
Claims (16)
- 一種電子封裝件,係包括:線路結構,係具有相對之第一側與第二側,且該線路結構係包含有複數導電盲孔柱;第一電子元件,係設於該線路結構之第一側上,其中,該第一電子元件係具有相對之作用面與非作用面,且該作用面具有複數電極墊,以令該電極墊接觸該導電盲孔柱,使該第一電子元件電性連接該線路結構;第一封裝體,係包覆該第一電子元件;第二電子元件,係設於該線路結構之第二側上;複數導電柱,係形成於該線路結構之第二側上且電性連接該線路結構,其中,該導電柱自其中一端面至另一端面之寬度係維持一致;以及第二封裝體,係包覆該第二電子元件與該導電柱,且該第二封裝體具有一結合該線路結構之第一表面與一相對該第一表面之第二表面,令該導電柱之其中一端面外露於該第二封裝體之第二表面。
- 如申請專利範圍第1項所述之電子封裝件,其中,該第一電子元件之非作用面係外露於該第一封裝體。
- 如申請專利範圍第1項所述之電子封裝件,其中,該第二電子元件係具有相對之作用面與非作用面,且該第二電子元件之作用面電性連接該線路結構。
- 如申請專利範圍第3項所述之電子封裝件,其中,該第二電子元件係以覆晶方式電性連接該線路結構。
- 如申請專利範圍第3項所述之電子封裝件,其中,該第二電子元件之非作用面外露於該第二封裝體之第二表面。
- 如申請專利範圍第1項所述之電子封裝件,其中,該導電柱係為銅柱。
- 如申請專利範圍第1項所述之電子封裝件,其中,該導電柱與線路結構第二側之間係設有一導電黏著層。
- 如申請專利範圍第1項所述之電子封裝件,復包括形成於該導電柱之端面上之導電元件。
- 一種電子封裝件之製法,係包括:提供一封裝組件,係包含有具相對之第一側與第二側之線路結構、設於該線路結構之第一側上之第一電子元件及設於該線路結構之第一側上以包覆該第一電子元件之第一封裝體,其中,該線路結構係包含有複數導電盲孔柱,且該第一電子元件係具有相對之作用面與非作用面,該作用面具有複數電極墊,以令該電極墊接觸該導電盲孔柱,使該第一電子元件電性連接該線路結構;待提供該封裝組件後,於該線路結構之第二側上設置第二電子元件,且於該線路結構之第二側上形成複數電性連接該線路結構之導電柱;於該線路結構之第二側上形成第二封裝體,以令該第二封裝體包覆該第二電子元件與該導電柱,其中,該第二封裝體具有一結合該線路結構之第一表面與一 相對該第一表面之第二表面;以及移除部分該第二封裝體,以令該導電柱之端面外露於該第二封裝體之第二表面。
- 如申請專利範圍第9項所述之電子封裝件之製法,其中,該第一電子元件之非作用面係外露於該第一封裝體。
- 如申請專利範圍第9項所述之電子封裝件之製法,其中,該第二電子元件係具有相對之作用面與非作用面,且該第二電子元件之作用面電性連接該線路結構。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該第二電子元件係以覆晶方式電性連接該線路結構。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該第二電子元件之非作用面外露於該第二封裝體之第二表面。
- 如申請專利範圍第9項所述之電子封裝件之製法,其中,該導電柱係為銅柱。
- 如申請專利範圍第9項所述之電子封裝件之製法,其中,該導電柱與線路結構第二側之間係形成有一導電黏著層。
- 如申請專利範圍第9項所述之電子封裝件之製法,復包括形成導電元件於該導電柱之端面上。
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