TW202046456A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TW202046456A
TW202046456A TW108119514A TW108119514A TW202046456A TW 202046456 A TW202046456 A TW 202046456A TW 108119514 A TW108119514 A TW 108119514A TW 108119514 A TW108119514 A TW 108119514A TW 202046456 A TW202046456 A TW 202046456A
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supporting structure
electronic
electrically connected
manufacturing
electronic package
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TW108119514A
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TWI723414B (zh
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王隆源
高灃
葉懋華
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矽品精密工業股份有限公司
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Priority to TW108119514A priority Critical patent/TWI723414B/zh
Priority to CN201910541797.9A priority patent/CN112054005B/zh
Priority to US16/673,078 priority patent/US11152331B2/en
Publication of TW202046456A publication Critical patent/TW202046456A/zh
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Publication of TWI723414B publication Critical patent/TWI723414B/zh
Priority to US17/481,610 priority patent/US12009340B2/en

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Abstract

一種電子封裝件及其製法，係將兩封裝模組相堆疊，以於後續製作電子產品時，減少電子封裝件佔用母板之面積，因而有利於縮減該電子產品之體積。

Description

電子封裝件及其製法
本發明係關於一種半導體封裝製程，特別是關於一種具有多個封裝模組之電子封裝件及其製法。
隨著近年來可攜式電子產品的蓬勃發展，各類相關產品之開發亦朝向高密度、高性能以及輕、薄、短、小之趨勢，各態樣的半導體封裝結構也因而配合推陳出新，以期能符合輕薄短小與高密度的要求。
因應可攜式電子產品功能越強大，所需半導體封裝結構將越多，故半導體封裝結構之配置趨勢係採用多模組(Multichip Module)形式，俾藉此將兩個或兩個以上之半導體封裝件組合在單一電子產品中，以縮減電子產品整體電路結構體積，並提昇電性功能。
如第1圖所示，習知電子產品1係包括一母板(Mother board)10及設於該母板10上之複數半導體封裝模組1a,1b。
惟，習知電子產品1中，該母板10的表面需同時水平排設許多半導體封裝模組1a,1b，造成佔據該母板10之空間越多，故無法設計出足夠的空間放置其它封裝模組，或是電池容量無法增大而受到限制。另一 方面，若將該母板10的表面積擴增，將迫使該電子產品1的體積增大，導致該電子產品1不符合輕薄短小之發展潮流。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種電子封裝件，係包括：一第一承載結構，係具有相對之第一表面與第二表面；至少一第一電子元件，係配置於該第一承載結構之第一表面上且電性連接該第一承載結構；複數導電體，係設於該第一承載結構之第二表面上且電性連接該第一承載結構；一第二承載結構，係藉由至少一導電元件堆疊於該第一承載結構之第一表面上，且令該導電元件電性連接該第一與第二承載結構；至少一功能電子元件，係配置於該第二承載結構上且電性連接該第二承載結構；以及一封裝層，係形成於該第一承載結構與該第二承載結構之間以包覆該第一電子元件、功能電子元件與導電元件。
本發明復提供一種電子封裝件之製法，係包括：提供一具有相對之第一表面與第二表面之第一承載結構，其中，該第一表面上配置有至少一電性連接該第一承載結構之第一電子元件，該第二表面上配置有複數電性連接該第一承載結構之導電體；將一配置有功能電子元件之第二承載結構藉由至少一導電元件堆疊於該第一承載結構之第一表面上，且令該導電元件電性連接該第一與第二承載結構，其中，該功能電子元件電性連接該第二承載結構；以及形成封裝層於該第一承載結構與該第二承載結構之間，以令該封裝層包覆該第一電子元件、功能電子元件與導電元件。
前述之製法中，該導電元件係先設於該第二承載結構上，再將該導電元件結合至該第一承載結構上。
前述之製法中，該導電元件係先設於該第一承載結構之第一表面上，再將該第二承載結構結合至該導電元件上。
本發明又提供一種電子封裝件之製法，係包括：提供一具有相對之第一表面與第二表面之第一承載結構與一配置有功能電子元件之第二承載結構，其中，該第一表面上配置有至少一電性連接該第一承載結構之第一電子元件，且該第二表面上配置有複數電性連接該第一承載結構之導電體；形成至少一導電元件於該第一承載結構之第一表面或該第二承載結構上，且形成封裝層於該第一承載結構之第一表面或該第二承載結構上；以及藉由該導電元件堆疊該第一承載結構與該第二承載結構，使該封裝層位於該第一承載結構與該第二承載結構之間，以令該封裝層包覆該第一電子元件、功能電子元件與導電元件。
前述之製法中，於堆疊該第一承載結構與該第二承載結構前，該導電元件係設於該第一承載結構與該第二承載結構之其中一者，且該封裝層形成於該第一承載結構與該第二承載結構之另一者。
前述之製法中，於堆疊該第一承載結構與該第二承載結構前，該導電元件係設於該第一承載結構與該第二承載結構之其中一者，且該封裝層係包覆該導電元件。
前述之電子封裝件及其兩種製法中，該第一承載結構之第二表面上設有至少一電性連接該第一承載結構之第二電子元件。
前述之電子封裝件及其兩種製法中，該第一承載結構之第二表面上設有一包覆該複數導電體之包覆層。例如，該導電體之部分表面外露於該包覆層。或者，該第一承載結構之第二表面上設有至少一電性連 接該第一承載結構之第二電子元件，且該包覆層包覆該第二電子元件，例如，該第二電子元件之部分表面外露於該包覆層。
前述之電子封裝件及其兩種製法中，該功能電子元件係位於該第一承載結構之第一表面與該第二承載結構之間。
前述之電子封裝件及其兩種製法中，該功能電子元件與該第一電子元件之配置係相疊合。
前述之電子封裝件及其兩種製法中，復包括配置屏蔽結構於該第一承載結構或該第二承載結構上，且該封裝層包覆該屏蔽結構。
由上可知，本發明之電子封裝件及其製法中，主要藉由將兩承載結構相堆疊，以於後續製作電子產品時，能減少該電子封裝件佔用母板的空間或表面積，故相較於習知技術，本發明之電子封裝件不僅能使母板有足夠的空間放置其它封裝模組或增加電池容量，且有利於縮減該電子產品之體積，使該電子產品符合輕薄短小之發展潮流。
1‧‧‧電子產品
1a,1b‧‧‧半導體封裝模組
10‧‧‧母板
2‧‧‧電子封裝件
2a,2b‧‧‧封裝模組
20‧‧‧第一承載結構
20a‧‧‧第一表面
20b‧‧‧第二表面
21,21’‧‧‧第一電子元件
210,220,230‧‧‧導電凸塊
22‧‧‧第二電子元件
23‧‧‧功能電子元件
24‧‧‧第二承載結構
25‧‧‧導電元件
26‧‧‧屏蔽結構
27‧‧‧封裝層
28,28’‧‧‧導電體
28a‧‧‧端面
29‧‧‧包覆層
29a‧‧‧表面
290‧‧‧開孔
9‧‧‧電子裝置
90‧‧‧銲錫凸塊
A‧‧‧側面交錯處
D‧‧‧距離
S‧‧‧切割路徑
第1圖係為習知電子產品之立體示意圖。
第2A至2E圖係為本發明之電子封裝件之製法之第一實施例之剖面示意圖。
第2B’及2B”圖係為第2B圖之不同實施方式之示意圖。
第2D’及2D”圖係為第2D圖之其它不同態樣之局部示意圖。
第2E’圖係為第2E圖之另一態樣之局部示意圖。
第3A至3C圖係為本發明之電子封裝件之製法之第二實施例之剖面示意圖。
第3A’圖係為第3A圖之另一實施方式之示意圖。
第4A至4C圖係為本發明之電子封裝件之屏蔽結構之不同佈設狀態之上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之電子封裝件2之製法之第一實施例的剖面示意圖。
如第2A圖所示，提供一封裝模組2a，其包含一第一承載結構20、至少一第一電子元件(本實施例中係顯示有兩個第一電子元件21,21’)及複數導電體28。
所述之第一承載結構20係為整版面基板形式，即該整版面基板包含複數基板單元，例如為具有核心層與線路結構之封裝基板或無核心層(coreless)之線路結構，其具有相對之第一表面20a與第二表面20b，且該線路結構係包含至少一絕緣層及至少一結合該絕緣層之線路層，如至少一扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)。應可理解地，該第一承載結構20亦可為其它承載晶片之板材，如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之載板等，並不限於上述。
於本實施例中，該第一承載結構20之製程方式繁多，例如，可採用晶圓製程製作線路層，而以化學氣相沉積(Chemical vapor deposition，簡稱CVD)形成氮化矽或氧化矽以作為絕緣層；或者，可採用一般非晶圓製程方式形成線路層，即採用成本較低之高分子介電材作為絕緣層，如聚醯亞胺(Polyimide，簡稱PI)、聚對二唑苯(Polybenzoxazole，簡稱PBO)、預浸材(Prepreg，簡稱PP)、封裝膠體(molding compound)、感光型介電層或其它材質等以塗佈方式形成之。
所述之第一電子元件21,21’係設於該承載結構20之第一表面20a上。
於本實施例中，該第一電子元件21,21’係為主動元件(如圖中標號21)、被動元件(如圖中標號21’)或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第一電子元件21係為半導體晶片，其可藉由複數如銲錫材料、金屬柱 (pillar)或其它等之導電凸塊210以覆晶方式設於該第一承載結構20之線路層上並電性連接該線路層；或者，該第一電子元件21可藉由複數銲線以打線方式電性連接該第一承載結構20之線路層；亦或，該第一電子元件21可直接接觸該第一承載結構20之線路層。另該第一電子元件21’係為被動元件。
再者，可依需求於該承載結構20之第二表面20b上配置第二電子元件22，其係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第二電子元件22係為半導體晶片，其可藉由複數如銲錫材料、金屬柱(pillar)或其它等之導電凸塊220以覆晶方式設於該第一承載結構20之線路層上並電性連接該線路層；或者，該第二電子元件22可藉由複數銲線以打線方式電性連接該第一承載結構20之線路層；亦或，該第二電子元件22可直接接觸該第一承載結構20之線路層。
因此，可於該第一承載結構20之第一表面20a與第二表面20b接置任意種類或數量之電子元件，以提升其電性功能，且有關電子元件電性連接承載結構之方式繁多，並不限於上述。
所述之導電體28係為如銅柱狀之金屬凸塊、銲錫材、金屬針或其它導電構造，其形成於該第一承載結構20之第二表面20b上。
於本實施例中，該導電體28係以圖案化方式，如電鍍金屬、沉積金屬或蝕刻金屬等製程形成於該第一承載結構20之第二表面20b上。
再者，可於該第一承載結構20之第二表面20b上形成一包覆層29，以包覆該些導電體28。具體地，該包覆層29係為絕緣材，如聚醯亞胺(PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或 封裝材(molding compound)，其可用壓合(lamination)、塗佈(coating)或模壓(molding)之方式形成於該第一承載結構20之第二表面20b上。
如第2B圖所示，將另一封裝模組2b(其包含一配置有至少一功能電子元件23之第二承載結構24)藉由一個或複數個導電元件25結合於該第一承載結構20之第一表面20a上。
所述之第二承載結構24係為整版面基板形式，即該整版面基板包含複數基板單元，例如為具有核心層與線路結構之封裝基板或無核心層(coreless)之線路結構，其包含至少一絕緣層及至少一結合該絕緣層之線路層，如至少一扇出(fan out)型重佈線路層(RDL)。應可理解地，該第二承載結構24亦可為其它承載晶片之板材，如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之載板等，並不限於上述。
於本實施例中，該第二承載結構24之製程方式繁多，例如，可採用晶圓製程製作線路層，而以化學氣相沉積(CVD)形成氮化矽或氧化矽以作為絕緣層；或者，可採用一般非晶圓製程方式形成線路層，即採用成本較低之高分子介電材作為絕緣層，如聚醯亞胺(PI)、聚對二唑苯(PBO)、預浸材(PP)、封裝膠體、感光型介電層或其它等以塗佈方式形成之。
所述之功能電子元件23係位於該承載結構20之第一表面20a與該第二承載結構24之間，且其與該第一電子元件21,21’之配置可相疊合(overlap)。例如，該功能電子元件23之側面與該第一電子元件21之側面係相疊合，如側面交錯處A。
於本實施例中，該功能電子元件23係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該功能電子元件23係為半導體晶片，其可藉由複數如銲錫材料、金屬柱(pillar)或其它等之導電凸塊230以覆晶方式設於該第二承載結構24之線路層上並電性連接該線路層；或者，該功能電子元件23可藉由複數銲線以打線方式電性連接該第二承載結構24之線路層；亦或，該功能電子元件23可直接接觸該第二承載結構24之線路層。應可理解地，可於該第二承載結構24上接置任意種類或數量之電子元件，以提升其電性功能，且有關電子元件電性連接承載結構之方式繁多，並不限於上述。
所述之導電元件25係電性連接該第一承載結構20之線路層與第二承載結構24之線路層，其可為如銅柱之金屬柱、包覆有絕緣塊之金屬凸塊、銲球(solder ball)、具有核心銅球(Cu core ball)之銲球或其它導電構造等，且其形狀並未有特殊限制，如圓柱體、橢圓柱體或多邊形柱體皆可。
於本實施例中，該導電元件25可先形成於該第二承載結構24上，再堆疊結合至該第一承載結構20之第一表面20a上，如第2B’圖所示；或者，該導電元件25亦可先形成於該第一承載結構20之第一表面20a上，再將該第二承載結構24堆疊結合至該導電元件25上，如第2B”圖所示。
另一方面，可依需求，於該第一承載結構20之第一表面20a與該第二承載結構24之間形成至少一屏蔽結構26，以防止多個第一電子元件21之間或多個功能電子元件23之間的電磁波相互干擾，且防止外界電磁波干擾該第一電子元件21與功能電子元件23之內部電路。
所述之屏蔽結構26係設於該第一承載結構20之第一表面20a上、該第二承載結構24上或兩側接固於該第一承載結構20與第二承載結構24上，且依需求電性連接該第一承載結構20之接地及/或第二承載結構24之接地，亦可未電性連接該第一承載結構20與第二承載結構24。
於本實施例中，該屏蔽結構26係呈框架狀、牆狀或柱狀，且形成該屏蔽結構26之材質為導電材，如銅、金、鎳或鋁等之金屬，並可以黏貼、電鍍、沉積或其它方式配置於承載結構上。具體地，如第4A圖所示，該屏蔽結構26係佈設於多個第一電子元件21之間或多個功能電子元件23之間；或者，如第4B及4C圖所示，該屏蔽結構26係佈設於所有該第一電子元件21之佈設區域之周圍或所有該功能電子元件23之佈設區域之周圍。應可理解地，有關該屏蔽結構26之構造與設置方式繁多，並不限於上述。
再者，該屏蔽結構26可配合該導電元件25配置於同一承載結構上，如第2B’及2B”圖所示；或者，該屏蔽結構26亦可自行配置，即不需配合該導電元件25配置於同一承載結構上。
如第2C圖所示，形成一封裝層27於該第一承載結構20之第一表面20a與該第二承載結構24之間，以令該封裝層27包覆該第一電子元件21、功能電子元件23、導電元件25與屏蔽結構26。
於本實施例中，該封裝層27接觸該第一承載結構20之第一表面20a與該第二承載結構24，且形成該封裝層27之材質係為絕緣材，如聚醯亞胺(PI)、環氧樹脂(epoxy)之封裝膠體或封裝材，其可用模壓(molding)方式形成。
如第2D圖所示，移除該包覆層29之部分材質，以露出該導電體28之部分表面。
於本實施例中，藉由如研磨方式之整平製程移除該包覆層29之部分材質，使該導電體28之端面28a齊平該包覆層29之表面29a。或者，如第2D’圖所示，以如雷射之鑽孔方式於該包覆層29之表面29a上形成複數外露該導電體28之開孔290。亦或，如第2D”圖所示，於移除該包覆層29之部分材質後，該導電體28之端面28a可凸出該包覆層29之表面29a。
再者，於移除該包覆層29之部分材質後，該第二電子元件22未外露於該包覆層29之表面29a。應可理解地，該第二電子元件22亦可外露於該包覆層29之表面29a，且該第二電子元件22外露之方式可如第2D、2D’或2D”圖所述之導電體28之外露方式。
如第2E圖所示，沿如第2D圖所示之切割路徑S進行切單製程，以得到複數電子封裝件2。
於本實施例中，若該導電體28為非銲錫構造，可形成複數銲錫凸塊90於各該導電體28之外露端面28a上，以於回銲該銲錫凸塊90後接置於一如電路板或母板之電子裝置9上；亦或如第2E’圖所示，若該導電體28’為銲錫材，則回銲該導電體28’以結合至一如電路板或母板之電子裝置9上。
第3A至3C圖係為本發明之電子封裝件2之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於封裝層之製作方式，其它製程大致相同，故以下不再贅述相同處。
如第3A圖所示，對應於第2A圖之製程中，形成一封裝層27於該封裝模組2a之第一承載結構20之第一表面20a上，以令該封裝層27包覆該第一電子元件21,21’，再採用第2B’圖之堆疊方式，將該第二承載 結構24壓合於該封裝層27上，且令該導電元件25與該屏蔽結構26插入該封裝層27中，如第3B圖所示。
於本實施例中，該封裝層27係為如聚醯亞胺(PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或塗佈(coating)之方式形成之。
再者，亦可將該封裝層27形成於該第二承載結構24上以包覆該功能電子元件23，如第3A’圖所示，再採用第2B”圖之堆疊方式，將該第二承載結構24藉由該封裝層27壓合於該第一承載結構20之第一表面20a上，且該第一電子元件21,21’、導電元件25與該屏蔽結構26埋入該封裝層27中，如第3B圖所示。或者，可先將該封裝層27與該導電於件25形成於同一承載結構上，再將另一承載結構壓合於該封裝層27上。
如第3C圖所示，進行第2D至2E圖之製程，且令該第二電子元件22外露於該包覆層29之表面，以獲取該電子封裝件2。
本發明之電子封裝件2之製法中，主要藉由將兩封裝模組2a,2b相堆疊，且以該些導電體28,28’作為外接點，以於後續製作電子產品時，能減少該電子封裝件2佔用該電子裝置9的空間或表面積，故相較於習知技術，本發明之電子封裝件2不僅能使該電子裝置9有足夠的空間放置其它封裝模組或增加電池容量，且有利於縮減該電子產品之體積，使該電子產品符合輕薄短小之發展趨勢。
再者，於該第一承載結構2a上可依需求層層堆疊多組封裝模組2b(或多組配置有功能電子元件23之第二承載結構24)。
又，由於該些導電體28,28’作為外接點，故該第二承載結構24(或最外側之第二承載結構24)之上表面不需設計外接點。
另外，藉由該功能電子元件23與該第一電子元件21,21’之疊合(overlap)配置，可縮減該第一承載結構20與第二承載結構24之間的距離D，以薄化該電子封裝件2。
本發明復提供一種電子封裝件2，其包括：第一承載結構20、第一電子元件21,21’、複數導電體28,28’、第二承載結構24、功能電子元件23以及封裝層27。
所述之第一承載結構20係具有相對之第一表面20a與第二表面20b。
所述之第一電子元件21,21’係設於該第一承載結構20之第一表面20a上且電性連接該第一承載結構20。
所述之導電體28,28’係設於該第一承載結構20之第二表面20b上且電性連接該第一承載結構20。
所述之第二承載結構24係藉由至少一導電元件25堆疊於該第一承載結構20之第一表面20a上，且該導電元件25電性連接該第一與第二承載結構20,24。
所述之功能電子元件23係配置於該第二承載結構24上且電性連接該第二承載結構24。
所述之封裝層27係形成於該第一承載結構20之第一表面20a與該第二承載結構24之間以包覆該第一電子元件21,21’、功能電子元件23與導電元件25。
於一實施例中，該第一承載結構20之第二表面20b上設有至少一電性連接該第一承載結構20之第二電子元件22。
於一實施例中，該第一承載結構20之第二表面20b上設有一包覆該複數導電體28,28’之包覆層29。例如，該導電體28,28’之部分表面外露於該包覆層29。或者，該第一承載結構20之第二表面20b上設有至少一電性連接該第一承載結構20之第二電子元件22，且該包覆層29包覆該第二電子元件22。進一步，該第二電子元件22之部分表面外露於該包覆層29。
於一實施例中，該功能電子元件23係位於該第一承載結構20之第一表面20a與該第二承載結構24之間。
於一實施例中，該功能電子元件23之位置係疊合該第一電子元件21之位置。
於一實施例中，所述之電子封裝件2復包括形成於該第一承載結構20或該第二承載結構24上的屏蔽結構26，且該封裝層27包覆該屏蔽結構26。
綜上所述，本發明之電子封裝件及其製法，主要藉由藉由將兩承載結構相堆疊，以於後續製作電子產品時，能減少電子封裝件佔用母板的空間或表面積，故相較於習知技術，本發明之電子封裝件不僅能使母板有足夠的空間放置其它封裝模組或增加電池容量，且有利於縮減該電子產品之體積，使該電子產品符合輕薄短小之發展潮流。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧第一承載結構
20a‧‧‧第一表面
20b‧‧‧第二表面
21,21’‧‧‧第一電子元件
22‧‧‧第二電子元件
23‧‧‧功能電子元件
24‧‧‧第二承載結構
25‧‧‧導電元件
26‧‧‧屏蔽結構
27‧‧‧封裝層
28‧‧‧導電體
29‧‧‧包覆層
9‧‧‧電子裝置
90‧‧‧銲錫凸塊
D‧‧‧距離

Claims (21)

  1. 一種電子封裝件，係包括：一第一承載結構，係具有相對之第一表面與第二表面；至少一第一電子元件，係配置於該第一承載結構之第一表面上且電性連接該第一承載結構；複數導電體，係設於該第一承載結構之第二表面上且電性連接該第一承載結構；一第二承載結構，係藉由至少一導電元件堆疊於該第一承載結構之第一表面上，且令該導電元件電性連接該第一承載結構與第二承載結構；至少一功能電子元件，係配置於該第二承載結構上且電性連接該第二承載結構；以及一封裝層，係形成於該第一承載結構與該第二承載結構之間以包覆該第一電子元件、功能電子元件與導電元件。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該第一承載結構之第二表面上設有至少一電性連接該第一承載結構之第二電子元件。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該第一承載結構之第二表面上設有一包覆該複數導電體之包覆層。
  4. 如申請專利範圍第3項所述之電子封裝件，其中，該導電體之部分表面外露於該包覆層。
  5. 如申請專利範圍第3項所述之電子封裝件，其中，該第一承載結構之第二表面上設有至少一電性連接該第一承載結構之第二電子元 件，且該包覆層包覆該第二電子元件。
  6. 如申請專利範圍第5項所述之電子封裝件，其中，該第二電子元件之部分表面外露於該包覆層。
  7. 如申請專利範圍第1項所述之電子封裝件，其中，該功能電子元件與該第一電子元件之配置係相疊合。
  8. 如申請專利範圍第1項所述之電子封裝件，復包括形成於該第一承載結構或該第二承載結構上的屏蔽結構，且令該封裝層包覆該屏蔽結構。
  9. 一種電子封裝件之製法，係包括：提供一具有相對之第一表面與第二表面之第一承載結構，其中，該第一表面上配置有至少一電性連接該第一承載結構之第一電子元件，且該第二表面上配置有複數電性連接該第一承載結構之導電體；將一配置有功能電子元件之第二承載結構藉由至少一導電元件堆疊於該第一承載結構之第一表面上，且令該導電元件電性連接該第一承載結構與第二承載結構，其中，該功能電子元件電性連接該第二承載結構；以及形成封裝層於該第一承載結構與該第二承載結構之間，以令該封裝層包覆該第一電子元件、功能電子元件與導電元件。
  10. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該導電元件係先設於該第二承載結構上，再將該導電元件結合至該第一承載結構上。
  11. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該導電元件係先設於該第一承載結構之第一表面上，再將該第二承載結構 結合至該導電元件上。
  12. 一種電子封裝件之製法，係包括：提供一具有相對之第一表面與第二表面之第一承載結構與一配置有功能電子元件之第二承載結構，其中，該第一表面上配置有至少一電性連接該第一承載結構之第一電子元件，且該第二表面上配置有複數電性連接該第一承載結構之導電體；形成至少一導電元件於該第一承載結構之第一表面或該第二承載結構上，且形成封裝層於該第一承載結構之第一表面或該第二承載結構上；以及藉由該導電元件堆疊該第一承載結構與該第二承載結構，使該封裝層位於該第一承載結構與該第二承載結構之間，且令該封裝層包覆該第一電子元件、功能電子元件與導電元件。
  13. 如申請專利範圍第12項所述之電子封裝件之製法，其中，於堆疊該第一承載結構與該第二承載結構前，該導電元件係設於該第一承載結構與該第二承載結構之其中一者，且該封裝層形成於該第一承載結構與該第二承載結構之另一者。
  14. 如申請專利範圍第12項所述之電子封裝件之製法，其中，於堆疊該第一承載結構與該第二承載結構前，該導電元件係設於該第一承載結構與該第二承載結構之其中一者，且該封裝層係包覆該導電元件。
  15. 如申請專利範圍第9或12項所述之電子封裝件之製法，其中，該第一承載結構之第二表面上設有至少一電性連接該第一承載結構之第二電子元件。
  16. 如申請專利範圍第9或12項所述之電子封裝件之製法，其中，該第一承載結構之第二表面上設有一包覆該複數導電體之包覆層。
  17. 如申請專利範圍第16項所述之電子封裝件之製法，其中，該導電體之部分表面外露於該包覆層。
  18. 如申請專利範圍第16項所述之電子封裝件之製法，其中，該第一承載結構之第二表面上設有至少一電性連接該第一承載結構之第二電子元件，且該包覆層包覆該第二電子元件。
  19. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該第二電子元件之部分表面外露於該包覆層。
  20. 如申請專利範圍第9或12項所述之電子封裝件之製法，其中，該功能電子元件與該第一電子元件之配置係相疊合。
  21. 如申請專利範圍第9或12項所述之電子封裝件之製法，復包括配置屏蔽結構於該第一承載結構或該第二承載結構上，且令該封裝層包覆該屏蔽結構。
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