TWI738525B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TWI738525B
TWI738525B TW109133123A TW109133123A TWI738525B TW I738525 B TWI738525 B TW I738525B TW 109133123 A TW109133123 A TW 109133123A TW 109133123 A TW109133123 A TW 109133123A TW I738525 B TWI738525 B TW I738525B
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Taiwan
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electronic component
electronic
conductive
active surface
component
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TW109133123A
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English (en)
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TW202213691A (zh
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張正楷
林長甫
江東昇
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矽品精密工業股份有限公司
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Priority to TW109133123A priority Critical patent/TWI738525B/zh
Priority to CN202011068946.3A priority patent/CN114256218A/zh
Priority to US17/108,399 priority patent/US11398429B2/en
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Publication of TWI738525B publication Critical patent/TWI738525B/zh
Publication of TW202213691A publication Critical patent/TW202213691A/zh

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Abstract

一種電子封裝件，係將第二電子元件及第三電子元件設於作為承載結構之第一電子元件上，因而無需配合習知封裝基板之佈線尺寸，故該第一電子元件能設計成尺寸較小之系統單晶片，以提高製程良率。

Description

電子封裝件及其製法
本發明係有關一種半導體晶片封裝技術，尤指一種能提高良率的電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，包含有例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組，或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知3D晶片堆疊之封裝結構1之剖面示意圖。如第1圖所示，該封裝結構1包括一矽中介板(Through Silicon interposer，簡稱TSI)1a，其具有一矽板體10及複數形成於其中之導電矽穿孔(Through-silicon via，簡稱TSV)101，且該矽板體10之表面上形成有一電性連接該導電矽穿孔101之線路重佈結構(Redistribution layer，簡稱RDL)。具體地，該線路重佈結構係包含一介電層11及一形成於該介電層11上之線路層12，且該線路層12電性連接該導電矽穿 孔101，並形成一絕緣保護層13於該介電層11與該線路層12上，且該絕緣保護層13外露部分該線路層12，以結合複數如銲錫凸塊之第一導電元件14。
再者，可先形成另一絕緣保護層15於該矽板體10上，且該絕緣保護層15外露該些導電矽穿孔101之端面，以結合複數第二導電元件16於該些導電矽穿孔101之端面上，且該第二導電元件16電性連接該導電矽穿孔101，其中，該第二導電元件16係含有銲錫材料或銅凸塊，且可選擇性於該導電矽穿孔101之端面上形成供接置該第二導電元件16之凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)160。
又，該封裝結構1復包括一封裝基板19，供該矽中介板1a藉由該些第二導電元件16設於其上，使該封裝基板19電性連接該些導電矽穿孔101，且以底膠191包覆該些第二導電元件16。
另外，該封裝結構1復包括複數半導體晶片17，其設於該些第一導電元件14上，使該半導體晶片17電性連接該線路層12，其中，該半導體晶片17係以覆晶方式結合該些第一導電元件14，且以底膠171包覆該些第一導電元件14，並形成封裝材18於該封裝基板19上，以令該封裝材18包覆該半導體晶片17與該矽中介板1a。
於後續應用中，該封裝結構1可形成複數銲球192於該封裝基板19之下側，以接置於一如電路板之電子裝置(圖略)上。
惟，現今終端產品之電性功能越加發達，故接置於該矽中介板1a上之電子元件(如半導體晶片17)越來越多，使該矽中介板1a的結合面積亦會越來越大，因而該導電矽穿孔101之佈設數量亦會增多，然而，於製程上不易製作大量導電矽穿孔101，造成該封裝結構1之良率下降。
再者，若於該封裝基板19上配置半導體元件，如系統單晶片(System on Chip)，以取代該矽中介板1a，則該半導體元件需配合該封裝基板19之佈線尺寸而設計成大尺寸之系統單晶片，因而需採用大於一倍的比例光罩(1X reticle)製作，造成晶圓良率(如20~30%)降低，且基於供電穩定需求，於該封裝基板19上需配置數量更多的被動元件(如可變電阻)，導致該封裝基板19之面積需增大，因而難以符合微小化之需求。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題
鑑於上述習知技術之種種缺失，本發明提供一種電子封裝件，係包括：第一電子元件，係具有作用面及設於該作用面上之電極墊；第二電子元件，係設於該第一電子元件之作用面上且具有相對之第一側與第二側及複數連通該第一側與第二側之導電穿孔，以令該第二電子元件以其第一側接合該作用面，並使該複數導電穿孔電性連接該電極墊；以及第三電子元件，係設於該第一電子元件之作用面上且電性連接該電極墊。
本發明亦提供一種電子封裝件之製法，係包括：提供一第一電子元件，其具有作用面及設於該作用面上之電極墊；設置第二電子元件於該第一電子元件之作用面上，其中，該第二電子元件係具有相對之第一側與第二側及複數連通該第一側與第二側之導電穿孔，以令該第二電子元件以其第一側接合該作用面，並使該複數導電穿孔電性連接該電極墊；以及設置第三電子元件於該第一電子元件之作用面上，且令該第三電子元件電性連接該電極墊。
前述之電子封裝件及其製法中，該第一電子元件係藉由導電體接合該第二電子元件與第三電子元件。
前述之電子封裝件及其製法中，該第一電子元件之作用面上係配置複數相互堆疊之該第三電子元件。
前述之電子封裝件及其製法中，該第三電子元件之內部係形成有複數導電穿孔。
前述之電子封裝件及其製法中，該第一電子元件係為主動元件。
前述之電子封裝件及其製法中，該第二電子元件及/或第三電子元件係為被動元件。
前述之電子封裝件及其製法中，復包括形成線路結構於該第二電子元件之第二側上。例如，該線路結構復形成於該第三電子元件上。進一步，復包括形成導電元件於該線路結構上。
前述之電子封裝件及其製法中，復包括形成封裝層於該作用面上以包覆該第二電子元件與第三電子元件。
由上可知，本發明之電子封裝件及其製法中，主要藉由將該第一電子元件作為承載結構，其上係配置細線路及細間距之半導體材之被動元件(如第二電子元件或第三電子元件)，因而無需配合習知封裝基板之佈線尺寸，故該第一電子元件能設計成尺寸較小之系統單晶片，以提高製程良率。
再者，藉由該第一電子元件之導電體之設計，以於接合該些半導體材之被動元件後，不僅可提高供電穩定性，且能提供高功率(high power)，甚至於大電流(high current)下，能產生較佳之銅遷移(Cu migration)。
又，於該第一電子元件21上可依需求配置所需的被動元件，使該導電穿孔之佈設數量可依需求設計，且單一被動元件之導電穿孔之數量可大幅減少，以易於製程上製作該導電穿孔，故有利於提高該電子封裝件之良率。
另外，將該第一電子元件作為承載結構，以於其上堆疊所需之半導體材之被動元件，因而無需使用習知封裝基板，故相較於習知技術，本發明之電子封裝件2有利於微小化及薄化之設計需求。
1:封裝結構
1a:矽中介板
10:矽板體
101:導電矽穿孔
11:介電層
12:線路層
13,15:絕緣保護層
14:第一導電元件
16:第二導電元件
160:凸塊底下金屬層
17:半導體晶片
171,191,292:底膠
18:封裝材
19:封裝基板
192:銲球
2,3:電子封裝件
20:支撐板
21:第一電子元件
21a:作用面
21b:非作用面
210:電極墊
211:導電體
22:第二電子元件
22a:第一側
22b:第二側
220,230:導電穿孔
23,33:電子組件
23a,23b,23c,33a,33b:第三電子元件
231:導電材
24:包覆層
26,36:線路結構
260:絕緣層
261:線路重佈層
27:導電元件
35:封裝層
35a:第一表面
35b:第二表面
H:高度
H1,H2:高度總和
P1,P2:高度位置
S:容置空間
圖1係為習知封裝結構之剖視示意圖。
圖2A至圖2D本發明之電子封裝件之製法之第一實施例的剖面示意圖。
圖3A至圖3D本發明之電子封裝件之製法之第二實施例的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之 明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2D係為本發明之電子封裝件2之製法之第一實施例的剖面示意圖。
如圖2A所示，提供一設於一支撐板20上之第一電子元件21，以令該第一電子元件21作為該電子封裝件2之承載結構。
於本實施例中，該第一電子元件21係為半導體材之主動元件，如單晶片系統(System on a Chip，簡稱SoC)，其作用面21a具有複數電極墊210，並於該些電極墊210上形成複數導電體211。例如，該些導電體211係為凸塊狀，其包含銲錫材料或銅之金屬柱或其它適當構造，或如包覆有絕緣塊之金屬塊體，或具有核心銅球(Cu core ball)之銲球等，並無特別限制。
再者，該第一電子元件21之作用面21a上可依需求形成一包覆該些導電體211之絕緣材(圖略)，其為非導電性薄膜(Non-conductive Film，簡稱NCF)，如異方性導電膠(Anisotropic conductive past，簡稱ACP)、異方性導電膠膜(Anisotropic Conductive Film，簡稱ACF)或其它構造等。
又，該支撐板20係例如為半導體材質(如矽或玻璃)之圓形板體，其尺寸可依需求選擇晶圓型基板(Wafer form substrate)或一般整版面型基板(Panel form substrate)，且該支撐板20上可依需求以塗佈方式依序形成有一離型層(圖略)與一黏著層(圖略)，以供該第一電子元件21以其相對該作用面21a之非作用面21b設於該黏著層上。
如圖2B所示，設置至少一第二電子元件22於該第一電子元件21之作用面21a上，且該第二電子元件22係具有相對之第一側22a與第二側22b，以令該第二電子元件22以其第一側22a藉由該些導電體211電性連接該第一電子元件 21，且於該第二電子元件22之第二側22b係形成有一電性連接該第二電子元件22之線路結構26。
於本實施例中，該第二電子元件22係為半導體材之被動元件，如可變電阻(Variable Resistor，簡稱VR)，其內配置有至少一連通該第一側22a與第二側22b之導電穿孔220，如導電矽穿孔(Through-silicon via，簡稱TSV)，以電性連接該線路結構26。應可理解地，有關該導電穿孔220之態樣繁多，如端處具有墊部，並無特別限制。
再者，該線路結構26係具有至少一絕緣層260及設於該絕緣層260中之線路重佈層(Redistribution layer，簡稱RDL)261，且最外層之絕緣層260可作為防銲層，以令最外層之線路重佈層261外露於該防銲層。或者，該線路結構26亦可僅包括單一絕緣層260及單一線路重佈層261。例如，形成該線路重佈層261之材質係為銅，且形成該絕緣層260之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材。
又，該線路結構26係以其絕緣層260接觸該第二電子元件22之第二側22b，並以其線路重佈層261電性連接該第二電子元件22之導電穿孔220。
另外，於該第一電子元件21之作用面21a上係間隔配置複數該第二電子元件22，以於該些第二電子元件22之間形成至少一容置空間S。
如圖2C所示，設置至少一第三電子元件23a於該容置空間S中之第一電子元件21之作用面21a上，以令該第三電子元件23a藉由該些導電體211電性連接該第一電子元件21。
於本實施例中，該第三電子元件23a係為半導體材之被動元件，如積體被動元件(Integrated Passive Device，簡稱IPD)。例如，可依需求電性堆疊複數個第三電子元件23a,23b,23c，以構成電子組件23，其中，該電子組件23相對 該作用面21a之高度H1可依需求調整，如高於(亦可低於或等於)該第二電子元件22與該線路結構26相對該作用面21a之高度總和H2。
再者，各該第三電子元件23a,23b,23c內部可配置有至少一貫穿之導電穿孔230，如導電矽穿孔(TSV)，以電性連接該導電體211及各該第三電子元件23a,23b,23c。例如，各該第三電子元件23a,23b,23c之間可藉由導電材231相互導通，且該導電材231係為凸塊狀，其包含銲錫材料或銅之金屬柱或其它適當構造，或如包覆有絕緣塊之金屬塊體，或具有核心銅球(Cu core ball)之銲球等，並無特別限制。
另外，可依需求形成一如底膠之包覆層24於該第一電子元件21之作用面21a與該第二電子元件22之第一側22a之間及/或與該第三電子元件23a之間。
如圖2D所示，移除該支撐板20，且形成複數導電元件27於該線路結構26上，以令該些導電元件27電性連接該線路重佈層261，供該電子封裝件2藉由該些導電元件27外接如電路板之電子裝置(圖略)。
於本實施例中，該導電元件27係為凸塊或球體，其包含銲錫材料或銅之金屬柱或其它適當構造，或如包覆有絕緣塊之金屬塊體，或具有核心銅球(Cu core ball)之銲球等，並無特別限制。
再者，該導電元件27相對該第一電子元件21之作用面21a之高度位置P2係高於該電子組件23相對該第一電子元件21之作用面21a之高度位置P1，以利於該些導電元件27外接電子裝置。
因此，本發明之製法中，將該第一電子元件21作為承載結構，其上係配置細線路及細間距之半導體材之被動元件(如第二電子元件22或第三電子元件23a,23b,23c)，因而無需配合習知封裝基板之佈線尺寸，故該第一電子元件21能設計成尺寸較小之系統單晶片(System on Chip)，以提高製程良率。
再者，藉由該第一電子元件21之導電體211之設計，以於接合該些半導體材之被動元件(如第二電子元件22或第三電子元件23a,23b,23c)後，不僅可提高供電穩定性，且能提供高功率(high power)，甚至於大電流(high current)下，能產生較佳之銅遷移(Cu migration)。
又，於該第一電子元件21上可依需求配置所需的被動元件(如第二電子元件22或第三電子元件23a,23b,23c)，使該導電穿孔220,230之佈設數量可依需求設計，且單一被動元件之導電穿孔220,230之數量可大幅減少，以易於製程上製作該導電穿孔220,230，故有利於提高該電子封裝件2之良率。
另外，將該第一電子元件21作為承載結構，以於其上堆疊所需之半導體材之被動元件(如第二電子元件22或第三電子元件23a,23b,23c)，因而無需使用習知封裝基板，故相較於習知技術，本發明之電子封裝件2有利於微小化及薄化之設計。
圖3A至圖3D係為本發明之電子封裝件3之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於線路結構之製程步驟，其它製程大致相同，故以下不再贅述相同處。
如圖3A所示，係接續圖2A所示之製程，設置至少一第二電子元件22與複數第三電子元件33a,33b於該第一電子元件21之作用面21a上。
於本實施例中，該第二電子元件22之第二側22b上未形成有線路結構，且該複數第三電子元件33a,33b之型式係為不具有導電穿孔230之半導體材之被動元件。
再者，電子組件33(包含兩個第三電子元件23a,23b)相對該作用面21a之高度H係等於(或低於)該第二電子元件22相對該作用面21a之高度H。
如圖3B所示，形成一封裝層35於該第一電子元件21上，以令該封裝層35包覆該第二電子元件22與該電子組件33，其中，該封裝層35係具有相對之 第一表面35a與第二表面35b，且其以第一表面35a結合該作用面21a。接著，藉由整平製程，使該封裝層35之第二表面35b齊平該第二電子元件22之第二側22b(甚至齊平該電子組件33之上表面)，令該第二電子元件22之第二側22b(甚至該電子組件33)外露於該封裝層35之第二表面35b。
於本實施例中，該封裝層35係為絕緣材，如環氧樹脂之封裝膠體，其可用壓合(lamination)或模壓(molding)之方式形成於該第一電子元件21上。
再者，該整平製程係藉由研磨方式，移除該封裝層35之部分材質，甚至移除該第二電子元件22之第二側22b(或該電子組件33)之部分材質。
如圖3C所示，形成一線路結構36於該封裝層35之第二表面35b上，且令該線路結構36電性連接該第二電子元件22之導電穿孔220(或該電子組件33)。
於本實施例中，該線路結構36復形成於該第三電子元件33a,33b上以電性連接該第三電子元件33b。
如圖3D所示，移除該支撐板20，且形成複數導電元件27於該線路結構36上，以令該些導電元件27電性連接該線路結構36，供該電子封裝件3藉由該些導電元件27外接如電路板之電子裝置(圖略)。
因此，本發明之製法中，將該第一電子元件21作為承載結構，其上係配置細線路及細間距之半導體材之被動元件(如第二電子元件22或第三電子元件33a,33b)，因而無需配合習知封裝基板之佈線尺寸，故該第一電子元件21能設計成尺寸較小之系統單晶片(System on Chip)，以提高製程良率。
再者，藉由該第一電子元件21之導電體211之設計，以於接合該些半導體材之被動元件(如第二電子元件22或第三電子元件33a,33b)後，不僅可提高供電穩定性，且能提供高功率(high power)，甚至於大電流(high current)下，能產生較佳之銅遷移(Cu migration)。
又，於該第一電子元件21上可依需求配置所需的被動元件(如第二電子元件22或第三電子元件33a,33b)，使該導電穿孔220之佈設數量可依需求設計，且單一被動元件之導電穿孔220之數量可大幅減少，以易於製程上製作該導電穿孔220，故有利於提高該電子封裝件3之良率。
另外，將該第一電子元件21作為承載結構，以於其上堆疊所需之半導體材之被動元件(如第二電子元件22或第三電子元件33a,33b)，因而無需使用習知封裝基板，故相較於習知技術，本發明之電子封裝件3有利於微小化及薄化之設計。
本發明復提供一種電子封裝件2,3，係包括：第一電子元件21、第二電子元件22以及第三電子元件23a,23b,23c,33a,33b。
所述之第一電子元件21係具有作用面21a及設於該作用面21a上之電極墊210。
所述之第二電子元件22係設於該第一電子元件21之作用面21a上且具有相對之第一側22a與第二側22b及複數連通該第一側22a與第二側22b之導電穿孔220，以令該第二電子元件22以其第一側22a接合該作用面21a，使該複數導電穿孔220電性連接該電極墊210。
所述之第三電子元件23a,23b,23c,33a,33b係設於該第一電子元件21之作用面21a上且電性連接該電極墊210。
於一實施例中，該第一電子元件21係藉由導電體211接合該第二電子元件22與第三電子元件23a,23b,23c,33a,33b。
於一實施例中，該第一電子元件21之作用面21a上係配置複數相互堆疊之該第三電子元件23a,23b,23c,33a,33b。
於一實施例中，該第三電子元件23a,23b,23c之內部係形成有複數導電穿孔230。
於一實施例中，該第一電子元件21係為主動元件。
於一實施例中，該第二電子元件22及/或第三電子元件23a,23b,23c,33a,33b係為被動元件。
於一實施例中，所述之電子封裝件2,3復包括一形成於該第二電子元件22之第二側22b上的線路結構26,36。例如，該線路結構36復形成於該第三電子元件33a,33b上。進一步，所述之電子封裝件2,3復包括複數形成於該線路結構26,36上之導電元件27。
於一實施例中，所述之電子封裝件3復包括形成於該作用面21a上以包覆該第二電子元件22與第三電子元件33a,33b之封裝層35。
綜上所述，本發明之電子封裝件及其製法，係藉由將該第一電子元件作為承載結構，其上係配置細線路及細間距之半導體材之被動元件，因而無需配合習知封裝基板之佈線尺寸，故該第一電子元件能設計成尺寸較小之系統單晶片，以提高製程良率。
再者，藉由該第一電子元件之導電體之設計，以於接合該些半導體材之被動元件後，不僅可提高供電穩定性，且能提供高功率，甚至於大電流下，能產生較佳之銅遷移。
又，於該第一電子元件上可依需求配置所需的被動元件，使該導電穿孔之佈設數量可依需求設計，且單一被動元件之導電穿孔之數量能大幅減少，以易於製程上製作該導電穿孔，故有利於提高該電子封裝件之良率。
另外，將該第一電子元件作為承載結構，以於其上堆疊所需之半導體材之被動元件，因而無需使用習知封裝基板，故本發明之電子封裝件有利於微小化及薄化之設計。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
21:第一電子元件
21a:作用面
211:導電體
22:第二電子元件
22a:第一側
22b:第二側
220,230:導電穿孔
23a,23b,23c:第三電子元件
26:線路結構
27:導電元件
P1,P2:高度位置

Claims (16)

  1. 一種電子封裝件，係包括：第一電子元件，係具有作用面及設於該作用面上之電極墊；第二電子元件，係設於該第一電子元件之作用面上且具有相對之第一側與第二側及複數連通該第一側與第二側之導電穿孔，以令該第二電子元件以其第一側接合該作用面，並使該複數導電穿孔電性連接該電極墊；線路結構，係形成於該第二電子元件之第二側上；以及複數第三電子元件，係相互堆疊設於該第一電子元件之作用面上且電性連接該電極墊。
  2. 如請求項1所述之電子封裝件，其中，該第一電子元件係藉由導電體接合該第二電子元件與第三電子元件。
  3. 如請求項1所述之電子封裝件，其中，該第三電子元件之內部形成有複數導電穿孔。
  4. 如請求項1所述之電子封裝件，其中，該第一電子元件係為主動元件。
  5. 如請求項1所述之電子封裝件，其中，該第二電子元件及/或第三電子元件係為被動元件。
  6. 如請求項1所述之電子封裝件，其中，該線路結構復形成於該第三電子元件上。
  7. 如請求項1所述之電子封裝件，復包括形成於該線路結構上之導電元件。
  8. 如請求項1所述之電子封裝件，復包括形成於該作用面上以包覆該第二電子元件與第三電子元件之封裝層。
  9. 一種電子封裝件之製法，係包括：提供一第一電子元件，其具有作用面及設於該作用面上之電極墊；設置第二電子元件於該第一電子元件之作用面上，其中，該第二電子元件係具有相對之第一側與第二側及複數連通該第一側與第二側之導電穿孔，以令該第二電子元件以其第一側接合該作用面，並使該複數導電穿孔電性連接該電極墊；形成線路結構於該第二電子元件之第二側上；以及設置複數相互堆疊之第三電子元件於該第一電子元件之作用面上，且令該第三電子元件電性連接該電極墊。
  10. 如請求項9所述之電子封裝件之製法，其中，該第一電子元件係藉由導電體接合該第二電子元件與第三電子元件。
  11. 如請求項9所述之電子封裝件之製法，其中，該第三電子元件之內部係形成有複數導電穿孔。
  12. 如請求項9所述之電子封裝件之製法，其中，該第一電子元件係為主動元件。
  13. 如請求項9所述之電子封裝件之製法，其中，該第二電子元件及/或第三電子元件係為被動元件。
  14. 如請求項9所述之電子封裝件之製法，其中，該線路結構復形成於該第三電子元件上。
  15. 如請求項9所述之電子封裝件之製法，復包括形成導電元件於該線路結構上。
  16. 如請求項9所述之電子封裝件之製法，復包括形成封裝層於該作用面上以包覆該第二電子元件與第三電子元件。
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