TWI620296B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TWI620296B
TWI620296B TW104126500A TW104126500A TWI620296B TW I620296 B TWI620296 B TW I620296B TW 104126500 A TW104126500 A TW 104126500A TW 104126500 A TW104126500 A TW 104126500A TW I620296 B TWI620296 B TW I620296B
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Taiwan
Prior art keywords
circuit structure
electronic
electronic component
layer
package
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TW104126500A
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English (en)
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TW201707174A (zh
Inventor
程呂義
馬光華
陳仕卿
呂長倫
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW104126500A priority Critical patent/TWI620296B/zh
Priority to CN201510534098.3A priority patent/CN106469690B/zh
Priority to US14/982,276 priority patent/US9601403B2/en
Publication of TW201707174A publication Critical patent/TW201707174A/zh
Application granted granted Critical
Publication of TWI620296B publication Critical patent/TWI620296B/zh

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Abstract

一種電子封裝件，係包括：第一線路結構、設於該第一線路結構表面上之第一電子元件、包覆該些第一電子元件之第一封裝層、形成於該第一線路結構表面上並位於該第一封裝層中之第一導電元件、包覆該第一電子元件與該第一導電元件之第一封裝層、以及形成於該第一封裝層上並電性連接該第一導電元件之第二線路結構。藉由直接將高I/O功能之電子元件接置於該線路結構上，因而不需使用一含核心層之封裝基板，故可減少該電子封裝件之厚度。本發明復提供該電子封裝件之製法。

Description

電子封裝件及其製法
本發明係有關一種電子封裝件，尤指一種具輕薄短小化之電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知3D晶片堆疊之半導體封裝件1之剖面示意圖。如第1圖所示，提供一矽中介板(Through Silicon interposer，簡稱TSI)10，該矽中介板10具有相對之置晶側10a與轉接側10b、及連通該置晶側10a與轉接側10b之複數導電矽穿孔(Through-silicon via，簡稱TSV)100，且該轉接側10b上具有複數線路重佈層(Redistribution layer，簡稱RDL)101。將間距較小之半導體晶片19之電 極墊190係藉由複數銲錫凸塊102電性結合至該置晶側10a上，再以底膠192包覆該些銲錫凸塊102，且形成封裝膠體18於該矽中介板10上，以覆蓋該半導體晶片19。於該線路重佈結構101上藉由複數如凸塊之導電元件103電性結合間距較大之封裝基板17之銲墊170，並以底膠172包覆該些導電元件103。
製作該半導體封裝件1時，係先將該半導體晶片19置放於該矽中介板10上，再將該矽中介板10以該些導電元件103接置於該封裝基板17上，之後形成該封裝膠體18。
惟，習知半導體封裝件1之製法中，使用該矽中介板10作為該半導體晶片19與該封裝基板17之間訊號傳遞的介質，因需具備一定深寬比之控制(即該導電矽穿孔100之深寬比為100um/10um)，才能製作出適用的矽中介板10，因而往往需耗費大量製程時間及化學藥劑之成本，進而提高製程難度及製作成本。
再者，該封裝基板17具有含玻纖材料之核心層，致使該封裝基板17厚度相當厚，因而不利於產品之輕薄短小化。
又，當該半導體晶片19具有細線寬線距的高I/O數時，則需加大該矽中介板10之面積，因而相對應之封裝基板17的面積亦需加大，故不利於產品之輕薄短小化。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：第一線路結構，係具有相對之第一表面及第二表面；第一電子元件，係設於該第一線路結構之第一表面上；第一封裝層，係形成於該第一線路結構之第一表面上，以包覆該第一電子元件；第一導電元件，係形成於該第一線路結構之第一表面上並位於該第一封裝層中，且令該第一導電元件外露於該第一封裝層；以及第二線路結構，係形成於該第一封裝層上並電性連接該第一導電元件。
前述之電子封裝件中，該第一封裝層包覆該第一導電元件。
前述之電子封裝件中，復包括第二電子元件，係設於該第一封裝層上並電性連接該第二線路結構。又包括形成於該第一封裝層上之第二封裝層，其包覆該第二電子元件。
前述之電子封裝件中，該第一封裝層形成有開口，以令部分該第一線路結構之第一表面外露於該開口，且於外露出該開口中之第一線路結構上設有第三電子元件。例如，該第三電子元件係電性連接該第二線路結構或該第二電子元件。
前述之電子封裝件中，該第一封裝層形成有開口，以令部分該第一線路結構之第一表面外露於該開口，且該第一導電元件係容置於該開口中並連結至該第二線路結構。復包括形成於該第一封裝層上與該開口中之第二封裝層， 以包覆該第二電子元件與該第一導電元件。又，該第二封裝層形成有至少一開孔，以令該第二電子元件之部分表面外露於該開孔，俾供結合第四電子元件於該第二電子元件上。
本發明復提供一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之第一線路結構；形成第一導電元件於該第一線路結構之第一表面上，且設置第一電子元件於該第一線路結構之第一表面上；形成第一封裝層於該第一線路結構之第一表面上，以包覆該第一電子元件與該第一導電元件，且令該第一導電元件外露於該第一封裝層；形成第二線路結構於該第一封裝層上，且該第二線路結構電性連接該第一導電元件；以及設置第二電子元件於該第一封裝層上，且該第二電子元件電性連接該第二線路結構。
前述之製法中，復包括形成第二封裝層於該第一封裝層上，以包覆該第二電子元件。
本發明亦提供一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之第一線路結構；設置第一電子元件於該第一線路結構之第一表面上；形成第一封裝層於該第一線路結構之第一表面上，以包覆該第一電子元件，且該第一封裝層形成有至少一開口，以令部分該第一線路結構之第一表面外露於該開口；形成第二線路結構於該第一封裝層上；設置第二電子元件於該第一封裝層上，且該第二電子元件電性連接該第二線路結構；以及形 成複數第一導電元件於該第二線路結構上與外露出該開口中之第一線路結構上。
前述之製法中，該第一封裝層形成有複數該開口，且部分該開口容置有該第一導電元件，而部分該開口中設有第三電子元件。例如，該第三電子元件電性連接該第二電子元件或該第二線路結構。
前述之製法中，復包括形成第二封裝層於該第一封裝層上與該開口中，以包覆該第二電子元件與該些第一導電元件。例如，該第二封裝層形成有至少一開孔，以令該第二電子元件之部分表面外露於該開孔，俾供結合第四電子元件於該第二電子元件上。
另外，前述之電子封裝件及兩種製法中，復包括形成複數第二導電元件於該第一線路結構之第二表面上。
由上可知，本發明之電子封裝件及其製法，主要藉由直接將高I/O功能之第一電子元件接置於該第一線路結構上，因而不需使用一含核心層之封裝基板，故可減少該電子封裝件之厚度。
再者，藉由該第一導電元件外露於該第一封裝層，使該第一封裝層上之第二電子元件可電性連接該第一導電元件，故該第一電子元件能電性連通至該第二電子元件，因而能縮小該電子封裝件之面積。
1‧‧‧半導體封裝件
10‧‧‧矽中介板
10a‧‧‧置晶側
10b‧‧‧轉接側
100‧‧‧導電矽穿孔
101,211‧‧‧線路重佈層
102,231‧‧‧銲錫凸塊
103‧‧‧導電元件
17‧‧‧封裝基板
170‧‧‧銲墊
172,192,260‧‧‧底膠
18‧‧‧封裝膠體
19‧‧‧半導體晶片
190‧‧‧電極墊
2,3,3’,3”‧‧‧電子封裝件
20‧‧‧承載件
200‧‧‧結合層
21‧‧‧第一線路結構
21a‧‧‧第一表面
21b‧‧‧第二表面
210‧‧‧介電層
22,22’,32,32’,32”‧‧‧第一導電元件
23,23’‧‧‧第一電子元件
24,24’,34‧‧‧第一封裝層
25‧‧‧第二線路結構
26,36‧‧‧第二電子元件
27,37‧‧‧第二封裝層
28‧‧‧第二導電元件
340,340’‧‧‧開口
33‧‧‧第三電子元件
330,360‧‧‧黏著材
370‧‧‧開孔
39‧‧‧第四電子元件
第1圖係為習知半導體封裝件之剖面示意圖；第2A至2G圖係為本發明之電子封裝件之製法之第一 實施例的剖面示意圖；第3A至3C圖係為本發明之電子封裝件之製法之第二實施例的剖面示意圖；以及第3C’圖係為本發明之電子封裝件之製法之第三實施例的剖面示意圖；其中，第3C”圖係為第3C’圖之另一態樣。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之電子封裝件2之製法之第一實施例的剖面示意圖。
如第2A圖所示，提供一設有第一線路結構21之承載件20。
於本實施例中，該承載件20係為半導體板體，例如矽晶圓(Si wafer)或玻璃，且該承載件20上具有一結合層200，以結合該第一線路結構21。例如，該結合層200係為熱化二氧化矽層(thermal SiO2 layer)、離形層或保護層。於本實施例中，該承載件20係矽晶圓，而該結合層200係為熱化二氧化矽層。
再者，該第一線路結構21係具有相對之第一表面21a與第二表面21b，並以該第二表面21b結合於該結合層200上，且該第一線路結構21係包含至少一介電層210及形成於該介電層210上之線路重佈層211(Redistribution layer，簡稱RDL)。
如第2B圖所示，設置複數第一電子元件23,23’於該第一線路結構21之第一表面21a上，且形成至少一第一導電元件22於該第一線路結構21之第一表面21a上。接著，形成第一封裝層24於該第一線路結構21之第一表面21a上，以包覆該些第一電子元件23,23’與第一導電元件22。
於本實施例中，該第一電子元件23,23’係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
再者，該第一電子元件23,23’係以覆晶方式電性連接該第一線路結構21。具體地，該第一電子元件23藉由複數銲錫凸塊231電性結合至該第一線路結構21之線路重佈層211上，並選擇性地以底膠(圖略)固定於該第一線路結構21之第一表面21a上。或者，該第一電子元件23,23’ 亦可以打線方式電性連接該第一線路結構21之線路重佈層211。
又，該第一導電元件22係以打線製程所形成之銲線，故該第一導電元件22呈現拱形體，即弧線狀。然而，該第一導電元件亦可為導電柱(圖略)。
另外，形成該第一封裝層24之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。
如第2C圖所示，於該第一封裝層24上進行整平製程，即移除該第一封裝層24之部分材質，且同時移除該第一導電元件22之部分材質，使經移除部分材質之第一導電元件22’變成兩條線段，且該該第一導電元件22’之端面係外露於經整平後之該第一封裝層24’之表面。
於本實施例中，係以研磨方式移除該第一封裝層24之部分材質，且該些第一電子元件23,23’未外露於該第一封裝層24’之表面。
如第2D圖所示，形成第二線路結構25於該第一封裝層24’上，且該第二線路結構25接觸該第一導電元件22’。接著，對該第一電子元件23,23’、第一導電元件22’、第一與第二線路結構21,25進行電性測試。
於本實施例中，該第二線路結構25係為線路重佈層(RDL)。
再者，可先接置該些第一電子元件23,23’(晶片及被動元件)後，再進行線路測試，待確認第一與第二線路結 構21,25正常後，再接置良好裸晶粒(Known Good Die，簡稱KGD)，即後述之第二電子元件26，以防止最終封裝件發生良率不佳之問題。
如第2E圖所示，設置複數第二電子元件26於該第二線路結構25上，再形成第二封裝層27於該第一封裝層24’上，以包覆該些第二電子元件26。
於本實施例中，該第二電子元件26係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第二電子元件26係以覆晶方式電性連接該第二線路結構25，並選擇性地以底膠260固定於該第二線路結構25上。當然，該第二電子元件26亦可以打線方式電性連接該第二線路結構25。
再者，該第二封裝層27之材質與該第一封裝層24’之材質係相同或不相同，且形成該第二封裝層27之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。
如第2F圖所示，移除該承載件20及該結合層200，以外露該第一線路結構21之第二表面21b。
如第2G圖所示，形成複數第二導電元件28於該第一線路結構21之第二表面21b上。
於本實施例中，該第二導電元件28係為銲球、金屬凸塊或金屬針等，且結合於該第一線路結構21之線路重佈層211上並電性連接該線路重佈層211。
第3A至3C圖係為本發明之電子封裝件3之製法之第二實施例的剖面示意圖。本實施例與第一實施例之方式大致相同，主要差異在於第一導電元件32,32’,32”的製程，故以下僅詳述相異處，而相同處不再贅述。
如第3A圖所示，接續第2A圖之製程(以下省略該承載件20及該結合層200之說明)，設置複數第一電子元件23於該第一線路結構21之第一表面21a上，再形成第一封裝層34於該第一線路結構21之第一表面21a上，以包覆該些第一電子元件23。接著，於該第一封裝層34上形成複數開口340,340’，以令該第一線路結構21之部分第一表面21a(或部分該線路重佈層211)外露於該些開口340,340’。
於本實施例中，形成該第一封裝層34之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。
如第3B圖所示，形成第二線路結構25於該第一封裝層34上，且設置複數第二電子元件26,36於該第二線路結構25上。
於本實施例中，部分該第二電子元件36藉由黏著材360設於該第一封裝層34上。
再者，於設置該些第二電子元件26,36時，可於部分該開口340’中之第一線路結構21之第一表面21a上藉由黏著材330設置第三電子元件33。具體地，該第三電子元件33係為主動元件、被動元件或其組合者，其中，該主動元 件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
另外，於其它方式中，可先形成第二線路結構25於該第一封裝層34上，再於該第一封裝層34上形成複數開口340,340’。
如第3C圖所示，形成複數第一導電元件32,32’,32”於該第二線路結構25、外露於該開口340中之線路重佈層211、第二電子元件26,36、與第三電子元件33上，且形成複數第二導電元件28於該第一線路結構21之第二表面21b上。
於本實施例中，該第一導電元件32,32’,32”係以打線製程所形成之銲線，故該第一導電元件32,32’,32”呈現拱形體，即弧線狀。
再者，該第二線路結構25藉由該第一導電元件32電性連接該第一線路結構21之線路重佈層211，且部分該第二電子元件26係以覆晶方式電性連接該第二線路結構25，而部分該第二電子元件36係以打線方式(即藉由該第一導電元件32’)相互電性連接或電性連接至該第二線路結構25。
又，該第三電子元件33係以打線方式(即藉由該第一導電元件32”)分別電性連接該第二線路結構25與部分該第二電子元件36。
第3C’圖係為本發明之電子封裝件3’之製法之第三實施例的剖面示意圖。本實施例與第二實施例之方式大致相 同，主要差異在於增加第二封裝層，故以下僅詳述相異處，而相同處不再贅述。
如第3C’圖所示，形成一第二封裝層37於該第一封裝層34上與該些開口340,340’中，以包覆該些第二電子元件26,36、第三電子元件33與該些第一導電元件32,32’,32”。
於本實施例中，該第二封裝層37之材質與該第一封裝層34之材質係相同或不相同，且形成該第二封裝層37之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。
再者，如第3C”圖所示，亦可於該第二封裝層37上形成有至少一開孔370，以令該第二電子元件36之部分表面外露於該開孔370，俾供結合第四電子元件39於該第二電子元件36上。具體地，該第四電子元件39係為感測晶片(sensor chip)，但不以此為限。
本發明之製法中，藉由直接將高I/O功能之電子元件(第一電子元件23,23’與第三電子元件33)接置於該第一線路結構21上，因而不需使用一含核心層之封裝基板，故可減少該電子封裝件2,3,3’,3”之厚度。
再者，藉由直接將高I/O功能之電子元件接置於該第一線路結構21上，使各電子元件(第一電子元件23,23’與第三電子元件33)間之傳導線距(Pitch)縮小。
又，藉由該第一導電元件22’,32外露於該第一封裝層24’,34，且利用打線技術(該第一導電元件22’,32,32’,32”)，使各層堆疊之電子元件(第一電子元件 23,23’、第二電子元件26,36及第三電子元件33)得以電性連結，即該第一電子元件23,23’及第三電子元件33能電性連通至該第二電子元件26,36，因而能縮小該電子封裝件2,3,3’,3”之體積，且能降低製作成本。
本發明提供一種電子封裝件2,3,3’,3”，係包括：第一線路結構21、第一電子元件23,23’、第一封裝層24’,34、第一導電元件22’,32、第二線路結構25、以及第二電子元件26,36。
所述之第一線路結構21係具有相對之第一表面21a及第二表面21b。
所述之第一電子元件23,23’係設於該第一線路結構21之第一表面21a上。
所述之第一封裝層24’,34係形成於該第一線路結構21之第一表面21a上，以包覆該些第一電子元件23,23’。
所述之第一導電元件22’,32係形成於該第一線路結構21之第一表面21a上並位於該第一封裝層24’,34中，且令該第一導電元件22’,32外露於該第一封裝層24’,34。
所述之第二線路結構25係形成於該第一封裝層24’,34上並電性連接該第一導電元件22’,32。
所述之第二電子元件26,36係設於該第一封裝層24’,34上並電性連接該第二線路結構25。
於一電子封裝件2之實施例中，該第一封裝層24’包覆該第一導電元件22’。
於一實施例中，所述之電子封裝件2復包括形成於該 第一封裝層24’上之第二封裝層27，其包覆該些第二電子元件26。
於一電子封裝件3,3’,3”之實施例中，該第一封裝層34形成有開口340’，以令該第一線路結構21之部分第一表面21a外露於該開口340’，且該開口340’中之第一線路結構21上設有第三電子元件33，使該第三電子元件33電性連接該第二線路結構25或該第二電子元件36。
於一電子封裝件3,3’,3”之實施例中，該第一封裝層34形成有開口340，以令該第一線路結構21之部分第一表面21a外露於該開口340，且該第一導電元件32係容置於該開口340中並連結至該第二線路結構25。再者，該電子封裝件3’,3”復包括形成於該第一封裝層34上與該開口340中之第二封裝層37，以包覆該些第二電子元件26,36與該第一導電元件32。又，該第二封裝層37形成有至少一開孔370，以令該第二電子元件36之部分表面外露於該開孔370，俾供結合第四電子元件39於該第二電子元件36上。
於一實施例中，所述之電子封裝件2,3,3’,3”復包括形成於該第一線路結構21之第二表面21b上的複數第二導電元件28。
綜上所述，本發明之電子封裝件及其製法，係藉由直接將高I/O功能之電子元件接置於該第一線路結構上，因而不需使用一含核心層之封裝基板，故可減少該電子封裝件之厚度。
再者，藉由該第一導電元件外露於該第一封裝層，使 該第一封裝層上之第二電子元件可電性連接該第一導電元件，故該第一電子元件能電性連通至該第二電子元件，因而能縮小該電子封裝件之面積。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (17)

  1. 一種電子封裝件，係包括：第一線路結構，係具有相對之第一表面及第二表面；第一電子元件，係設於該第一線路結構之第一表面上；第一封裝層，係形成於該第一線路結構之第一表面上，以包覆該第一電子元件；第一導電元件，係形成於該第一線路結構之第一表面上並位於該第一封裝層中，且令該第一導電元件外露於該第一封裝層；第二線路結構，係形成於該第一封裝層上並電性連接該第一導電元件；第二電子元件，係設於該第一封裝層上並電性連接該第二線路結構；以及第二封裝層，係形成於該第一封裝層上且包覆該第二電子元件。
  2. 如申請專利範圍第1項所述之電子封裝件，復包括結合於該第二電子元件上之第四電子元件。
  3. 一種電子封裝件，係包括：第一線路結構，係具有相對之第一表面及第二表面；第一電子元件，係設於該第一線路結構之第一表面上；第一封裝層，係形成於該第一線路結構之第一表面上，以包覆該第一電子元件；第一導電元件，係形成於該第一線路結構之第一表面上並位於該第一封裝層中，且令該第一導電元件外露於該第一封裝層；第二線路結構，係形成於該第一封裝層上並電性連接該第一導電元件；以及複數第二導電元件，係形成於該第一線路結構之第二表面上。
  4. 如申請專利範圍第1或3項所述之電子封裝件，其中，該第一封裝層包覆該第一導電元件。
  5. 如申請專利範圍第1或3項所述之電子封裝件，其中，該第一封裝層形成有開口，以令部分該第一線路結構之第一表面外露於該開口，且於外露出該開口中之第一線路結構上設有第三電子元件。
  6. 如申請專利範圍第5項所述之電子封裝件，其中，該第三電子元件係電性連接該第二線路結構。
  7. 如申請專利範圍第1或3項所述之電子封裝件，其中，該第一封裝層形成有開口，以令部分該第一線路結構之第一表面外露於該開口，且該第一導電元件係容置於該開口中並連結至該第二線路結構。
  8. 如申請專利範圍第7項所述之電子封裝件，復包括形成於該開口中之第二封裝層，以包覆該第一導電元件。
  9. 一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之第一線路結構；形成第一導電元件於該第一線路結構之第一表面上，且設置第一電子元件於該第一線路結構之第一表面上；形成第一封裝層於該第一線路結構之第一表面上，以包覆該第一電子元件與該第一導電元件，且令該第一導電元件外露於該第一封裝層；形成第二線路結構於該第一封裝層上，且該第二線路結構電性連接該第一導電元件；以及設置第二電子元件於該第一封裝層上，且該第二電子元件電性連接該第二線路結構。
  10. 如申請專利範圍第9項所述之電子封裝件之製法，復包括形成第二封裝層於該第一封裝層上，以包覆該第二電子元件。
  11. 如申請專利範圍第9項所述之電子封裝件之製法，復包括形成複數第二導電元件於該第一線路結構之第二表面上。
  12. 一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之第一線路結構；設置第一電子元件於該第一線路結構之第一表面上；形成第一封裝層於該第一線路結構之第一表面上，以包覆該第一電子元件，且該第一封裝層形成有至少一開口，以令部分該第一線路結構之第一表面外露於該開口；形成第二線路結構於該第一封裝層上；設置第二電子元件於該第一封裝層上，且該第二電子元件電性連接該第二線路結構；以及形成複數第一導電元件於該第二線路結構上與外露出該開口中之第一線路結構上。
  13. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該第一封裝層形成有複數該開口，且部分該開口容置有該第一導電元件，而部分該開口中設有第三電子元件。
  14. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該第三電子元件電性連接該第二電子元件或該第二線路結構。
  15. 如申請專利範圍第12項所述之電子封裝件之製法，復包括形成第二封裝層於該第一封裝層上與該開口中，以包覆該第二電子元件與該些第一導電元件。
  16. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該第二封裝層形成有至少一開孔，以令該第二電子元件之部分表面外露於該開孔，俾供結合第四電子元件於該第二電子元件上。
  17. 如申請專利範圍第12項所述之電子封裝件之製法，復包括形成複數第二導電元件於該第一線路結構之第二表面上。
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