JP5003260B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP5003260B2 JP5003260B2 JP2007105852A JP2007105852A JP5003260B2 JP 5003260 B2 JP5003260 B2 JP 5003260B2 JP 2007105852 A JP2007105852 A JP 2007105852A JP 2007105852 A JP2007105852 A JP 2007105852A JP 5003260 B2 JP5003260 B2 JP 5003260B2
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- Prior art keywords
- semiconductor device
- semiconductor element
- sealing layer
- metal post
- metal
- Prior art date
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Classifications
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- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/4857—Multilayer substrates
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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- H—ELECTRICITY
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- H01L2224/161—Disposition
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- H01L2224/161—Disposition
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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Description
前記封止層は、補強材を有する有機材料であることが望ましい。
(半導体装置)
図1(a)は、本発明の第1実施形態の半導体装置の構造の例を示す断面図であり、図1(b)は図1(a)の部分拡大図である。
また、半導体装置を積層することなく、図11に示すように、金属ポスト24にヒートシンク32を搭載することで、高放熱性の半導体装置としても構わない。
(半導体装置の製造方法)
図12Aから図12Lは、本発明の第1実施形態にかかる半導体装置の製造法を工程順に示す断面図である。本実施形態の製造方法は、図1に示したような第1実施形態の半導体装置を製造するためのものである。
金属体33は、最終的に金属ポスト24として機能させるため、例えば、銅、アルミニウム、ニッケル、ステンレス鋼、鉄、マグネシウム、および亜鉛からなる群から選択された少なくとも1種の金属もしくはこれらを主成分とする合金が用いられる。特に、電気抵抗値およびコストの観点から、金属体33として銅を選択することが望ましい。本実施形態では、銅が用いられている。
絶縁層21は、例えば感光性または非感光性の有機材料で形成されており、有機材料は、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、BCB(benzocyclobutene)、PBO(polybenzoxazole)、ポリノルボルネン樹脂等や、ガラスクロスやアラミド繊維などで形成された織布や不織布にエポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、BCB(benzocyclobutene)、PBO(polybenzoxazole)、ポリノルボルネン樹脂等を含浸させた材料を用いる。本実施形態では、ガラスクロスを含浸させたエポキシ樹脂が用いられている。
ビアホール34は、絶縁層21が感光性の材料で形成される場合、フォトリソグラフィーにより形成される。絶縁層21が、非感光性の材料、または、感光性の材料でパターン解像度が低い材料で形成される場合、ビアホール34は、レーザー加工法、ドライエッチング法またはブラスト法により形成される。本実施形態では、レーザー加工法が用いられる。
本実施形態では、銅が用いられている。充填方法は、電解めっき、無電解めっき、印刷法、溶融金属吸引法等で行う。
上層配線20としては、例えば、銅、銀、金、ニッケル、アルミニウム、およびパラジウムからなる群から選択された少なくとも1種の金属もしくはこれらを主成分とする合金が用いられる。特に、電気抵抗値およびコストの観点から、上層配線20を銅により形成することが望ましい。本実施形態では、セミアディティブ法を用い、上層配線20には銅が用いられている。
ソルダーレジスト22は、配線基板17の表面回路保護と難燃性を発現するために形成される。その材料は、エポキシ系、アクリル系、ウレタン系、ポリイミド系の有機材料からなり、必要に応じて無機材料や有機材料のフィラーが添加されていても構わない。また、配線基板にソルダーレジスト22を設けなくても構わない。
エッチング方法は、ディップ法またはスプレー法により行う。本実施形態では、アンモニアを主成分とするアルカリ銅エッチング液(メルテックス:エープロセス)を用いて、スプレーエッチング法により行った。
封止層14は、搭載されている半導体素子10と金属ポスト24の上に、真空プレス、真空ラミネートなどで積層される。
また、封止層14で半導体装置40の剛性を高めることができるため、配線基板17を薄くでき、配線基板17として薄型基板を使用することで、低反り、かつ、薄型の半導体装置40を実現することが可能になる。
半導体素子10の搭載箇所だけではなく、半導体素子10が搭載されている配線基板17の面の全面を封止材で覆うことで、半導体装置の剛性を確保すると共に、低反り化を実現することが可能になる。
また、上記半導体装置の製造方法によれば、薄型基板の支持体である金属体を接続端子としているため、新たに電極を形成する必要がなく、従来のパッケージ積層型SiPの構造と比べて半導体装置の低コスト化を実現することが可能になる。
11 ビルドアップ配線基板
12 コア層
13 ビルドアップ層
14 封止層
15 半田ボール
16 アンダーフィル樹脂
17 配線基板
18 下層配線
19 ビア
20 上層配線
21 絶縁層
22 ソルダーレジスト
23 電極
24 金属ポスト
25 接着層
26 ボンディングワイヤ
27 補強剤
28 配線基板17の補強剤
29 埋め込み材
30 半導体素子封止層
31 上パッケージ
32 ヒートシンク
33 金属体
34 ビアホール
35 マスク
36 半導体素子領域開口部
37 金属ポスト領域開口部
38 プリプレグ
39 開口済プリプレグ
40 半導体装置
41 開口部と補強材を持たない封止層
Claims (19)
- 絶縁層と配線層により構成された配線基板の片面に半導体素子が搭載された半導体装置であって、
前記半導体素子が搭載されている前記配線基板の面に設けられた金属ポストと、
前記半導体素子を覆うと共に、前記金属ポストの一部のみが露出するように、前記半導体素子が搭載されている前記配線基板の面に設けられた封止層と、を含み、前記封止層は、補強材を含む有機材料から構成されており、前記封止層中の前記補強材と前記金属ポストは、接していないことを特徴とする半導体装置。 - 前記補強材が、ガラス、アラミド、液晶ポリマー、PTFEのいずれか、もしくは、それらのうちの複数からなることを特徴とする請求項1に記載の半導体装置。
- 前記補強材が、織布であることを特徴とする請求項1に記載の半導体装置。
- 前記補強材が、不織布であることを特徴とする請求項1に記載の半導体装置。
- 前記補強材が、フィルムであることを特徴とする請求項1に記載の半導体装置。
- 前記金属ポストの外周に埋め込み材が設けられていることを特徴とする請求項1から5のいずれか1項に記載の半導体装置。
- 前記封止層は、前記半導体素子を覆う半導体素子封止層を有することを特徴とする請求項1から6のいずれか1項に記載の半導体装置。
- 前記金属ポストの形状において、前記金属ポストの前記配線基板と接する面の面積が、その反対の面の面積よりも大きいことを特徴とする請求項1から7のいずれか1項に記載の半導体装置。
- 前記金属ポストが設けられた面の前記配線基板の配線層の一部が前記絶縁層よりも窪んでいることを特徴とする請求項1から8のいずれか1項に記載の半導体装置。
- 前記半導体素子と前記配線基板との接続が、フリップチップ接続かワイヤーボンディング接続のいずれかであることを特徴とする請求項1から9のいずれか1項に記載の半導体装置。
- 前記半導体素子と前記配線基板との接続が、前記半導体素子の接続端子部分に直接前記配線基板の配線が接続された接続であることを特徴とする請求項1から10のいずれか1項に記載の半導体装置。
- 前記金属ポストは複数あり、前記金属ポストのいずれかは、前記配線層と接続され、他の半導体装置との接続部として使用されることを特徴とする請求項1から11のいずれか1項に記載の半導体装置。
- 前記金属ポストがヒートシンクと接続していることを特徴とする請求項1から12のいずれか1項に記載の半導体装置。
- 金属体上に絶縁層および配線層により構成された配線基板を形成する工程と、
前記金属体の前記配線基板と接する面の反対面に、マスクを形成する工程と、
前記マスクを用いて前記金属体の一部を除去して金属ポストを形成する工程と、
前記金属ポストが形成された前記配線基板上に半導体素子を搭載する工程と、
前記半導体素子と前記金属ポストを、補強材を含む有機材料から構成された封止層で埋め込む工程と、
前記封止層の一部を除去して、前記半導体素子が覆われた状態で前記金属ポストの前記配線基板と接する面の反対面を露出する工程と、を含み、
前記半導体素子と前記金属ポストを前記封止層で埋め込む工程において、前記封止層中の前記補強材と前記金属ポストが、接しないように、前記半導体素子と前記金属ポストを前記封止層で埋め込むことを特徴とする半導体装置の製造方法。 - 前記半導体素子と前記金属ポストを埋め込む工程は、
前記封止層に半導体素子領域開口部と金属ポスト領域開口部を形成する工程と、
前記開口部が形成された前記封止層を、前記半導体素子と前記金属ポストが設けられた配線基板上に積層する工程と、
開口部と補強材を持たない第2封止層を、前記封止層に積層する工程と、を有することを特徴とする請求項14に記載の半導体装置の製造方法。 - 前記半導体素子と前記金属ポストを埋め込む工程は、
前記封止層に半導体素子領域開口部と金属ポスト領域開口部を形成する工程と、
前記開口部が形成された前記封止層を、前記半導体素子と前記金属ポストが設けられた配線基板上に積層する工程と、
埋め込み材を前記封止層に積層する工程と、を有することを特徴とする請求項14に記載の半導体装置の製造方法。 - 前記半導体素子と前記金属ポストを埋め込む工程は、
前記半導体素子を半導体素子封止層で埋め込む工程と、
前記金属ポストを封止層で埋め込む工程と、を有することを特徴とする請求項14から16のいずれか1項に記載の半導体装置の製造方法。 - 前記半導体素子と前記金属ポストを埋め込む工程は、
前記金属ポストを封止層で埋め込む工程と、
前記半導体素子を半導体素子封止層で埋め込む工程と、を有することを特徴とする請求項14から16のいずれか1項に記載の半導体装置の製造方法。 - 前記半導体装置の前記金属ポストを電気的な接続部として半導体装置を積層する工程を有することを特徴とする請求項14から18のいずれか1項に記載の半導体装置の製造方法。
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