CN101286484B - 半导体器件和制造方法 - Google Patents

半导体器件和制造方法 Download PDF

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Publication number
CN101286484B
CN101286484B CN2008100870930A CN200810087093A CN101286484B CN 101286484 B CN101286484 B CN 101286484B CN 2008100870930 A CN2008100870930 A CN 2008100870930A CN 200810087093 A CN200810087093 A CN 200810087093A CN 101286484 B CN101286484 B CN 101286484B
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semiconductor element
sealant
semiconductor device
metal column
circuit board
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CN101286484A (zh
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森健太郎
菊池克
山道新太郎
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Godo Kaisha IP Bridge 1
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NEC Corp
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Abstract

一种半导体器件，其中半导体元件安装在由绝缘层和布线层组成的电路板的一侧上，包括：金属柱，其提供在上面安装了所述半导体元件的所述电路板的一侧上；和密封层，其提供在上面安装了所述半导体元件的所述电路板的一侧上，以便覆盖所述半导体元件以及仅暴露出所述金属柱的一部分。

Description

半导体器件和制造方法
本申请基于2007年4月13日提交的日本专利申请No.2007-105852并要求其优先权，其公开通过参考全部包含在这里。
技术领域
本发明涉及一种用来实现用于更薄且更不易于翘曲的堆叠封装SiP封装的半导体器件，并涉及制造这种半导体器件的方法。
背景技术
作为用来实现具有更高功能性的更小电子设备的技术，SiP(系统级封装)引起了注意。在SiP内部，堆叠封装SiP(PoP，堆叠式封装层叠)提供了对确保产品无缺陷问题的容易解决方案。另外，堆叠封装SiP允许在组合芯片上的高自由度。结果，堆叠封装SiP的订单在增加，尤其是用于携带式电话机的。
然而，堆叠封装SiP有比多个半导体元件堆叠在一个封装中的堆叠半导体元件SiP更高的组件高度的问题。由于仅模铸了安装半导体元件的位置的内插衬底和部分模铸变薄，堆叠封装SiP还有更大封装翘曲和膨胀的问题。
图1是示出堆叠封装SiP中下部封装的典型结构的截面图。该封装使用具有芯层12的组合电路板11作为内插衬底。而且，在该封装中，半导体元件10，这里是芯片，通过接合线26由引线接合到组合电路板11。该封装具有仅半导体元件10的安装位置被密封层14密封的部分模铸结构。
已提出各种技术作为贴附和封装翘曲的高度的对策。
例如，JP-A-2003-133521描述了一种降低组件剖面的技术。更具体地，JP-A-2003-133521描述了一种技术，在该技术中封装不是通过在衬底上安装芯片，而是在衬底中提供开口，在该开口底部上的支撑带上面朝上安装芯片，通过引线结合连接芯片，实现芯片位置的部分模铸，以及最后安装球，来制造的。
可选地，JP-A-2005-45251公开了一种通过在衬底上安装芯片、安装焊球作为外部电极、模铸整个表面、以及然后研磨该焊球和芯片反面的一部分来制造封装的技术。
作为用于封装翘曲的对策，JP-A-2007-42762公开了一种改变形成在下部封装上并且是上部封装连接器的电极的高度以确保翘曲发生时连接可靠性的技术。
尽管在堆叠封装SiP中寻求组件高度的低剖面和封装的减小翘曲，但这两个目的难以在堆叠封装SiP中同时实现。
在JP-A-2003-133521公开的技术中，封装的厚度是通过在衬底中提供开口和在这些开口中安装半导体元件减小的。然而，这种封装采用了仅用于半导体元件的部分模铸结构，结果，难以在未被模铸密封的封装端部抑制翘曲。
在JP-A-2005-45251公开的技术中，通过模铸密封整个表面的构造是通过在衬底上安装半导体元件和焊球以及然后安装整个表面实现的。然而，该半导体元件的反面是通过研磨露出的，尽管可以减小封装的厚度，但难以抑制半导体元件区域中的翘曲。
在JP-A-2007-42762公开的技术中，在堆叠上部和下部封装时由翘曲引起的连接缺陷的问题是通过调节下部封装上的电极的高度解决的。然而，当减小衬底的厚度实现低剖面的组件高度时，通过仅调节电极的高度难以吸收封装的翘曲。因此难以同时实现组件高度的低剖面和减小的翘曲。
发明内容
本发明的示范性目的是提供一种可以同时实现组件高度的低剖面和减小翘曲的半导体器件以及制造这种半导体器件的方法。
根据本发明的示范性方面的半导体器件是这样一种半导体器件，其中半导体元件安装在由绝缘层和布线层组成的电路板的一侧上，且其包括金属柱，提供在其上面安装了半导体元件的电路板的一侧上；和密封层，提供在上面安装了半导体元件的电路板的一侧上，以便覆盖该半导体元件并且仅暴露出部分金属柱。
根据本发明的示范性方面的方法是一种制造半导体器件的方法，其包括在金属体上形成由绝缘层和布线层组成的电路板；在与接触电路板的金属体的表面相对的金属体的表面上形成掩模；利用掩模通过移除金属体的一部分形成金属柱；在其上面形成了金属柱的电路板上安装半导体元件；在密封层中嵌入半导体元件和金属柱；和通过移除密封层的一部分暴露出接触电路板的相对表面的金属体的表面。
参考示出了本发明的实例的附图，由下面的描述，本发明的上述和其它目的、特征和优点将变得显而易见。
附图说明
图1是示出堆叠封装SiP的下部封装的典型结构的示例图；
图2是示出根据本发明第一示范性实施例的半导体器件结构的实例的截面图；
图3是示出根据本发明第一示范性实施例的半导体器件结构的第一修改的截面图；
图4是示出根据本发明第一示范性实施例的半导体器件结构的第二修改的截面图；
图5是示出根据本发明第一示范性实施例的半导体器件结构的第三修改的截面图；
图6是示出根据本发明第二示范性实施例的半导体器件结构的实例的截面图；
图7是示出根据本发明第三示范性实施例的半导体器件结构的实例的截面图；
图8是示出根据本发明第三示范性实施例的半导体器件结构的第一修改的截面图；
图9是示出根据本发明第三示范性实施例的半导体器件结构的第二修改的截面图；
图10是示出根据本发明第三示范性实施例的半导体器件结构的第三修改的截面图；
图11是示出根据本发明第四示范性实施例的半导体器件结构的实例的截面图；
图12是示出根据本发明第四示范性实施例的半导体器件结构的第一修改的截面图；
图13A是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图13B是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图13C是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图13D是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图13E是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图13F是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图13G是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图13H是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图13I是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图13J是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图13K是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图13L是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图14是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图15是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图16A是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图16B是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的上平面图；
图16C是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图16D是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的上平面图；
图16E是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图16F是示出用于说明制造根据本发明第一示范性实施例的半导体器件的方法的半导体器件结构的实例的上平面图；
图17是示出用于说明制造根据本发明第二示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图18A是示出用于说明制造根据本发明第三示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图18B是示出用于说明制造根据本发明第三示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图18C是示出用于说明制造根据本发明第三示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图18D是示出用于说明制造根据本发明第三示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；
图19A是示出用于说明制造根据本发明第三示范性实施例的半导体器件的方法的第一修改的半导体器件结构的实例的截面图；
图19B是示出用于说明制造根据本发明第三示范性实施例的半导体器件的方法的第一修改的半导体器件结构的实例的截面图；
图19C是示出用于说明制造根据本发明第三示范性实施例的半导体器件的方法的第一修改的半导体器件结构的实例的截面图；
图19D是示出用于说明制造根据本发明第三示范性实施例的半导体器件的方法的第一修改的半导体器件结构的实例的截面图；
图20A是示出用于说明制造根据本发明第四示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图；和
图20B是示出用于说明制造根据本发明第四示范性实施例的半导体器件的方法的半导体器件结构的实例的截面图。
具体实施方式
接下来参考附图具体地描述本发明的示范性实施例。
半导体器件
图2是示出根据本发明第一示范性实施例的半导体器件结构的实例的截面图和该半导体器件的部分放大图。
图2中所示的半导体器件40包括电路板17。在电路板17中，下层布线18借助通路19电连接至上层布线20。在电路板17的下层布线18侧上提供多个金属柱24、半导体元件10和密封层14。半导体元件10由密封层14覆盖。密封层14还提供在多个金属柱24之间。暴露出金属柱24的表面，该表面与接触电路板17的表面相反(仅金属柱24的一部分)。密封层14由包括加固材料27的有机材料形成。
例如，金属柱24由铜、镍、铝、金、银、钯、铂、铁、不锈钢、锌、镁、钛、42-合金、铬、钒、铑、钼和钴中的任一种、或多种这些元素的材料组成。
根据低成本和容易加工的目的，铜尤其适合作为金属柱24。在第一示范性实施例中，使用铜作为金属柱24。
关于第一示范性实施例中金属柱24的形状、金属柱24的表面的形状，接触电路板17的表面的面积比相对的表面的面积大，因此金属柱24和电路板17之间的接触度高。结果，甚至在金属柱24上以液体或膜形式沉积密封层14时可以容易加工密封层14。
在第一示范性实施例中，金属柱24的形状不限于图2中所示的形状。另外，多个金属柱24的至少一个连接至下层布线18。
半导体元件10借助焊球15电连接至电路板17(更具体地，连接至下层布线18)。该连接实现为倒装芯片连接。半导体元件10和电路板17之间的空间用底层填料树脂16填充。
焊球15是由焊料组成的球。焊球15通过电镀法、球转移法和印刷法贴附在电路板17上。焊球15由铅-锡共晶焊料或无铅焊料组成。
底层填料树脂16是由把硅石填料加到环氧材料所获得的材料组成的。底层填料树脂16减小了半导体元件10和焊球15的热膨胀系数之间的差异，因此底层填料树脂16会防止对焊球15的损伤。如果焊球15具有足够的刚性能够保持高可靠性，则底层填料树脂16不是必要的。
关于电路板17和半导体元件10的结合，可代替焊球15使用导电胶或铜凸块。在第一示范性实施例中，使用焊球15。
半导体元件10和电路板17的连接方法不限于以上描述的方法。
例如，半导体元件10可通过如图3所示的或半导体元件10的表面的粘接剂25粘附到电路板17，与粘附到电路板17的表面相反的表面可通过接合线26连接至电路板17(更具体地，下层布线18)。
可使用有机材料或银胶作为粘接剂25。接合线26是由主要由金组成的材料组成的且电连接半导体元件10和电路板17的电极。
例如，电路板17由至少一个布线层和绝缘层组成，如图2所示。
在图2中，绝缘层21是一层而布线层是两层：上层布线20和下层布线18，但绝缘层和布线层不限于该形式，且绝缘层和布线层可以是由所需数量的层制成的结构。
例如，电路板17的绝缘层21由光敏或非光敏的有机材料形成。可使用例如环氧树脂、环氧-丙烯酸树脂、聚氨酯丙烯酸树酯、聚脂树脂、酚醛树脂、聚酰亚胺树脂、BCB(苯环丁烯)、PBO(聚苯并噁唑)或聚降冰片烷树脂的材料作为有机材料。可选地，可使用通过用环氧树脂、环氧丙烯酸树脂、聚氨酯丙烯酸树酯、聚脂树脂、酚醛树脂、聚酰亚胺树脂、BCB(苯环丁烯)、PBO(聚苯并噁唑)或聚降冰片烷树脂充满由玻璃布或芳香聚酰胺纤维形成的织物或非织物获得的材料作为有机材料。在第一示范性实施例中，使用充满环氧树脂的玻璃布作为有机材料。
使用选自由铜、银、金、镍、铝和钯组成的组的至少一种金属或采用这些金属作为主要成分的合金作为包括在电路板17中的下层布线18、上层布线20和通路19。
根据电阻和成本的观点，下层布线18、上层布线20和通路19优选地由铜形成。
在第一示范性实施例中，下层布线18、上层布线20和通路19由铜形成。可在绝缘层21上形成焊料抗蚀剂以便露出上层布线20的一部分并覆盖上层布线20的剩余部分。
在具有其上面提供金属柱24的表面的电路板17中的下层布线18的一部分可与绝缘层21齐平或可相对于绝缘层21被压下。
当表面是平的时，可以应用由下层布线18组成的电极垫(未示出)以使电路板17和半导体元件10之间的引线结合连接中的间距变窄。另外，当进行连接时，接合线工具和绝缘层21之间的干扰消除会提高产率。
当下层布线18的部分被压下时(见图3)，绝缘层21起半导体元件10的倒装芯片连接中的抗蚀剂作用。结果，仅在被压下部分中形成焊球，由此消除了对分离地提供形成焊球的抗蚀剂图案的需求。
另外，可在电路板17的所希望位置提供电容器以用作电路的噪声滤波器。
优选地使用金属氧化物材料例如氧化钛、氧化钽、氧化铝(Al2O3)、二氧化硅(SiO2)、氧化锆(ZrO2)、氧化铪(HfO2)或五氧化铌(Nb2O5)作为组成电容的介质材料。可选地，可使用钙钛矿材料例如BST(钛酸锶钡)(BaxSr1-xTiO3)、PZT(锆钛酸铅)(PbZrxTi1-xO3)或PLZT(Pb1-yLayZrxTi1-xO3)或Bi序列分层化合物例如SrBi2Ta2O9作为介质材料。这里，值“x”和“y”满足关系0≤x≤1和0＜y＜1。另外，还可使用混合了无机或磁性材料的有机材料作为组成电容的介质材料。
使用玻璃、芳族聚酰胺、液晶聚合物和PTFE(聚四氟乙烯)中任一种作为密封层14。可选地，可使用一种材料作为密封层14，其是通过在环氧树脂、环氧-丙烯酸脂、聚氨酯丙烯酸酯、聚脂树脂、酚醛树脂、聚酰亚胺树脂、BCB(苯环丁烯)、PBO(聚苯并噁唑)或聚降冰片烷树脂中注入或层压加固材料27获得的，该加固材料27由来自玻璃、芳族聚酰胺、液晶聚合物和PTFT当中的多个组成。
当加固材料27为玻璃时可以实现低成本工艺。当加固材料27为芳族聚酰胺时可以获得高的水蒸汽渗透性。当加固材料27为液晶聚合物时提高了抗张强度和弹性模量。当加固材料27为PTFE时提高了热阻、冲击强度和高的绝缘性。
图2中的加固材料27是织物。图5中的加固材料27是膜。在两者任一情况下，加固材料27都没有接触金属柱24，但加固材料27可接触金属柱24，而不会导致问题。
密封层14中包含的加固材料27能够使密封层14的刚性增加。当加固材料27是织物时，不仅增加了密封层14的刚性，而且还可以减小加固材料27的表面变化且改进了激光处理的易用性。当加固材料27是非织物时，不仅增加了密封层14的刚性，而且还可以增加密封层14的水蒸汽渗透性。当加固材料27是膜时，不仅可以增加密封层14的刚性，而且还可以获得更薄的密封层14。
在第一示范性实施例中，使用充满环氧树脂的玻璃织物作为密封层14。
密封层14优选地由通过具有高弹性模量的材料提高半导体器件40的刚性的材料形成。可选地，密封层14优选地由导致密封层14和电路板17之间小的热膨胀差的材料形成以避免密封层14和绝缘层21结合的噁化。
另外，由于密封层14可以提高半导体器件40的刚性，所以电路板17可以做得更薄，由此可以实现具有低剖面和小翘曲的半导体器件。
根据第一示范性实施例，半导体元件10和金属柱24是通过包括加固材料27的密封层14固定的。结果，密封层14可以增加半导体器件40的刚性并且实现半导体器件40的翘曲减小。而且，由于密封层14可以增加半导体器件40的刚性，所以电路板17可以做得更薄。利用薄衬底作为电路板17可以实现具有少量翘曲而且薄的半导体器件40。
图6是示出根据本发明第二示范性实施例的半导体器件结构的实例的截面图。
根据第二示范性实施例的半导体器件包括下层布线18借助通路19电连接至上层布线20的电路板17。在电路板17的下层布线18侧上提供多个金属柱24、半导体元件10和密封层14。半导体元件10由密封层14覆盖。密封层14还提供在多个金属柱24之间。在金属柱24的表面中，露出了与接触电路板17的表面相反的表面。密封层14由包括加固材料27的有机材料形成。嵌入材料29提供在加固材料27和半导体元件10或金属柱24之间(金属柱24外围附近)。
图6是根据第二示范性实施例的半导体器件的金属柱24和加固材料27与嵌入材料29的部分的放大图。
以下说明涉及关于根据第一示范性实施例的半导体器件的差异。没有具体说明的部分与根据第一示范性实施例的半导体器件的说明中的部分相同。
嵌入材料29由光敏或非光敏的有机材料形成。有机材料是例如环氧树脂、环氧-丙烯酸树脂、聚氨酯丙烯酸树酯、聚脂树脂、酚醛树脂、聚酰亚胺树脂、BCB(苯环丁烯)、PBO(聚苯并噁唑)和聚降冰片烷树脂的材料。嵌入材料29不包括加固材料27。
另外，嵌入材料29优选地具有比密封层14低的弹性模量以用作压力缓冲层。
另外，使用嵌入材料29可以固定金属柱24或半导体元件10的外围，并且其它区域可以由密封层14固定。对于每个区域采用不同的树脂能够选择对于每个区域翘曲的最佳有机材料。
根据第二示范性实施例，半导体元件10和金属柱24由包括加固材料27的密封层14间接固定。结果，半导体器件40的刚性可以通过密封层14增加，且可以实现半导体器件40的低翘曲。
另外，电路板17可以做得更薄，因为密封层14可以增加半导体器件40的刚性。使用薄衬底作为电路板17能够实现低翘曲的薄半导体器件40。
使用提供在具有比密封层14少的弹性树脂的加固材料27和半导体元件10或金属柱24之间的嵌入材料29允许这些部件起应力缓冲层作用，由此提高了半导体器件作为分离实体的可靠性和二次封装时的可靠性。
使用嵌入材料29允许金属柱24或半导体元件10的外围被嵌入材料29固定且允许其它区域被密封层14固定。对于每个区域采用不同的树脂能够选择对抗翘曲的理想有机材料，由此可以进一步抑制半导体器件的翘曲。
图7是示出根据本发明第三示范性实施例的半导体器件结构的实例的截面图。
图7中所示的半导体器件40包括下层布线18借助通路19电连接至上层布线20的电路板17。在电路板17的下层布线18侧上提供多个金属柱24、半导体元件10和密封层14。密封层14提供在多个金属柱24之间。在金属柱24的表面中，露出了与接触电路板17的表面相反的表面。密封层14由包括加固材料27的有机材料形成。半导体元件10嵌入在半导体元件密封层30中。密封层14和半导体元件密封层30起密封层作用。
以下说明涉及不同于第一示范性实施例的半导体器件40的部分。没有具体描述的部分与第一示范性实施例中描述的相同。
半导体元件密封层30由光敏或非光敏的有机材料形成。例如，有机材料是环氧树脂、环氧-丙烯酸树脂、聚氨酯丙烯酸树酯、聚脂树脂、酚醛树脂、聚酰亚胺树脂、BCB(苯环丁烯)、PBO(聚苯并噁唑)或聚降冰片烷树脂。半导体元件密封层30由与密封层14不同的材料形成。加固材料(未示出)可提供在与电路板17的连接表面相反的表面上或半导体元件10的外围上。
另外，如图8和9每个所示，半导体元件密封层30可伸出在密封层14上方或被压下在密封层14下方。
当半导体元件密封层30伸出时，半导体元件30可以做得更厚。在半导体元件10上增加半导体元件密封层30的树脂的厚度能够减小在半导体元件10上的翘曲。
可选地，当半导体元件密封层30被压下时，半导体元件10可以做得更薄且当与其它半导体器件连接时可以减小组件高度。
另外，如图10所示，密封层14可进一步嵌入到嵌入半导体元件10的半导体元件密封层30。
根据第三示范性实施例，半导体元件10和金属柱24由包括加固材料27的密封层14固定。因此半导体器件40的刚性可以由密封层14增加，且可以实现半导体器件的低翘曲。另外，密封层14增加半导体器件40的刚性，由此电路板17可以做得薄。利用薄衬底作为电路板17能够实现薄且具有减小的翘曲的半导体器件40。
而且，利用密封层14密封金属柱24和利用半导体元件密封层30密封半导体元件10允许选择用于减小各自区域中翘曲的最佳有机材料，由此可以大大抑制半导体器件的翘曲。
另外，可以自由地调节半导体元件密封层30和密封层14的高度。当半导体元件密封层30伸出超过密封层14时，半导体元件10可以做得更厚，且可以提高半导体元件10的刚性。增加半导体元件10上的半导体元件密封层30的树脂厚度可以进一步减小半导体元件10的翘曲。
可选地，当半导体元件密封层30被压下时，在上侧连接的半导体器件的焊球可以制作成小直径，由此可以进一步减小组件高度。
图11是示出根据本发明第四示范性实施例的半导体器件结构的截面图。
在图11所示的半导体器件中，在电路板17的下层布线18侧上提供多个金属柱24、半导体元件10和密封层14。半导体元件10由密封层14覆盖。还在多个金属柱24之间提供密封层14。在金属柱24的表面中，露出了与接触电路板17的表面相反的表面。图11中所示的半导体器件具有包括经由插入的连接材料与连接至其它半导体器件的这些露出表面堆叠的两个半导体器件的结构。
至少一个金属柱24连接至下层布线18并起外部端子部分作用。作外部端子的功能应包括至少电连接至外部元件的功能。
在图11中，图2中所示的半导体器件起下部半导体器件作用，但对于该半导体器件可使用第一至第三示范性实施例中任一个。
在图11中，一个半导体元件10被安装在每个半导体器件上，但可安装多个元件。
而且，在图11中堆叠了两个半导体器件，但可堆叠三个或更多的半导体器件。
可选地，一个高的热量排放半导体器件还可通过不堆叠半导体器件而是如图12所示在金属柱24上安装热沉32形成。
热沉32由铜、镍、铝、金、银、钯、铂、铁、不锈钢、锌、镁、钛、42-合金、铬、钒、铑、钼或钴中的任一种、或多种这些元素的某一材料组成。根据成本和容易加工的观点，铜尤其适合作为热沉器32。在第四示范性实施例中，使用铜作为热沉32。
热沉32可进一步如图12所示以散热片形成，或可以不带散热片形成。对于连接热沉32和半导体器件40，可在半导体器件40的整个表面上方形成粘接层(未示出)，或可在不同于金属柱24的露出表面的点形成粘接层(未示出)。
根据第四示范性实施例，半导体元件10和金属柱24由包括加固材料27的密封层14固定。结果，半导体器件40的刚性可以由密封层14增加且可以实现具有低翘曲的半导体器件40。而且，半导体器件40的刚性可以由密封层14增加，由此电路板17可以做得更薄。
利用薄衬底作为电路板17能够实现薄且受到少许翘曲的半导体器件40。
半导体器件的堆叠结构具有允许在多个水平面堆叠半导体器件、增加半导体元件组件中的自由度和增加存储容量中例如处理变化的灵活性的优点。
另外，通过安装热沉可以实现高热量排放的半导体器件。
半导体器件的制造方法
图13A至13L是依次示出根据本发明第一示范性实施例的半导体器件的制造方法的步骤的截面图。该方法是用于制造根据如图2所示的第一实施例的半导体器件。
首先，如图13A所示，对金属体33按需要进行湿法清洗、干法清洗、拉平和粗糙化处理。
金属体33最后被使得起金属柱24作用。因此，使用选自由铜、铝、镍、不锈钢、铁、镁和锌组成的组中的至少一种金属、或采用这些金属作为主要成分的合金作为金属体33。根据电阻和成本的观点尤其希望选择铜作为金属体33。在本实施例中使用铜。
接下来，如图13B所示，例如，通过减法、半加法或全加法在金属体33上形成下层布线18。
减法是通过在提供于衬底上的铜箔上形成所希望图案的抗蚀剂且在蚀刻不需要的铜箔之后剥离掉抗蚀剂获得所希望图案的方法。
半加法是通过无电镀法、溅射法或CVD(化学气相沉积)法形成电源层、然后形成以所希望图案提供开口的抗蚀剂、在抗蚀剂开口中通过电镀法沉积金属且在移除抗蚀剂之后蚀刻电源层而获得所希望布线图案的方法。
全加法是通过在衬底上吸收无电镀催化剂、然后通过抗蚀剂形成图案、用保持未变化的该抗蚀剂激活该催化剂以作为绝缘膜、以及然后通过无电镀法在绝缘膜的开口中沉积金属来获得所希望图案的方法。
使用选自由例如铜、银、金、镍、铝和钯组成的组中的至少一种金属、或采用这些金属作为主要成分的合金作为下层布线18。根据电阻和成本的观点，下层布线18优选地由铜形成。在本实施例中，使用了铜。
接下来，如图13C所示，在下层布线18上层压绝缘层21。
例如，绝缘层21由光敏或非光敏的有机材料形成。使用例如环氧树脂、环氧-丙烯酸树脂、聚氨酯丙烯酸树酯、聚脂树脂、酚醛树脂、聚酰亚胺树脂、BCB(苯环丁烯)、PBO(聚苯并噁唑)或聚降冰片烷树脂的材料作为有机材料。可选地，可使用由充满了例如环氧树脂、环氧-丙烯酸树脂、聚氨酯丙烯酸树酯、聚脂树脂、酚醛树脂、聚酰亚胺树脂、BCB(苯环丁烯)、PBO(聚苯并噁唑)或聚降冰片烷树脂的玻璃布或芳香聚酰胺纤维形成的织物或非织物作为有机材料。在本实施例中，使用充满了环氧树脂的玻璃布。
接下来，如图13D所示，在绝缘层21中形成通路孔34。
当绝缘层21由光敏材料形成时，通过光刻形成通路孔34。当绝缘层21为非光敏材料时，或当绝缘层21为光敏材料但由具有低图案分辨率的材料形成时，通过激光处理法、干蚀刻法或吹风法形成通路孔34。在本实施例中，使用激光处理法。
接下来，如图13E所示，通过用由例如铜、银、金、镍、铝和钯组成的组中的至少一种金属或采用这些金属作为主要成分的合金填充通路孔34的内部形成通路19。
在本实施例中，使用铜。填充方法是通过电镀、无电镀、印刷或熔融金属吸力法实施的。
可选地，可采用一种预先在通路19的位置形成导体柱、之后形成绝缘层21和然后通过抛光/研磨来研磨绝缘层21的表面以暴露出导体柱并由此形成通路19的方法。可选地，可用与下文描述的上层布线20相同的步骤形成通路19。
通过例如减法、半加法或全加法的方法在通路19上进一步形成上层布线20。
使用选自由例如铜、银、金、镍、铝和钯组成的组中的至少一种金属或采用这些金属作为主要成分的合金作为上层布线20。尤其是根据电阻和成本的观点，上层布线20优选地由铜形成。在本实施例中，使用半加法，并且对于上层布线20采用铜。
接下来，如图13F所示，在上层布线20上形成焊料抗蚀剂22的图案。
形成焊料抗蚀剂22用于制造电路板17的耐燃性和表面电路保护。该材料可由例如环氧树脂、丙烯、聚氨酯或聚酰亚胺的有机材料组成；并且根据需要可使用无机或有机填充材料作为添加剂。另外，不需要在电路板上提供焊料抗蚀剂22。
尽管图13B中示出了从形成布线层开始形成电路板17的实例，但还可从绝缘层开始形成电路板17。
在图13中，示出了电路板17由两个导电层和一个绝缘层组成的实例，还可通过对应于所希望的层数重复上述步骤许多次来形成电路板17。
接下来，如图13G所示，金属柱掩模35，其利用至少一种有机材料或不同于金属体33的至少一种金属材料形成，在金属体33的表面上的，待在与接触电路板17的表面相反的表面上提供金属柱24的希望位置形成从0.01μm至100μm的厚度。
如果掩模35由有机材料形成，且如果有机材料为液体形式，则使用旋涂法、模压涂层法、幕式淋涂法或印刷法层压掩模35。如果有机材料为干膜，则例如通过层压法层压掩模35。
在层压有机材料之后，通过例如干法的工艺、工艺之后如果有机材料为光敏的则通过例如光处理或如果有机材料为非光敏的则通过例如激光处理法在待提供金属柱24的希望位置上形成有机材料来固化有机材料。
当掩模35由金属材料形成时，在金属体33的表面上，与接触电路板17的表面相反的表面上，层压电镀抗蚀剂。
如果电镀抗蚀剂为液体形式，则使用旋涂法、模压涂层法、幕式淋涂法或印刷法层压电镀抗蚀剂；且如果电镀抗蚀剂为干膜，则通过层压法层压电镀抗蚀剂。
在层压电镀抗蚀剂之后，通过例如干法工艺、工艺之后如果电镀抗蚀剂为光敏的则使用光处理或如果电镀抗蚀剂为非光敏的则使用激光处理法在待提供金属柱24的希望位置提供电镀抗蚀剂中的开口，来固化电镀抗蚀剂。
然后使用电镀法或无电镀法在电镀抗蚀剂的开口中沉积不同于金属体33的金属材料，方法之后移除电镀抗蚀剂，由此在待提供金属柱24的希望位置形成金属材料。
在本实施例中，在掩模35中涂敷金属材料(镍)，光敏液体电镀抗蚀剂(由Tokyo Ohka Kogyo，Ltd.制造的商标名PMER P-LA900)用于电镀抗蚀剂，通过旋涂法将电镀抗蚀剂涂敷到金属体33，通过光刻在电镀抗蚀剂中提供开口，通过电镀法在电镀抗蚀剂的开口中电镀镍，并将厚度设定为10μm。
接下来，如图13H所示，利用掩模35的上表面的蚀刻剂对金属体33进行蚀刻工艺。
使用浸渍法或喷雾法作为蚀刻法。在本实施例中，采用使用具有氨作为主要成分的碱性铜蚀刻剂(由Meltex，Inc制造的商标名E-Process)的喷雾蚀刻法。
接下来，如图13I所示，通过电路板17的表面上，与在上面形成金属柱24的表面相反的表面上的焊球15，将半导体元件10倒装芯片连接至电路板17。
然后使用底层填料树脂16填充上面形成焊球15的半导体元件10和电路板17之间的空间。
以减少半导体元件10和焊球15的热膨胀系数差和防止损坏焊球15的目的使用底层填料树脂16。
如果焊球15具有足够的强度保持所希望的可靠性，则用底层填料树脂16填充该空间是不必要的。
焊球15是由焊料组成的微小球且通过电镀法、球转移和印刷法形成。可以从铅-锡共晶焊料和无铅焊料中选择作为适合于焊球15的材料。
底层填料树脂16由环氧树脂材料形成。在使用焊球15连接半导体元件10之后涂敷底层填料树脂16。
另外，可通过金属例如铜的凸块而不是通过由焊料组成的微小球来实施半导体元件10和电路板17之间的连接。
尽管连接图13I中描述的半导体元件10的形式使用倒装芯片连接，但也可使用通过引线结合的连接、或布线板的布线直接连接至半导体元件10的连接端子部分而不使用凸块或引线结合的连接。
接下来，如图13J所示，由密封层14密封半导体元件10和金属柱24。
使用玻璃、芳族聚酰胺、液晶聚合物或PTFE中的任一种作为密封层14。可选地，还可使用由玻璃、芳族聚酰胺、液晶聚合物和PTFE多个组成的加固材料27浸渍在或层压环氧树脂、环氧-丙烯酸树脂、聚氨酯丙烯酸树酯、聚脂树脂、酚醛树脂、聚酰亚胺树脂、BCB(苯环丁烯)、PBO(聚苯并噁唑)或聚降冰片烷树脂的材料作为密封层14。
例如使用真空增压和真空层压的方法在金属柱24上和安装了半导体元件10的上面层压密封层14。
当加固材料27为玻璃时，可以实现低成本工艺。当加固材料27为芳族聚酰胺时，可以获得高的水-蒸汽渗透性。当加固材料27为液晶聚合物时，提高了抗张强度和弹性模量。当加固材料27为PTFE时，提高了热阻、冲击强度和高绝缘。
下面的说明关于层压密封层14的方法。
如图14所示，在密封层14上预先提供半导体元件区域开口36和金属柱区域开口37。可使用例如激光、钻孔、干法蚀刻和湿法蚀刻的方法作为形成开口的方法。在本实施例中，使用激光。
接下来，如图15所示，堆叠每个衬底以便把电路板17上的半导体元件10和金属柱24插入到密封层14上的半导体元件区域开口36和金属柱区域开口37。另外，在密封层14上堆叠没有开口和加固材料的密封层41。还可仅在半导体元件10上堆叠没有开口和加固材料的密封层41。
接下来，通过成批固化这些堆叠的树脂部件可以在半导体元件10和金属柱24周围有效地提供加固材料27。
接下来，如图13K所示，与接触电路板17的表面相反的金属柱24的表面通过研磨或抛光从密封层14的表面暴露出来而且这些表面被制作得与密封层14的表面实际上齐平。
接下来，如图13L所示，在与金属柱24相反的电路板17的表面上安装焊球15。
根据本实施例，可以有效地形成第一实施例的半导体器件。
半导体元件10和金属柱24由包括加固材料27的密封层14固定，由此半导体器件40的刚性可以由密封层14增加，且实现了半导体器件40的翘曲减小。
另外，密封层14可以增加半导体器件40的刚性。结果，电路板17可以做得更薄。利用薄衬底作为电路板17能够实现具有少许翘曲而且薄的半导体器件40。
图16A示出了提供在电路板17上的半导体元件10和金属柱24，图16B是该结构的上平面图。
图16C是用于说明当重叠和堆叠密封层14和密封层41时的状态的截面图，密封层14包括其中提供了半导体元件区域开口36和金属柱区域开口37的加固材料27的密封层14，密封层41没有开口和加固材料且布置在图16A所示的电路板17上的密封层14的上方，以及图16D是该结构的上平面图。
图16E是堆叠之后的截面图，图16F是该结构的上平面图。
图17是示出制造根据本发明第二示范性实施例的半导体器件的方法的一部分的截面图。本实施例的制造方法是用于制造例如图6所示的第二实施例的半导体器件。
以下说明关于不同于制造半导体器件的方法的第一示范性实施例的部分。没有具体说明的部分与制造半导体器件的方法的第一示范性实施例的说明相同。
说明首先关于堆叠密封层14的方法。
如图17所示，预先在密封层14中提供半导体元件区域开口36和金属柱区域开口37。利用例如激光、钻孔、干法蚀刻和湿法蚀刻形成开口。在本实施例中，使用激光。
接下来，如图17所示，堆叠每个衬底以便将电路板17上的半导体元件10和金属柱24插入到密封层14上的半导体元件区域开口36和金属柱区域开口37中。另外，在密封层14上堆叠不同于密封层14且没有开口和加固材料的嵌入材料29。
接下来，通过批量固化这些堆叠的树脂部分在半导体元件10和金属柱24周围可以有效地提供加固材料27，且可以在半导体元件10和金属柱24和加固材料27之间形成不同于密封层14的嵌入材料29。
根据本实施例，可以有效地形成第二示范性实施例的半导体器件。
另外，半导体元件10和金属柱24由包括加固材料27的密封层14固定。结果，半导体器件40的刚性可以由密封层14增加，且可以实现半导体器件40的低翘曲。而且，半导体器件40增加的刚性能够使用薄衬底作为电路板17。使用薄衬底能够实现具有少许翘曲而且薄的半导体器件。
而且，通过使提供在加固材料27和半导体元件10或金属柱24之间的嵌入材料29比密封层14的弹性树脂少，这些部件起应力缓冲层的作用，由此提高了半导体器件作为单个实体的可靠性和二次封装的可靠性。
另外，通过利用嵌入材料29，半导体元件10和金属柱24的外围可以由嵌入材料29固定，且剩余区域可以由密封层14固定。通过使每个区域具有不同的树脂，可以在每个区域选择用于防止翘曲的最佳有机材料以能够进一步抑制半导体器件的翘曲。
图18是示出制造根据本发明第三示范性实施例的半导体器件的方法的一部分的截面图。该实施例的制造方法是用于制造根据例如图7中所示的第三示范性实施例的半导体器件。
以下说明涉及不同于半导体器件的制造方法的第一示范性实施例的部分。没有具体说明的部分与半导体器件的制造方法的第一示范性实施例的说明相同。
如图18A所示，在电路板17上提供半导体元件10和金属柱24。
接下来，如图18B所示，仅在半导体元件10的区域中层压半导体元件密封层30。
半导体元件密封层30的材料例如是环氧树脂、环氧丙烯酸树脂、聚氨酯丙烯酸树酯、聚脂树脂、酚醛树脂、聚酰亚胺树脂、BCB(苯环丁烯)、PBO(聚苯并噁唑)或聚降冰片烷树脂。例如，利用传递模塑法、压缩形成模铸法、印刷法、真空增压法或真空层压法提供半导体元件密封层30。
接下来，如图18C所示，仅在金属柱24的区域中层压密封层14。
预先在密封层14中提供金属柱区域开口37。例如，利用激光、钻孔、干法蚀刻或湿法蚀刻形成开口。在本实施例中，使用激光。
接下来堆叠每个衬底以便将电路板17上的金属柱24插入在密封层14上的金属柱区域开口37中。另外，可堆叠或不堆叠没有开口和加固材料的密封层41。
可选地，可在如图19A-19D所示的半导体元件10的区域中堆叠没有开口和加固材料的密封层41。另外，还可堆叠嵌入材料29。
半导体元件密封层30和金属柱24的嵌入还可按相反的顺序。
根据本实施例，有效地形成第三示范性实施例的半导体器件。
另外，半导体元件10和金属柱24由包括加固材料27的密封层14固定。结果，半导体器件40的刚性可以由密封层14增加且可以实现半导体器件40的翘曲减小。另外，由密封层14实现的半导体器件40的刚性增加允许使用更薄衬底作为电路板17，由此可以实现具有减小的翘曲和更薄形式的半导体器件。
另外，由密封层14密封金属柱24和由半导体元件密封层30密封半导体元件10允许选择防止在每个区域中的翘曲的最佳有机材料，由此可以进一步抑制半导体器件的翘曲。
另外，半导体元件密封层30和密封层14的高度可以自由地调节。当半导体元件密封层30伸出密封层14上方时，半导体元件30可以做得更厚。增加半导体元件10上的半导体元件密封层30的树脂厚度能够使半导体元件10上的翘曲减小。另一方面，当半导体元件密封层30被压下在密封层14下方时，半导体元件10可以做得薄且当与另一半导体器件连接时的组件高度可以做得更低。
图20是示出制造根据本发明第四示范性实施例的半导体器件的方法的一部分的截面图。该实施例的制造方法是用于制造根据例如图11所示的第四示范性实施例的半导体器件的。
以下说明关于不同于半导体器件的制造方法的第一示范性实施例的部分。没有具体说明的部分与半导体器件的制造方法的第一示范性实施例的说明相同。
在本实施例的半导体器件的制造方法中，根据第一至第三示范性实施例的半导体器件通过如图20A-20B所示的金属柱24连接至另一半导体器件。
可使用第一至第三示范性实施例的半导体器件的任一个作为图20中所示的半导体器件。在上部半导体器件的对应于下部半导体器件的金属柱24的露出表面的点上提供焊球15。
首先利用安装设备在下部半导体器件的上层上堆叠上部半导体器件。可选地，可在板上封装下部半导体器件且然后安装上部半导体器件。
下部半导体器件的金属柱24起外部端子作用。作为外部端子的功能应包括至少电连接至外部元件的功能。至少一个金属柱24连接至下层布线18。
接下来，当保持该状态时，将该组件引入到回流炉中以施加至少焊球15的熔点的温度，由此使焊球15连接至金属柱24。还可采用代替回流通过安装设备熔融焊球15的方法。
根据本实施例，有效地形成第四示范性实施例的半导体器件。
另外，半导体元件10和金属柱24由包括加固材料27的密封层14固定。半导体器件40的刚性因此可以由密封层14增加，且实现具有减小翘曲的半导体器件40。另外，由密封层14实现的半导体器件40的刚性的增加能够使用薄衬底作为电路板17。使用薄衬底能够实现具有减小翘曲且薄形式的半导体器件。
本实施例有各种优点，例如能够堆叠多层半导体器件、增加组合半导体元件的自由度以及提高存储容量变化的处理灵活性。另外，通过安装热沉可以实现高热量排放的半导体器件。
每个示范性实施例都显示出下面的作用：
密封剂不仅覆盖安装半导体元件10的位置而且覆盖上面安装了半导体元件10的电路板17的整个表面。在该情况下，不仅可以保持半导体器件的刚性，而且还可以实现低翘曲。
另外，当密封层14包括加固材料27时，进一步提高了半导体器件的总刚性，提高封装的单元可靠性，并且因为封装衬底(电路板)17和半导体元件10的热膨胀差降低了，所以还提高了封装可靠性。
而且，由于半导体器件的刚性增加了，所以当在半导体器件上方堆叠封装时可以实现具有上部封装的高连接可靠性。
另外，在半导体器件中提供的金属柱24不仅可以起连接端子的作用，而且起热量排放路径作用，由此可以实现高热量排放的半导体器件。
而且，由密封层14引起的半导体器件的刚性增加允许电路板17的相应变薄。使用薄衬底作为电路板17允许实现具有低翘曲且薄形式的半导体器件。
制造上述半导体器件的方法使用金属体，其是薄衬底的支撑基底，作为连接端子。结果，除去了对新形式电极的需求，由此对于半导体器件相比对于相关技术的堆叠封装SiP结构能够实现更低的成本。
另外，可以在半导体元件10和金属柱24的外围有效地提供包括加固材料27的密封层14。
为了提高其上面形成金属柱24的电路板的处理能力，留下支撑基底金属体的一部分。因此可以保持其上面形成金属柱24的电路板17的刚性。
密封层优选地是包括加固材料的有机材料。
加固材料优选地由玻璃、芳族聚酰胺、液晶聚合物和PTFE中任一种组成或由多种这些材料组成。
加固材料优选地是织物。
加固材料优选地是非织物。
加固材料优选地是膜。
加固材料和金属柱优选地不接触。
加固材料和金属柱优选地接触。
嵌入材料优选地提供在金属柱的外围。
密封层优选地包括覆盖半导体元件的半导体元件密封层。
关于金属柱的形状，接触电路板的金属柱的表面面积优选地大于金属柱的相对表面的面积。
表面上面提供了金属柱的电路板的布线层的一部分优选地低于绝缘层。
半导体元件和电路板之间的连接优选地是倒装芯片连接或引线结合连接二者之一。
半导体元件和电路板之间的连接优选地是电路板布线直接连接至半导体元件的连接端子部分的连接。
优选地存在多个金属柱，金属柱的任一个都优选地连接至布线层且用作与另一半导体器件的连接部分。
金属柱优选地连接至热沉。
嵌入半导体元件和金属柱优选地包括：在密封层中形成半导体元件区域开口和金属柱区域开口；堆叠在其上面提供了半导体元件和金属柱的电路板上已经形成开口的密封层；以及在密封层上堆叠没有开口和加固材料的第二密封层。
嵌入半导体元件和金属柱优选地包括：在密封层中形成半导体元件区域开口和金属柱区域开口；堆叠在其上面提供了半导体元件和金属柱的电路板上已经形成开口的密封层；以及在该密封层上堆叠嵌入材料。
嵌入半导体元件和金属柱优选地包括：在半导体元件密封层中嵌入半导体元件；以及在密封层中嵌入金属柱。
嵌入半导体元件和金属柱优选地包括：在密封层中嵌入金属柱；以及在半导体元件密封层中嵌入半导体元件。
优选包括用半导体器件的金属柱堆叠半导体器件作为电连接部分。
根据本发明的示范性优点是提供可以同时实现具有低剖面和封装翘曲减小的组件高度的半导体器件和制造这种半导体器件的方法的能力。
虽然已利用具体术语描述了本发明的示范性实施例，但这种描述仅是用于说明的目的，且要明白，可以进行改变和变化，而不脱离以下权利要求的精神或范围。

Claims (8)

1.一种半导体器件，其中半导体元件安装在由绝缘层和布线层制成的电路板的一侧上，所述半导体器件包括：
金属柱，提供在所述电路板的其上安装了所述半导体元件的一侧上；和
密封层，提供在所述电路板的其上安装了所述半导体元件的一侧上，以便覆盖所述半导体元件以及仅暴露出所述金属柱的一部分，
其中，嵌入材料提供在所述密封层和所述半导体元件之间，或者提供在所述密封层和所述金属柱之间，
其中，所述嵌入材料具有比所述密封层低的弹性模量以用作压力缓冲层。
2.一种半导体器件，其中半导体元件安装在由绝缘层和布线层制成的电路板的一侧上，所述半导体器件包括：
金属柱，提供在所述电路板的其上安装了所述半导体元件的一侧上；和
密封层，提供在所述电路板的其上安装了所述半导体元件的一侧上，以便覆盖所述半导体元件以及仅暴露出所述金属柱的一部分，
其中所述密封层包括用于覆盖所述半导体元件的半导体元件密封层，
其中，所述半导体元件密封层伸出在所述密封层上方或被压下在所述密封层下方。
3.一种制造半导体器件的方法，包括：
在金属体上形成由绝缘层和布线层组成的电路板；
在所述金属体的、与所述金属体的接触所述电路板的表面相对的表面上形成掩模；
通过利用所述掩模移除所述金属体的一部分形成金属柱；
在其上已经形成了所述金属柱的所述电路板上安装半导体元件；
在密封层中嵌入所述半导体元件和所述金属柱；和
通过移除所述密封层的一部分暴露出所述金属柱的作为接触所述电路板的相对表面的表面。
4.根据权利要求3所述的制造半导体器件的方法，其中嵌入所述半导体元件和所述金属柱包括：
在所述密封层中形成半导体元件区域开口和金属柱区域开口；
在其上已经提供了所述半导体元件和所述金属柱的所述电路板上堆叠其中已经形成了所述开口的所述密封层；和
在所述密封层上堆叠没有开口和加固材料的第二密封层。
5.根据权利要求3所述的制造半导体器件的方法，其中嵌入所述半导体元件和所述金属柱包括：
在所述密封层中形成半导体元件区域开口和金属柱区域开口；
在其上已经提供了所述半导体元件和所述金属柱的所述电路板上堆叠其中已经形成了所述开口的所述密封层；和
在所述密封层上堆叠嵌入材料；
批量固化所堆叠的部件，
其中嵌入材料不同于密封层并且没有开口和加固材料。
6.根据权利要求3所述的制造半导体器件的方法，其中嵌入所述半导体元件和所述金属柱包括：
在半导体元件密封层中嵌入所述半导体元件；和
在密封层中嵌入所述金属柱。
7.根据权利要求3所述的制造半导体器件的方法，其中嵌入所述半导体元件和所述金属柱包括：
在密封层中嵌入所述金属柱；和
在半导体元件密封层中嵌入所述半导体元件。
8.根据权利要求3所述的制造半导体器件的方法，进一步包括用所述半导体器件的所述金属柱作为电连接部来堆叠半导体器件。
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