TW201230259A - A semiconductor package and a semiconductor equipment - Google Patents

A semiconductor package and a semiconductor equipment Download PDF

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Publication number
TW201230259A
TW201230259A TW100131022A TW100131022A TW201230259A TW 201230259 A TW201230259 A TW 201230259A TW 100131022 A TW100131022 A TW 100131022A TW 100131022 A TW100131022 A TW 100131022A TW 201230259 A TW201230259 A TW 201230259A
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TW
Taiwan
Prior art keywords
wiring substrate
semiconductor
reinforcing member
semiconductor element
package
Prior art date
Application number
TW100131022A
Other languages
Chinese (zh)
Inventor
Ryoichi Okada
Kenya Tachibana
Takeshi Hosomi
Original Assignee
Sumitomo Bakelite Co
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Filing date
Publication date
Application filed by Sumitomo Bakelite Co filed Critical Sumitomo Bakelite Co
Publication of TW201230259A publication Critical patent/TW201230259A/en

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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Abstract

The semiconductor package (1) of the present invention has: the wiring substrate (2), the semiconductor device (3) bonded to one side of the wiring substrate (2), the first reinforcing member (4) bonded to the surface, which does not bind to the semiconductor device (3), of the wiring substrate (2) on the side of the semiconductor device (3), wherein the thermal expansion coefficient of the first reinforcing member (4) is smaller than that of the wiring substrate (2), the wiring substrate (301) which is bound to the wiring substrate (2) via two or more metal bumps (400), wherein the wiring substrate (301) and the wiring substrate (2) are on opposite side of the first reinforcing member (4), and the semiconductor device (305) bonded to the surface of the wiring substrate (301) on the side opposite thereof relative to the wiring substrate (2), wherein the semiconductor device (3) contacts or does not contact the wiring substrate(301).

Description

201230259 六、發明說明： 【發明所屬之技術領域】 本發明係關於半導體封裝及半導體裴置。 【先前技術】 因應近年的電子機器高機能化及輕薄短小化之要求，正朝 電子零件的高密度積體化、以及高密度安骏化演進，該等電 子機器所使用的半導體封裝自習知起亦日益朝小型化且夕 針腳化進展。 半導體封裝隨其小型化，使用如習知引線框架形態的封農 在小型化時會有極限限制。因此’最近作為在電路基板上^ 裝晶片者係提案有BGA(Ball Grid Array，球拇陣列封幻、 CSP(Chip Scale Package，晶片尺寸型封幻之類的區域安裝 型新顆封裝方式。 BGA、CSP等新穎封裝所使用的中介層⑽叫。㈣，—般 係在纖維純巾含賴餘餘_成的絲上，形成導體 圖案或導體柱。 此種中介層與晶片間之熱賴係數差大。且，因為中介層 通常較晶片為大面積’故未與晶片接觸之部分的面積大。二 種未與晶片接觸之部分_性極低，會因如前述晶片與令介 層間之熱祕差而容易出輸曲情泥。另外，本發明中所謂 「熱膨脹係數」係指在30〜就範圍内，物體每代延伸的 長度，所謂「剛性」係指板狀物質的不易彎曲程度。 100131022 201230259 m已二有將分別設有中介層的2個封裝(上層封裴、下層封 冓造"料所謂P〇P(Paekage〇nPaekage)構造的 習知POP構造_|，會有下層㈣的巾介層因前述與 晶片間之熱膨脹差而容易出現㈣情形、及使電氣式連接可 靠度降低的問題。 再者，S知POP才冓造的封裝中，無法將在中介層間夹置 的晶片之熱有效率地發散，此種情形亦會成為引發如前述問 題的肇因。 [先行技術文獻] [專利文獻] [專利文獻1]日本專利特開2009-81261號公報 【發明内容】 (發明所欲解決之問題） 本發明之目的在於提供可防止因熱而造成不良情況發生 的半導體封裝及半導體裝置。 (解決問題之手段） 此種目的係可藉由下述（1)〜(25)的本發明達成。 (1)一種半導體封装’係具備有·· 第1佈線基板； 第1半導體元件’其係接合於上述第丨佈線基板其中一面； 補強構件，其係接合於上述第1佈線基板靠上述第丨半導 100131022 5 201230259 體元件側的面未接合上述第1半導體元件的部分處，且熱膨 脹係數小於上述第1佈線基板； 第2佈線基板，其係相對於上述補強構件設置在與上述第 1佈線基板相反侧，真經由2個以上之金屬凸塊而接合於上 述第1佈線基扳；以及 第2半導體元件，其係接合於上述第2佈線基板與上述第 1佈線基板相反侧的面 其中，上述第1半導體元件係對上述第2佈線基板呈非接 觸。 (2) —種半導體封裝，係具備有： 第1佈線基板； 第1半導體元件’其係接合於上述第1佈線基板其中一面； 補強構件，其係接合於上述第1佈線基板靠上述第1半導 體元件側的面未接合上述第1半導體元件的部分處’且熱膨 脹係數小於上述第1佈線基板； 第2佈線基板，其係相對於上述補強構件設置在與上述第 1佈線基板相反側’且經由2個以上之金屬凸塊而接合於上 述第1佈線基板；以及 第2半導體元件，其係接合於上述第2佈線基板與上述第 1佈線基板相反側的面； 其中，上述第1半導體元件係對上述第2佈線基板呈接觸。 (3) —種半導體封裝，係具備有： 100131022 6 201230259 第1佈線基板； 第1半導體元件，其係接合於上述第1佈線基板其中一面； 補強構件，其係接合於上述第1佈線基板與上述第1半導 體元件相反側的面，且熱膨脹係數小於上述第1佈線基板； • 第2佈線基板，其係相對於上述第1半導體元件設置在與 • 上述第1佈線基板相反側，且經由2個以上之金屬凸塊而接 合於上述第1佈線基板；以及 第2半導體元件，其係接合於上述第2佈線基板與上述第 1佈線基板相反側的面； 其中，上述第1半導體元件係對上述第2佈線基板呈非接 觸。 (4)一種半導體封裝，係具備有： 第1佈線基板； 第1半導體元件，其係接合於上述第1佈線基板其中一面； 補強構件，其係接合於上述第1佈線基板與上述第1半導 體元件相反側的面，且熱膨脹係數小於上述第1佈線基板； '' 第2佈線基板，其係相對於上述第1半導體元件設置在與 一 上述第1佈線基板相反側，且經由2個以上之金屬凸塊而接 合於上述第1佈線基板；以及 第2半導體元件，其係接合於上述第2佈線基板與上述第 1佈線基板相反側的面， 其中，上述第1半導體元件係對上述第2佈線基板呈接觸。 100131022 201230259 (5) —種半導體封裝，係具備有： 第1佈線基板； 第1半導體元件，其係接合於上述第1佈線基板其中一面； 第1補強構件，其係接合於上述第1佈線基板靠上述第1 半導體元件側的面未接合上述第1半導體元件的部分處，且 熱膨脹係數小於上述第1佈線基板； 第2補強構件，其係接合於上述第1佈線基板與上述第1 半導體元件相反侧的面，且熱膨脹係數小於上述第1佈線基 板； 第2佈線基板，其係相對於上述第1補強構件設置在與上 述第1佈線基板相反側，且經由2個以上之金屬凸塊而接合 於上述第1佈線基板；以及 第2半導體元件，其係接合於上述第2佈線基板與上述第 1佈線基板相反側的面， 其中，上述第1半導體元件係對上述第2佈線基板呈非接 觸。 (6) —種半導體封裝，係具備有： 第1佈線基板； 第1半導體元件，其係接合於上述第1佈線基板其中一面； 第1補強構件，其係接合於上述第1佈線基板靠上述第1 半導體元件側的面未接合上述第1半導體元件的部分處，且 熱膨脹係數小於上述第1佈線基板； 100131022 ⑧ 201230259 第2補強構件，其係接合於上述第^線基板與上述第i 半導體元件相反側的面，賴膨脹紐小於上述第ι佈線基 板； 第2佈線基板’其係相對於上述第."㈣構件設置在與上 述第1佈線基板相反側，且經由2個以上之金屬凸塊而接合 於上述第1佈線基板；以及 第2半導體元件，其係接合於上述第2佈線基板與上述第 1佈線基板相反側的面； ,、中上述第1半導體疋件係對上述第]佈線基板呈接觸。 ⑺如上述(5)或⑹所記載之半導體㈣，其中，上述第1 補強構件係形成包圍上述第1半導體元件周圍的形狀。 (8)如上述⑴、（3)、（5)及⑺中任一項所記載之半導體封 装’其中，上述第1半導體元件與上述第2佈線基板間之距 離係0.01mm以上且Q 8mm以下。 ⑼如上述(5)至⑻中任—項所記狀半導體封裝，其中 上述第1補強構件係對上述第2佈線基板呈非接觸：、 (1〇)如上述(6)或⑺所記載之半導體封裝，其中，上 補強構件係對上述第2佈線基板呈接觸。 ()、Κ(9)所錢之半導體封裝，其中，上述第1補強 構件與上述第2佈線基板間之距離，係大於上述上述第1 半導體元件與上述第2佈線基板間之距離。 (12)如上述(5)至⑴）中任—項所記載之半導體封裳，其 100131022 201230259 中，上述第1補強構件係設有依對上述各金屬凸塊呈非接觸 且包圍上述各金屬凸塊之方式所形成的2個以上開口部。 (13) 如上述（5)至（12)中任一項所記載之半導體封裝，其 中，在上述第1補強構件與上述各金屬凸塊之間設有絕緣 材。 (14) 如上述（5)至（13)中任一項所記載之半導體封裝，其 中，上述第1補強構件與上述第2補強構件分別與上述第1 半導體元件間之熱膨脹係數差在7ppm/°C以下。 (15) 如上述（5)至（14)中任一項所記載之半導體封裝，其 中，上述第1補強構件與上述第2補強構件分別係形成板狀。 (16) 如上述（5)至（15)中任一項所記載之半導體封裝，其 中，上述第1補強構件與上述第2補強構件分別係由金屬材 料構成。 (17) 如上述（16)所記載之半導體封裝，其中，上述金屬材 料係Fe-Ni系合金。 (18) —種半導體裝置，係具備有上述（1)至（17)中任一項所 記載之半導體封裝。 (19) 一種半導體封裝之製造方法，該半導體封裝係上述（1) 至（17)中任一項所記載之半導體封裝；該製造方法包括有： 將第1補強構件接合於第1佈線基板的步驟； 在上述第1佈線基板上接合第1半導體元件，而形成下層 封裝的步驟； 100131022 10 201230259 將第2半導體元件接人 的步驟；以及 ° ;佈線基板，而形成上層封裝 經由2個以上金屬凸塊，將上n 予以接合的步驟。 /、上返下層封褒 ⑽-種半導體料之料方法， 至⑼中任-項所記M之半導體封裂 十裝係上述⑴ 將第2補強構件接合於第】佈線基极的^方法包括有： 在上述第丨料騎與上述第 1驟， 合第⑽體元件⑽爾⑽.Γ側的面’接 將第2半導體70件接合於第2佈線基板，而 的步驟；以及 ^成上層封裝 經由2個以上金屬凸塊，將上述上 予以接合的步驟。 d錢上述下層封| ⑼-種半導體料之製造方法，該 至⑼中任-項所記載之半導體封裝；二包^0) 將第1補強構件接合於第！佈線基板的步驟；有： 將上述第2㈣構件接合於第丨佈線騎的步驟“ ^上述第^佈線基板與上述第2補強構件相反側的面 δ第1半導體元件而形成下層封裝的步驟； 將第2半導體元件接合於第2佈線基板，而形 的步驟；以及 了裝 經由2個以上金屬凸塊，將上述上層封裝與上述下層封较 100131022 201230259 予以接合的步驟。 (22)如上述(19)或(21)所記載之半導體封裝之製造方法， 其中’將第1補強構件接合於上述第i佈線基板的步驟，係 包括有： 準備金屬層與預浸㈣積層體，並在上述積層體的預浸片 側之面接合第1補強構件的副步驟； 在上述預浸片中形成貫通孔的副步驟； 在上述貫通孔中形成導體柱的副步驟； 藉由對上述金屬層施行圖宰 驟;以及 Ώ案化而形成導體圖案的副步 使上述預浸片硬化的副步驟。 (23) 如上述（19)至（22)中任一項 ϋ u + 員斤5己载之半導體封裝之製 造方法，其中，隨上述金屬凸塊的冷卻，上述 厚度方向膨脹，使上述上層封裝 ^免係朝 封裝的p半導體元件成為遠離42態佈線基板與上述下層 (24) 如上述（19)至（22)中任一 :， 造方法，其中，在上述上層封裝與之半導體封裝之製 隔物，並在上述上層封裝與上層封裝之間配置間 除上述間隔物，使上述上層封I的層封裝之接合後，藉由移 封裝的第1半導體元件成為遣U 2佈線基板與上述下層 碾離之狀態。 (25) 如上述（19)至（22)中任〜項戶^ 造方法，其中，朝上述上層封、所记栽之半導體封裝之製 、、上述下層封裴互相靠近之 100131022 1 ^ 201230259 方向，對該等加壓，而使上述上層封裝的第2佈線基板與上 述下層封裝的第1半導體元件成為接觸之狀態。 (發明效果） 根據本發明的半導體封裝，因為第1佈線基板利用補強構 件進仃補強（特別因為補強構件係與第i半導體元件形成一 體並補強第1佈線基板），故可防止或抑制因第1佈線基板 與第1半導體元件間之熱膨脹係數差而造成的翹曲情形。結 果’可提升將第2佈線基板與第1佈線基板予以連接的金屬 凸塊之連接可靠度、將第1半導體元件與第1佈線基板予以 連接的金屬凸塊之連接可靠度、佈線基板内部的導體圖案· ¥體柱之連接可罪度、以及將第1佈線基板與母板予以連接 的金屬凸塊之連接可靠度。 再者，根據本發明的半導體封裝，當第丨半導體元件與第 2佈線基板呈非接觸的情況，透過在第1半導體元件與第2 佈線基板間形成的間隙施行通氣，便可將第1半導體元件的 熱有效率地朝外發散。另一方面，當第1半導體元件與第2 佈線基板呈接制情況’可將第1半導體元件賴經由第2 佈線基板有效率地朝外發散。又，因為第1佈線基板係如前 述般被補強，故可不需要提高第1佈線基板本身的剛性，可 削薄第1佈線基板的厚度。故，可提高第丨佈線基板厚度方 向的熱傳導性，亦可將來自帛！半導體元件的熱經由第i 佈線基板有效率地朝外發散。由此，本發明的半導體封裝係 100131022 13 201230259 散熱性優異。 前述的半 再者’根據本發明的半導體裝置，因為具備有如 導體封裝，故可靠度優異。 【實施方式】 以下，根據所附示圖式，針對本發明半導體封骏及半導體 裝置的較佳實麵態進行說明，惟本發明並残*限於該等 實施形態。在不脫逸本發明主旨的範圍内，亦可就構造進一 附加、省略、取代、以及其他變更。 <第1實施形態> (半導體封裝） 首先’針對本發明的半導體封裝進行說明。 圖1所示係本發明第1實施形態的半導體封襞示意剖視 圖，圖2所示係圖i所示半導體封裝的俯視圖，圖3所示係 圖1所示半導體封裝的底視圖，圖4所示係圖丨所示半導體 封裝的製造方法一例圖。另外，以下的說明中，為求說明上 的方便，將圖1中的上側稱「上」，將下側稱「下」。又，圖 1至4中，分別為求說明上的方便，半導體封裝的各部位有 誇張描續' 情形。 如圖1所示’半導體封裝i係具備有佈線基板2、搭戴於 该佈線基板2上的半導體it件3、第丨補強構件4、第2補 強構件5、佈線基板301、格栽於該佈線基板3〇1上的半導 體元件305、以及將佈線基板2與佈線基板3〇1予以連接的 100131022 14 201230259 複數金屬凸塊400。 該半導體封裝1係具有在佈線基板（第1佈線基板)2上搭 載著半導體元件（第1半導體元件)3的下層封裝500、與在 佈線基板(第2佈線基板)301上搭載著半導體元件（第2半導 . 體元件）3〇5的上層封裝300呈重疊的P0p(package 〇n • Package)構造。 根據此種半導體封裝卜即便與半導體元件3相接合的部 分以外之部分處，因為佈線基板2利用第i補強構件4進行 補強，故增加下層封裝500整體的剛性。特別係因為第1 補強構件4的熱膨脹係數小於佈線基板2(具體而言係後述 基板21)，故與半導體元件3橫跨佈線基板2整面設置的情 況同樣的，可抑制或防止因佈線基板2與半導體元件3間之 熱膨脹係數差所造成的佈線基板2發生翹曲情形。 再者，如後述，因為半導體元件3與佈線基板3〇1係非接 觸’故透過半導體元件3與佈線基板3〇1間所形成之間隙施 行通氣便可將半導體元件3的熱有效率地朝外邊發散。 又’因為佈線基板2係如前述般經補強，故不需要提高佈線 土板本身的剛性，可削薄佈線基板2的厚度，所以可提高 佈線基板2的厚度方向熱傳導性，來自半導體it件3的熱可 紅由佈線基板2而發散。由此，半導體封裝1的散熱性優異。 又，藉由適當選擇第1補強構件4與第2補強構件5的構成 材料’亦可提高半導體封们的散熱性。 100131022 15 201230259201230259 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a semiconductor package and a semiconductor device. [Prior Art] In response to the demand for higher performance and lighter and thinner electronic devices in recent years, the high-density integration of electronic components and the development of high-density security, the semiconductor packages used in these electronic devices are known. It is also becoming more and more miniaturized and progressing. As semiconductor packages are miniaturized, there is a limit in the use of a conventional lead frame form. Therefore, the BGA (Ball Grid Array), the CSP (Chip Scale Package), and the area-mounting type new packaging method such as the chip size package are proposed. The interposer (10) used in the novel package such as CSP is called (4), and the conductor pattern or the conductor post is formed on the filament of the fiber pure towel. The thermal coefficient between the interposer and the wafer The difference is large, and because the interposer is usually larger than the wafer, the area of the portion that is not in contact with the wafer is large. The two parts that are not in contact with the wafer are extremely low, because of the heat between the wafer and the intercalation layer. In the present invention, the term "thermal expansion coefficient" means a length in which the object extends in a range of 30 to 30. The term "rigidity" means the degree of bending of the plate-like substance. 100131022 201230259 m There are two packages (the upper layer seal, the lower layer seal made " the so-called P〇P (Paekage〇nPaekage) structure of the conventional POP structure _|, there will be a lower layer (four) Towel layer due to the aforementioned The thermal expansion between the wafers is prone to occur (4) and the reliability of the electrical connection is reduced. Furthermore, in the package in which the POP is fabricated, the heat of the wafer sandwiched between the interposers cannot be efficiently diverged. In this case, the cause of the above-mentioned problem is also caused. [Provisional Technical Documents] [Patent Document] [Patent Document 1] Japanese Patent Laid-Open Publication No. 2009-81261 (Summary of the Invention) SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package and a semiconductor device capable of preventing occurrence of defects due to heat. (Means for Solving the Problem) This object can be achieved by the present inventions (1) to (25) below. 1) A semiconductor package 'includes a first wiring substrate; a first semiconductor element 'bonded to one of the second wiring substrates; and a reinforcing member bonded to the first wiring substrate by the first half Guide 100131022 5 201230259 The surface of the body element side is not joined to the first semiconductor element, and the thermal expansion coefficient is smaller than the first wiring substrate; the second wiring substrate is relative to The reinforcing member is provided on the opposite side of the first wiring substrate, and is bonded to the first wiring substrate via two or more metal bumps, and the second semiconductor element is bonded to the second wiring substrate and the second wiring substrate. In the surface on the opposite side of the first wiring board, the first semiconductor element is in non-contact with respect to the second wiring substrate. (2) A semiconductor package includes: a first wiring substrate; and a first semiconductor device a reinforcing member that is bonded to a portion of the first wiring substrate that is not joined to the first semiconductor element on a surface of the first semiconductor element and that has a thermal expansion coefficient smaller than the first wiring. a second wiring substrate which is provided on the opposite side of the first wiring substrate from the reinforcing member and joined to the first wiring substrate via two or more metal bumps, and a second semiconductor element. The second semiconductor substrate is bonded to a surface of the second wiring substrate opposite to the first wiring substrate; wherein the first semiconductor element is opposite to the second wiring substrate Touch. (3) A semiconductor package comprising: 100131022 6 201230259 a first wiring substrate; a first semiconductor element bonded to one surface of the first wiring substrate; and a reinforcing member bonded to the first wiring substrate and a surface on the opposite side of the first semiconductor element and having a thermal expansion coefficient smaller than the first wiring substrate; and a second wiring substrate provided on the opposite side of the first wiring substrate from the first semiconductor element, and via 2 One or more metal bumps are bonded to the first wiring substrate; and the second semiconductor element is bonded to a surface of the second wiring substrate opposite to the first wiring substrate; wherein the first semiconductor element pair The second wiring substrate is non-contact. (4) A semiconductor package comprising: a first wiring substrate; a first semiconductor element bonded to one surface of the first wiring substrate; and a reinforcing member bonded to the first wiring substrate and the first semiconductor a surface on the opposite side of the element and having a thermal expansion coefficient smaller than the first wiring substrate; '' the second wiring substrate is provided on the opposite side of the first wiring substrate from the first semiconductor element, and is passed through two or more a metal bump is bonded to the first wiring substrate; and a second semiconductor element is bonded to a surface of the second wiring substrate opposite to the first wiring substrate, wherein the first semiconductor element is paired with the second The wiring substrate is in contact. (100) A semiconductor package comprising: a first wiring substrate; a first semiconductor element bonded to one surface of the first wiring substrate; and a first reinforcing member bonded to the first wiring substrate a portion of the first semiconductor element side that is not bonded to the first semiconductor element, and a thermal expansion coefficient smaller than the first wiring substrate; and a second reinforcing member that is bonded to the first wiring substrate and the first semiconductor element The surface on the opposite side has a thermal expansion coefficient smaller than that of the first wiring substrate, and the second wiring substrate is provided on the opposite side of the first wiring substrate from the first reinforcing member via two or more metal bumps. And the second semiconductor element is bonded to a surface of the second wiring substrate opposite to the first wiring substrate, wherein the first semiconductor element is different from the second wiring substrate contact. (6) A semiconductor package comprising: a first wiring substrate; a first semiconductor element bonded to one of the first wiring substrates; and a first reinforcing member bonded to the first wiring substrate a portion of the first semiconductor element side that is not bonded to the first semiconductor element, and has a thermal expansion coefficient smaller than that of the first wiring substrate; 100131022 8 201230259 a second reinforcing member bonded to the second substrate and the ith semiconductor The surface on the opposite side of the element is smaller than the first wiring substrate, and the second wiring substrate is provided on the opposite side of the first wiring substrate from the first and fourth members, and is provided with two or more metals. a bump is bonded to the first wiring substrate; and a second semiconductor element is bonded to a surface of the second wiring substrate opposite to the first wiring substrate; wherein the first semiconductor element is connected to the first semiconductor device The wiring substrate is in contact. (4) The semiconductor (4) according to (5) or (6), wherein the first reinforcing member is formed to surround a shape surrounding the first semiconductor element. The semiconductor package described in any one of the above-mentioned (1), wherein the distance between the first semiconductor element and the second wiring substrate is 0.01 mm or more and Q 8 mm or less. . (9) The semiconductor package according to any one of (5) to (8), wherein the first reinforcing member is in non-contact with the second wiring substrate: (1) is as described in (6) or (7) above. In the semiconductor package, the upper reinforcing member is in contact with the second wiring substrate. (1) The semiconductor package of (9), wherein a distance between the first reinforcing member and the second wiring substrate is larger than a distance between the first semiconductor element and the second wiring substrate. (12) The semiconductor package according to any one of the above-mentioned items (5) to (1), wherein, in the above-mentioned first reinforcing member, the first reinforcing member is provided so as to be in contact with each of the metal bumps and surround the metal Two or more openings formed by bumps. (13) The semiconductor package according to any one of the above (5), wherein an insulating material is provided between the first reinforcing member and each of the metal bumps. The semiconductor package according to any one of the above-mentioned (1), wherein a difference in thermal expansion coefficient between the first reinforcing member and the second reinforcing member and the first semiconductor element is 7 ppm/ Below °C. The semiconductor package according to any one of the above aspects, wherein the first reinforcing member and the second reinforcing member are each formed in a plate shape. (16) The semiconductor package according to any one of the above (5), wherein the first reinforcing member and the second reinforcing member are each made of a metal material. (17) The semiconductor package according to the above (16), wherein the metal material is an Fe-Ni alloy. (18) A semiconductor device comprising the semiconductor package according to any one of the above (1) to (17). (19) A semiconductor package according to any one of the above (1) to (17), wherein the manufacturing method includes: bonding the first reinforcing member to the first wiring substrate a step of bonding a first semiconductor element to the first wiring substrate to form a lower package; a step of attaching a second semiconductor element to 100131022 10 201230259; and a wiring substrate to form an upper package via two or more metals Bump, the step of joining n. /, upper and lower layer sealing (10) - a semiconductor material material method, to (9), any of the items of the semiconductor sealing device of the above-mentioned (1) the method of bonding the second reinforcing member to the first wiring base includes There is a step of: bonding the second semiconductor 70 to the second wiring substrate by the first semiconductor device (10) (10). The side surface of the first (10) body element (10). The step of bonding the above is performed by encapsulating two or more metal bumps. (1) The method of manufacturing a semiconductor material, the semiconductor package described in any one of (9), and the second package ^0) bonding the first reinforcing member to the first! a step of bonding the second (fourth) member to the second wiring member: a step of forming a lower layer package by the step δ the first semiconductor element on the opposite side of the second wiring member from the second reinforcing member; a step of bonding the second semiconductor element to the second wiring substrate, and a step of bonding the upper package and the lower package to 100131022 201230259 via two or more metal bumps. (22) As described above (19) The method of manufacturing a semiconductor package according to the above aspect, wherein the step of bonding the first reinforcing member to the ith wiring substrate includes: preparing a metal layer and a prepreg (four) layered body, and the laminated body a sub-step of joining the first reinforcing member to the surface of the prepreg; a sub-step of forming a through hole in the prepreg; a sub-step of forming a conductor post in the through hole; and performing a drawing on the metal layer And a sub-step of hardening the prepreg by forming a sub-step of forming a conductor pattern. (23) A semiconductor package as described in any one of the above (19) to (22) a manufacturing method in which the thickness direction is expanded as the metal bumps are cooled, so that the upper layer package is made away from the 42-state wiring substrate and the lower layer (24) as described above (19) (22) The method of the present invention, wherein the upper layer is packaged with a spacer of the semiconductor package, and the spacer is disposed between the upper package and the upper package to form the layer of the upper layer I After the bonding of the package, the first semiconductor element transferred by the package is in a state in which the U 2 wiring substrate and the lower layer are grounded. (25) The method according to any one of (19) to (22) above, wherein And pressing the upper layer seal, the semiconductor package to be mounted, and the lower layer seal to be adjacent to each other in a direction of 100131022 1 ^ 201230259, and pressurizing the second wiring substrate of the upper package and the lower package In the semiconductor package of the present invention, the first wiring substrate is reinforced by the reinforcing member (especially because the reinforcing member is Since the i-semiconductor element is integrated and the first wiring substrate is reinforced, it is possible to prevent or suppress the warpage caused by the difference in thermal expansion coefficient between the first wiring substrate and the first semiconductor element. As a result, the second wiring substrate can be improved. Connection reliability of the metal bumps to be connected to the first wiring board, connection reliability of the metal bumps connecting the first semiconductor element and the first wiring board, and connection of the conductor pattern inside the wiring board. And the connection reliability of the metal bumps that connect the first wiring board and the mother board. Further, according to the semiconductor package of the present invention, when the second semiconductor element and the second wiring substrate are not in contact with each other, the transmission is performed. The gap formed between the first semiconductor element and the second wiring substrate is ventilated, so that the heat of the first semiconductor element can be efficiently dissipated outward. On the other hand, when the first semiconductor element and the second wiring substrate are connected to each other, the first semiconductor element can be efficiently dissipated outward through the second wiring substrate. Further, since the first wiring board is reinforced as described above, it is not necessary to increase the rigidity of the first wiring board itself, and the thickness of the first wiring board can be reduced. Therefore, the thermal conductivity in the thickness direction of the second wiring board can be improved, and it can be derived from 帛! The heat of the semiconductor element is efficiently dissipated outward via the ith wiring substrate. Thus, the semiconductor package system 100131022 13 201230259 of the present invention is excellent in heat dissipation. The above-described semiconductor device according to the present invention is excellent in reliability because it has a conductor package. [Embodiment] Hereinafter, preferred embodiments of the semiconductor sealing device and the semiconductor device of the present invention will be described with reference to the accompanying drawings, but the present invention is not limited to the embodiments. Additions, omissions, substitutions, and other modifications are possible in the constructions without departing from the scope of the invention. <First Embodiment> (Semiconductor Package) First, the semiconductor package of the present invention will be described. 1 is a schematic cross-sectional view of a semiconductor package according to a first embodiment of the present invention, FIG. 2 is a plan view of the semiconductor package shown in FIG. 1, and FIG. 3 is a bottom view of the semiconductor package shown in FIG. An example of a method of manufacturing a semiconductor package shown in FIG. In the following description, for convenience of explanation, the upper side in Fig. 1 is referred to as "upper" and the lower side is referred to as "lower". Further, in Figs. 1 to 4, for the convenience of explanation, the portions of the semiconductor package have an exaggerated description. As shown in FIG. 1 , the semiconductor package i includes a wiring board 2 , a semiconductor element 3 mounted on the wiring board 2 , a second reinforcing member 4 , a second reinforcing member 5 , and a wiring board 301 . The semiconductor element 305 on the wiring board 3〇1 and the 100131022 14 201230259 complex metal bump 400 connecting the wiring board 2 and the wiring board 3〇1. The semiconductor package 1 includes a lower package 500 in which a semiconductor element (first semiconductor element) 3 is mounted on a wiring substrate (first wiring substrate) 2, and a semiconductor element mounted on a wiring substrate (second wiring substrate) 301 ( The second half-conductor. The upper layer package 300 of the body element 3〇5 has an overlapped P0p (package 〇n • Package) structure. In the portion other than the portion where the semiconductor package is bonded to the semiconductor element 3, the wiring board 2 is reinforced by the i-th reinforcing member 4, so that the rigidity of the entire lower package 500 is increased. In particular, since the thermal expansion coefficient of the first reinforcing member 4 is smaller than that of the wiring board 2 (specifically, the substrate 21 to be described later), the wiring board can be suppressed or prevented similarly to the case where the semiconductor element 3 is provided over the entire surface of the wiring board 2 . The wiring substrate 2 is warped due to the difference in thermal expansion coefficient between the semiconductor element 3. Further, as will be described later, since the semiconductor element 3 is not in contact with the wiring board 3〇1, the heat of the semiconductor element 3 can be efficiently directed toward the gap formed between the semiconductor element 3 and the wiring board 3〇1. Divergence outside. Further, since the wiring board 2 is reinforced as described above, it is not necessary to increase the rigidity of the wiring board itself, and the thickness of the wiring board 2 can be thinned. Therefore, the thermal conductivity in the thickness direction of the wiring board 2 can be improved, and the semiconductor element 3 can be obtained. The heat red is diverged by the wiring substrate 2. Thereby, the semiconductor package 1 is excellent in heat dissipation. Further, by appropriately selecting the constituent materials ' of the first reinforcing member 4 and the second reinforcing member 5, the heat dissipation properties of the semiconductor packages can be improved. 100131022 15 201230259

佈線基板2與半導體元件3 亦可有效抑制或防止因The wiring substrate 2 and the semiconductor element 3 can also effectively suppress or prevent the cause

再者，半導體封裝丨中，藉 線基板2與半導體元件3 間之熱膨脹係數差所造成的佈線 ‘上層封裳300與下層封裝Furthermore, in the semiconductor package, the wiring caused by the difference in thermal expansion coefficient between the substrate 2 and the semiconductor element 3 is the upper layer of the package 300 and the lower package.

差。特別因為第2 71間，故可牢ϋ地補強佈線基板2。 ’藉由將第2補強構件5接合於佈 3相反側之面（下面），形成佈線基板 5夾持的狀態，故可更牢 線基板2雙面的熱膨脹 構件係設置為延續至後述金屬凸塊 以下針對半導體封裝丨的各部位依序進行詳細說明。 (下層封裝） 下層封裝（第1封裝)綱係具備有佈線絲2、半導體元 件3、第1補強構件4、及第2補強構件5。 [佈線基板] 佈線基板2係支撐半導體元件3的基板(第1佈線基板）， 例如將其所搭載的半導體元件3與後述母板200間之電氣式 連接予以中繼的中繼基板（中介層）。又，佈線基板2的俯視 形狀通常係設為正方形、長方形等四角形。 佈線基板2係具備有基板21、導體圖案221、222、223、 224、導體柱 231、232、233、234、及導熱柱 24。 另外，本實施形態中，導體圖案221係構成在基板21其 100131022 16 201230259 中 側所3又置的弟1導體圖案，而導體圖案224係構成設 置於基板21另-面側，且電氣式連接於上述第丨導體圖案 的第2導體圖案。 基板21係由複數(本實施形態中為5層）的絕緣層211、 212 213、214、215構成。更具體而言，基板21係依序積 層絕緣層21卜絕緣層212'絕緣層213、絕緣層214、及絕 緣層215而構成。另外’構成基板21的絕緣層數並不僅限 定於此，可為1〜4層，亦可為6層以上。 各絕緣層211、212、213、214、215係由具絕緣性的材料 構成。 具體而言’各絕緣層2U、212、213、214、215係由基材 (纖維基材）、與該基材中所含浸的樹脂組成物構成。 基材係使用作為各絕緣層2U、212、213、、⑴的芯 材。藉由具有此種基材，可提高基板21的剛性。 土材係可舉例如玻璃織布、玻璃不織布等由玻璃纖維構成 ..1玻璃纖維基材；或由以聚醯胺樹脂纖維、芳香族聚酿胺樹 .脂麟、全料族練賴織料飽旨纖維，聚 醋樹脂纖維、芳香族聚_脂纖維、全芳香族聚S旨樹脂纖維 等聚醋系樹脂纖維’聚輕胺樹脂纖維、㈣脂纖維等為主 成分的織布衫織布構叙合成齡基材；或以牛皮紙、棉 短絨紙、短毛纖與牛皮紙漿的混抄紙等為主成分的紙基材 等。邊等之中，該基材較佳係玻璃纖維基材。藉此，可提高 100131022 17 201230259 基板21的剛性，且玎達成基板21的薄型化。且’亦可減小 基板2的熱膨脹係數。 構成此種玻璃纖維基材的玻璃係可舉例如E玻璃、c坡 璃、A玻璃、S玻璃、D玻璃、NE玻璃、T玻璃、Η玻璃等。 該等之中較佳為Τ玻璃。藉此，可降低玻璃纖維基材的熱 膨脹係數，依此可降低基板21的熱膨脹係數。 再者，當絕緣層211、212、213、214、215係含有基材的 情況’絕緣層211、212、213、214、215中的基材含有率分 別較佳係30〜70wt%、更佳係40〜60wt%。藉此，可確實防 止該等絕緣層發生龜裂等破損，且可使各絕緣層的電絕緣性 與熱膨脹係數充分降低。另外，絕緣層211、212、213、 215中之至少丨層可;；j；含有基材’㈣㈣脂組成物構成。 在此種基材中含浸的樹脂組成物係含有樹脂材料。該樹月旨 材料較佳係使用熱硬化性樹脂。 曰 上述熱硬化性树脂係可舉例㈣祕樹脂、甲盼齡 脂、雙酴A祕樹脂等祕㈣樹脂；未改質的_ 脂；經桐油、亞麻仁油、核桃油等改質過的油改質驗播 脂等等的祕型_料轉脂；魏A環氧樹脂、雙齡p 環氧樹脂等雙_輯樹脂；_環氧樹脂、曱㈣ 樹脂等_魏氧則旨；型錢樹脂轉氧樹脂；〇 賴樹脂、脉(尿素)樹月旨、三聚氰胺樹脂等具三倾次 不餘和聚賴脂、雙射烯二醯亞贿脂'«甲^樹 !〇〇131〇22 201230259 脂、鄰苯二甲酸二烯丙輯脂、聚錢 之樹脂、氰酸酿樹脂等。 八本开。亏畊環 該等之中，特佳係氰動旨樹脂。藉此， η的熱膨脹係數。且，基板21的電 二-基板 低介電損耗等）亦較為優異。 “電常數、 組成物較佳係含有填料。即，絕緣層211、 3、214、215分別較佳係含有填料。藉此 2緣層211、212、213、214，的熱膨脹係：条低 謂「填料」係指即便製造步驟中 制 ，所 體狀態之構成上述絕緣層的物質為取終製品時仍保持固 =述填料係可舉勤鐘錢侧^機填料。 孩I機=(無機填充材)係可舉例如二氧一氧化-、碎 二二t鈦、氧化鐵、氧化辞、氧化鎂、金屬肥粒㈣氧 質）、二 氫氧化料氫氧化物；碳_(輕質、重 鎂、白雲石、編8石等碳酸鹽；硫㈣、硫酸 石4叙、亞硫_等硫酸鹽或亞硫酸鹽；滑石、喷母 ::土、破璃纖維，、蒙脫石、膨二 辞、偏，、确呂，讀等爛酸二碳： 二墨、碳纖維等碳；此外尚可舉出鐵粉、铜粉、紹粉、料、 瓜匕鉬、硼纖維、鈦酸鉀、鈦酸锆酸鉛。 再者’有機填料係可舉出合成樹脂粉末。該 100131022 係可舉例如醇酸樹脂、環氧樹脂、聚錢樹脂、物=聚 19 201230259 酉曰、丙烯酸樹脂、縮醛樹脂、聚乙烯、聚醚、聚碳酸酯、聚 醯胺、聚砜、聚苯乙烯、聚氣乙烯系、氟樹脂、聚丙烯、乙 烯-醋酸乙烯酯系共聚物等各種熱硬化性樹脂或熱可塑性樹 脂的粉末、或該等樹脂的共聚物粉末。又，有機填料的其他 例係可舉出芳香族或脂肪族聚醯胺纖維、聚丙烯纖維、聚酯 纖維、芳香族聚醯胺纖維等。 剞述的填料中，較佳係使用無機填料。藉此，可有效地降 低絕緣層211、212、213、214、215的熱膨脹係數。又，亦 可提高絕緣層211、212、213、214、215的導熱性。 尤其，無機填料之中較佳為二氧化矽，從低熱膨脹性優異 的觀點而言，較佳為熔融二氧化矽（特別係球狀熔融二氧化 石夕）。 無機填料的平均粒徑並無特別的限定，較佳係 0.05〜2.0μπι、更佳係〇.1〜i.(^m。藉此，在絕緣層2U、212、 213、214、215中，無機填料可更均勻地分散，俾使絕緣層 21卜212、213、214、215的物理性強度與絕緣性特別優異。 另外，上述無機填料的平均粒徑係可例如利用粒度分佈計 (HORIBA製’ LA-500)進行測定。又，本說明書中，所謂「平 均粒徑」係指體積基準的平均粒徑。 絕緣層21卜212、213、214、215中的無機填充材含有量 为別均無特別的限疋，當將除去基材以外的樹脂組成物設為 lOOwt%時’較佳係30〜80wt%、更佳係45〜75wt%。若含有 100131022 20 ⑧ 201230259 量在上述範圍内，絕緣層211、212、213、214、215便可形 成熱膨脹係數充分低、吸濕性特別低者。 再者’上述樹脂組成物係除了前述熱硬化性樹脂之外，尚 可含有笨氧樹脂、聚醯亞胺樹脂、聚醯胺醯亞胺樹脂、聚苯 醚樹脂、聚醚颯樹脂等熱可塑性樹脂。 再者，上述樹脂組成物視需要亦可含有顏料、抗氧化劑等 上述成分以外的添加物。 再者’絕緣層2U、212、213、214、215係可由互同的材 料構成，亦可由互異的材料構成。 上述之由複數層構成的基板21之平均厚度並無特別的限 定，較佳係30μηι以上且800μηι以下、更佳係30μιη以上且 400μηι 以下。 在此種基板21的絕緣層211與絕緣層212之間介插入導 體圖案221。又’在絕緣層212與絕緣層213之間介插入導 體圖案222。又，在絕緣層213與絕緣層214之間介插入導 體圖案223。又，在絕緣層214與絕緣層215之間介插入導 體圖案224。又，在絕緣層211的上面上設有導體圖案225。 該等導體圖案221、222、223、224、225分別發揮當作具 複數佈線之電路的機能。 導體圖案221、222、223、224、225的構成材料在具有導 電性的前提下，其餘並無特別的限定，可舉例如銅、銅系合 金、铭、鋁系合金等各種金屬及各種合金。其中，該構成材 100131022 21 201230259 料較佳係使用銅及銅系合金。銅及銅系合金的導電率較高。 故，可使佈線基板2的電氣特性呈良好。又，因為銅及銅系 合金的熱傳導性亦優異，故亦可提升佈線基板2的散熱性。 再者’導體圖案221、222、223、224、225的平均厚度並 無特別的限定，較佳係5 μηι以上且3 0 μιη以下。 再者，在絕緣層211中形成貫通其厚度方向的介層洞，並 在該介層洞内設置導體柱（介層柱)231。該導體柱231係在 絕緣層211中貫通其厚度方向，且上端部經由金屬凸塊31 連接於半導體元件3，下端部則連接於導體圖案22卜藉此， 導體圖案221與半導體元件3相導通。另外，所謂「介層洞」 係指用以使絕緣層上方的電路與下方的電路導通之貫通戋 有底的孔。 再者’雖未圖示’在絕緣層211中，使導體圖案221與導 體圖案225導通的導體柱(介層柱)係貫通厚度方向。在導體 圖案225之基板21的上面上’接合複數金屬凸塊々⑼。 該等各金屬凸塊400係執行上層封裝3〇〇與下層封裝 間之電氣式連接(更具體而言’係佈線基板2與佈線基板撕 間之電氣式連接）。又，各金屬凸塊亦具有執行佈線基 板2與佈線基板301間之機械性連接（固定）的機能。 該等複數金屬凸塊40G係沿佈線基板2的外周部隔開間隔 而配置。 本實施形態中 各金屬凸塊400係形成大致球狀。另外， 100131022 22 201230259 各金屬凸塊400的形狀並不僅限定於此。又，各金屬凸塊 400的大小（直徑）係如後述，設定為半導體元件3與佈線基 板301呈非接觸的程度。 再者，金屬凸塊400的構成材料並無特別的限定，可使用 例如錫-錯糸、錫-銀糸、錫-辞糸、錫-絲糸、錫-録糸、錫_ 銀-祕糸、錫-銅糸、錫-銀-銅糸等各種焊料(鲜錫）。 再者，在絕緣層212中設有貫通其厚度方向的導體柱(介 層柱)232。該導體柱232係上端部連接於導體圖案221，且 下端部連接於導體圖案222。藉此，導體圖案221與導體圖 案222相導通。 再者，在絕緣層213中設有貫通其厚度方向的導體柱(介 層柱)233。該導體柱233係上端部連接於導體圖案222，且 下端部連接於導體圖案223。藉此，導體圖案222與導體圖 案223相導通。 再者，在絕緣層214中設有貫通其厚度方向的導體柱(介 層柱)234。該導體柱234係上端部連接於導體圖案223，且 下端部連接於導體圖案224。藉此，導體圖案223與導體圖 案224相導通。 再者，在絕緣層215中設有貫通其厚度方向的複數開口 部，從該等各開口部中露出導體圖案224其中一部分（端 子）。在該導體圖案224所露出的各部分(端子）上接合著金屬 凸塊71。即，在屬於第2導體圖案的導體圖案224與基板 100131022 23 201230259 21相反側的面’接合著複數金屬凸塊71。 該金屬凸塊71細半導體封裝1對例如後述母板進行電 氣式連接。 貫施升八、中，金屬凸塊71係形成大致球狀。另外，4 屬凸塊71的形狀並不僅限定於此。 金屬凸免71的構成材料並無特別的限定，可使用例如韻 錯系、錫·銀系、锡爾、錫褐、錫·錄系、锡务絲系 錫-銅系、錫-銀•鋼系等各種焊料(銲錫）。 再者在基板21中貫通其厚度方向橫跨全域形成複數1 層洞，並在該等各介層洞中設置導熱柱24。 該等各導熱柱24係在基板21整體中貫通其厚度方向，且 上端從基板2丨的上面露出，下端則從基板2ι的下面露出。 導熱柱24係上端接觸到第！補強構件4,下端則接觸到第2 補強構件5。II此’各導熱柱24將第】補強構件4與第2 補強構件5予以相連接。 4等各導餘(熱傳部)24係具有較前述基板21(絕緣層) 更高的導熱性。藉此，可將熱從第丨觸構件4經由導熱柱 24有效率地料給第2補強構件5。結果，可提升半導體封 裝1的散熱性。 再者’因為該等各導熱柱24係在基板21貫通其厚度方 向，故與公知導體柱同樣的可簡單且高精度地形成。 再者，各導熱柱24係可為中空、亦可為實心。又，各導 100131022 24 ⑧ 201230259 熱柱24的橫截面形狀並無特別的限定，可舉例如圓形、橢 圓形、多角形等。又，導熱柱24的數量並無特別的限定， 可為任意，在不致損及佈線基板2的機械強度之程度内’最 好儘可能設置較多數量。 • 再者，各導熱柱24並不參與電氣信號的傳輸。藉此，可 • 將熱從第1補強構件4經由導熱柱24更有效率地傳導給第 2補強構件 本實施形態中，複數導熱柱24係當俯視佈線基板2時， 形成沿佈線基板2的外周部呈相互隔開間隔而並排設置之 狀態。尤其，複數導熱柱24較佳係當俯視佈線基板2時， 形成沿佈線基板2的外周部在周方向上等間隔地並排設 置。藉此，可使佈線基板2的溫度分佈均勻化。 再者，複數導熱柱24係依當俯視佈線基板2時，不會重 疊於前述導體圖案22卜222、223、224、225的方式設置。 藉此，導熱柱24的形成較為簡單，且可防止因導熱柱24 而導致導體圖案22卜222、如、224、225出現短路。 此種各導熱柱24的構成材料係在具有較前述基板叫絕 緣層）更高導熱性的前提下，其餘並無特別的限定，較佳係 使用金屬材料。 =屬材料係可舉例如鋼、銅系合金、！呂、㈣合金等各 種金及各種合金。其巾，該金屬材做導熱 而言’較佳係使用鋼、銅系合金、紹、銘系合金。 100131022 25 201230259 再者’導熱柱24的構成材料可不同於前述導體柱如〜234 的=成材料，但較佳係與導體挺231〜234的構成材 係導體柱234的構成材料)相同。藉此，可在導體柱234 j 成之同=統括地形成導料24。故，可使半導體封裳; 的製造簡單化，且可使半暮 定牛導體封裝1成為低價者。 [半導體元件] ^導體兀件（第1半導體元件）3係例如積體電路元件 該半導體元件3係接二Γ記憶體及受發光元件等。 面(其中-面），並電氣切^述佈線基板2的基板21之上 案22卜 ^式連接於屬於第1導體圖案的導體圖 具體而言，半導 子，且鱗各端切由金1在下面設有未圖㈣複數端 線基板2的導體挺231 “ 4 3卜電氣式連接於前述佈 的導體@案221便％氣式H，半導體元件3與佈線基板2 凸塊71同樣的，体田，， /、則逃贪屬 «、錫-錄系、鱗、:：， 焊料(銲錫）。 、净'、錫-銅系、錫-銀-銅系等各種 再者，半導體元件 基板2的上面。.係經由接著層32,接著(接合)於佈線 該接著層32係由目 例如 -、有接著性與絕緣性的材料構成， 100131022 ⑧ 26 201230259 由填底材的硬化物所構成。 填底材並無特別的限定，可使用公知的填底材，亦可使用 與供形成後述絕緣材81用的銲錫接合用防焊劑相 [第1補強構件] °首° •=補強構件(補強板⑽ff))4係接合於前述佈線基板 2的基板21上面(其巾—面)未接合於半導體元件3之部分 處。 人該^補^件4與基板21係例如可經由接著劑進行接 °稭此’第1補強構件4的設置簡單。 —該接著劑係在具有接著機能的前提下，其餘並無特別的限 疋’可使用各種接著劑，較佳係熱傳導性優異者，可使用與 後述熱傳導性材料6同樣者。 ’ 該第1補強構件4係熱義係數小於基板2卜藉此，可 抑制基板21的熱膨脹。 9 再者，第1補強構件4係形成板狀。藉此，可使第！補強 構件4的構造較為簡單且小型。 _ 本實施形態中，第1補強構件4與基板21相反側的面（即 上面)係和與半導體元件3之基板η相反側的面（即上面)位 於同一面。藉此，可使半導體封裝i薄型化，且可有效地抑 制或防止佈線基板2的翹曲。又’當在第！補強構件4的上 面設置上層封裝300的佈線基板3〇1時，可安定地執行其設 置。又，製造半導體封们之際，當在第1補強構件4設置 100131022 27 201230259 後才設置半導體元件3時，可使半導體元件3的設置較為容 易。 再者，第1補強構件4係形成為包圍半導體元件3周圍的 形狀。本實施形態中，第1補強構件4係依包圍半導體元件 3的方式形成環狀（更具體而言係四角環狀）。藉此，可增加 第1補強構件4與半導體元件3的一體性，可使利用第1 補強構件4提高佈線基板2之剛性的效果更為優異。 再者，如圖2所示，在第1補強構件4中形成貫通其厚度 方向的複數開口部42。在該等各|開口部42内配置前述金屬 凸塊400。 1 本實施形態中，各開口部42係分別對各金屬凸塊400 — 對一地對應設置。各開口部42係依對各金屬凸塊400呈非 接觸且包圍各金屬凸塊400的方式形成。依此，藉由在開口 部42内配置金屬凸塊400，可容許經由複數金屬凸塊400 進行的佈線基板2與佈線基板301間之接合，且可增加第1 補強構件4的俯視面積。 再者，如圖2所示，在第1補強構件4與各金屬凸塊400 之間（開口部42的壁面與金屬凸塊400之間）設有絕緣材 401。藉此，即便第1補強構件4具有導電性的情況，仍可 防止金屬凸塊400彼此間發生短路。藉由將絕緣材401填充 於第1補強構件4與各金屬凸塊400之間，可增加第1補強 構件4與各金屬凸塊400的一體性，並可提高第1補強構件 100131022 28 201230259 4與各金屬凸塊間之熱傳導性。 再者、·、邑緣材401係形成包圍金屬凸塊4〇〇基板21側之 4刀（下糊圍的形狀’且接合於各金屬凸塊糊。藉此， 絕緣材401補強金屬凸塊4〇〇。 再者，絕緣材401較佳係具有高於前述佈線基板2之基板 21的熱傳導性。藉此，可使金屬凸塊與第μ強構件* 間之熱傳導性呈優異，俾可提升半導體封裝丨的散熱性。 、此種絕緣材401係具有絕緣性，且含有樹脂材料而構成， 並無特別的限定，但與後述絕緣材81同樣的，較佳係例如 由具熱硬化性的㈣接合用樹輯形成者。 、再者，第Μ強構件4係依與各金屬凸塊彻間之距離(俯 、τ 1 .M2的壁面與金屬凸塊4〇〇的外周面間之距離) 橫跨金屬凸塊全周呈—定的方式而形成。藉此，可增加 Ρ補強構件4與各金屬凸塊4〇〇的一體性，俾適當發揮由 該等產生的佈線基板2之補強效果。 再者’第1補強構件4係依與半導體元件3間之距離（第 1補強構件4的内周面41與半導體元件3的外周面33間之 距離)橫跨半導體元件3全 ^ Π呈一疋的方式形成。藉此，增 加第1補強構件4與半導體元件3的-體性，可適當地發揮 利用料產生的佈線基板2之補強效果。又，可有效率且均 勻地產生經由後述熱傳導性材料6從半導體 補強構件的導熱。 ^ 100131022 29 201230259 再者，第1補強構件4較佳係鱼 于^、+導體元件3間之熱 係數差在7ppm/°C以下。藉此，半| ' 導體凡件3與第1補強構 件4可一體地補強佈線基板2， 並可抑制下層封裝500整研 的熱膨脹。 版 再者’第1補強構件4的構成 再成材枓在具有如前述般之熱膨 脹係數的前提下’其餘並無特別 符別的限定，可使用例如金屬材 料、陶瓷材料等，但較佳係使用全眉 μ 文用i屬材枓。若第1補強構件 4係由金屬材料構成，則可提高第1補強構件4的散熱性。 結果，可提升下層封裝5〇〇的散熱性。 該金屬材料在具有如前述的熱膨脹係數之前提下，1餘並 無特別的限定，可使用各種域㈣，從實現賴性與低熱 膨脹的觀點而言，較佳係使用含&的合金。 該含Fe的合金係可舉例如純系^金、Fe_c〇 Cr “ 金、Fe-Co系合金、Fe>vPt糸入么 ° 糸合金,、Fe-Pd合金等，特別較佳 係使用Fe-Ni系合金。 此種金屬材料不僅散熱性優異，且熱膨服係數低，並 接近-般半導體元件3之熱膨脹係數的熱膨服係數。故，、 導體元件3與第1補強構件4可—體性地補強佈線基板2。difference. In particular, because of the 2nd 71th, the wiring board 2 can be reinforced. 'The second reinforcing member 5 is joined to the surface (the lower surface) on the opposite side of the cloth 3 to form a state in which the wiring board 5 is sandwiched. Therefore, the thermal expansion member on both sides of the substrate 2 can be further extended to the metal protrusion described later. The following sections of the semiconductor package package are described in detail below. (Lower Package) The lower package (first package) includes a wiring wire 2, a semiconductor element 3, a first reinforcing member 4, and a second reinforcing member 5. [Cable Substrate] The wiring board 2 is a substrate (first wiring board) that supports the semiconductor element 3, and is, for example, an interposer that relays the electrical connection between the semiconductor element 3 mounted thereon and the motherboard 200 to be described later. ). Further, the planar shape of the wiring board 2 is generally a square shape such as a square or a rectangle. The wiring board 2 includes a substrate 21, conductor patterns 221, 222, 223, and 224, conductor posts 231, 232, 233, and 234, and a heat transfer column 24. Further, in the present embodiment, the conductor pattern 221 is formed on the substrate 21 in the middle of the 100131022 16 201230259 side, and the conductor pattern 224 is formed on the other side of the substrate 21, and is electrically connected. a second conductor pattern of the second conductor pattern. The substrate 21 is composed of a plurality of insulating layers 211, 212 213, 214, and 215 (in the present embodiment, five layers). More specifically, the substrate 21 is formed by sequentially laminating the insulating layer 21, the insulating layer 212' insulating layer 213, the insulating layer 214, and the insulating layer 215. Further, the number of insulating layers constituting the substrate 21 is not limited thereto, and may be 1 to 4 layers or 6 or more layers. Each of the insulating layers 211, 212, 213, 214, and 215 is made of an insulating material. Specifically, each of the insulating layers 2U, 212, 213, 214, and 215 is composed of a substrate (fiber substrate) and a resin composition impregnated in the substrate. As the substrate, a core material as the insulating layers 2U, 212, 213, and (1) was used. By having such a substrate, the rigidity of the substrate 21 can be improved. The soil material may be made of glass fiber, such as glass woven fabric or glass non-woven fabric, or a glass fiber substrate. Weaving fiber, polyester fiber, aromatic poly-lipid fiber, wholly aromatic poly-S resin fiber, such as polyester resin fiber, poly-light amine resin fiber, (4) fat fiber, etc. A synthetic base material; or a paper substrate mainly composed of kraft paper, cotton linter paper, mixed paper of short-wool fiber and kraft pulp, and the like. The substrate is preferably a glass fiber substrate. Thereby, the rigidity of the substrate 21 of 100131022 17 201230259 can be improved, and the thickness of the substrate 21 can be reduced. And the thermal expansion coefficient of the substrate 2 can also be reduced. Examples of the glass constituting the glass fiber base material include E glass, c glass, A glass, S glass, D glass, NE glass, T glass, and bismuth glass. Among these, bismuth glass is preferred. Thereby, the coefficient of thermal expansion of the glass fiber substrate can be lowered, whereby the coefficient of thermal expansion of the substrate 21 can be lowered. Further, in the case where the insulating layers 211, 212, 213, 214, and 215 contain a substrate, the substrate contents in the insulating layers 211, 212, 213, 214, and 215 are preferably 30 to 70% by weight, respectively. 40 to 60 wt%. Thereby, it is possible to surely prevent the insulating layers from being damaged by cracks or the like, and to sufficiently reduce the electrical insulating properties and thermal expansion coefficients of the respective insulating layers. Further, at least one of the insulating layers 211, 212, 213, and 215 may be formed of a base composition of the substrate (4) and (4). The resin composition impregnated in such a substrate contains a resin material. It is preferable to use a thermosetting resin as the material of the tree.曰 The above thermosetting resin system can be exemplified by (4) secret resin, acetaminophen, bismuth A secret resin and the like (four) resin; unmodified _ fat; modified oil such as tung oil, linseed oil, walnut oil, etc. The secret type of the modified test fat, etc. _ material transesterification; Wei A epoxy resin, double age p epoxy resin and other double _ series resin; _ epoxy resin, bismuth (four) resin, etc. Resin-transfer resin; Resin resin, vein (urea) tree, melamine resin, etc. with three times of dip and polylysate, double-shot enephite bribe grease '«甲^树!〇〇131〇22 201230259 Grease, diallyl phthalate, poly-resin, cyanate resin, etc. Eight copies open. Deficient tillage ring Among these, the special best is cyanide resin. Thereby, the coefficient of thermal expansion of η. Further, the electric two-substrate of the substrate 21 has a low dielectric loss and the like. The electric constant and the composition preferably contain a filler. That is, the insulating layers 211, 3, 214, and 215 each preferably contain a filler. The thermal expansion system of the two edge layers 211, 212, 213, and 214 is low. "Filler" means that even if the material constituting the above-mentioned insulating layer in the state of the body is made in the manufacturing step, the material is kept solid when the final product is used. The child I machine = (inorganic filler) may be, for example, dioxo-oxidized-, crushed di-t-t-titanium, iron oxide, oxidized, magnesium oxide, metal fertilizer (tetra) oxyhydroxide, hydroxide hydroxide; Carbon _ (light, heavy magnesium, dolomite, 8 stone and other carbonates; sulfur (four), sulphate 4, sulphur _ and other sulphates or sulfites; talc, spray:: soil, broken glass, , montmorillonite, swelling two words, partial, correct Lu, read and other rotten acid two carbon: two ink, carbon fiber and other carbon; in addition, iron powder, copper powder, Shao powder, material, melon, molybdenum, boron The fiber, the potassium titanate, and the lead zirconate titanate. The organic filler is a synthetic resin powder. The 100131022 is, for example, an alkyd resin, an epoxy resin, a polyphenol resin, or a product = poly 19 201230259 酉曰, acrylic resin, acetal resin, polyethylene, polyether, polycarbonate, polyamide, polysulfone, polystyrene, polystyrene, fluororesin, polypropylene, ethylene-vinyl acetate copolymer, etc. a powder of a thermosetting resin or a thermoplastic resin, or a copolymer powder of the resins. Further, other organic fillers Examples thereof include aromatic or aliphatic polyamine fibers, polypropylene fibers, polyester fibers, and aromatic polyamide fibers. Among the fillers described above, inorganic fillers are preferably used. The thermal expansion coefficients of the insulating layers 211, 212, 213, 214, and 215. Further, the thermal conductivity of the insulating layers 211, 212, 213, 214, and 215 can be improved. In particular, among the inorganic fillers, cerium oxide is preferred, from low. From the viewpoint of excellent thermal expansion property, molten cerium oxide (especially spherical molten sulphur dioxide) is preferable. The average particle diameter of the inorganic filler is not particularly limited, but is preferably 0.05 to 2.0 μm, and more preferably 〇.1~i.(^m. Thereby, in the insulating layers 2U, 212, 213, 214, 215, the inorganic filler can be more uniformly dispersed, so that the physical properties of the insulating layer 21, 212, 213, 214, 215 The average particle diameter of the inorganic filler can be measured, for example, by a particle size distribution meter ("LA-500" manufactured by HORIBA). In the present specification, the "average particle diameter" means a volume. The average particle size of the reference. Insulation layer 21 212, 213, The content of the inorganic filler in 214 and 215 is not particularly limited. When the resin composition other than the substrate is set to 100% by weight, it is preferably 30 to 80% by weight, more preferably 45 to 75% by weight. If the amount of 100131022 20 8 201230259 is within the above range, the insulating layers 211, 212, 213, 214, and 215 can form a coefficient of thermal expansion which is sufficiently low and particularly low in hygroscopicity. Further, the above resin composition is in addition to the aforementioned heat. In addition to the curable resin, a thermoplastic resin such as a stearoxy resin, a polyimide resin, a polyamidoximine resin, a polyphenylene ether resin, or a polyether oxime resin may be contained. Further, the resin composition may contain additives other than the above components such as a pigment and an antioxidant as needed. Further, the 'insulating layers 2U, 212, 213, 214, and 215 may be composed of mutually similar materials or may be composed of mutually different materials. The average thickness of the substrate 21 composed of the plurality of layers described above is not particularly limited, but is preferably 30 μm or more and 800 μm or less, more preferably 30 μm or more and 400 μm or less. A conductor pattern 221 is interposed between the insulating layer 211 of the substrate 21 and the insulating layer 212. Further, a conductor pattern 222 is interposed between the insulating layer 212 and the insulating layer 213. Further, a conductor pattern 223 is interposed between the insulating layer 213 and the insulating layer 214. Further, a conductor pattern 224 is interposed between the insulating layer 214 and the insulating layer 215. Further, a conductor pattern 225 is provided on the upper surface of the insulating layer 211. The conductor patterns 221, 222, 223, 224, and 225 function as circuits having a plurality of wirings, respectively. The constituent materials of the conductor patterns 221, 222, 223, 224, and 225 are not particularly limited as long as they have electrical conductivity, and various metals such as copper, copper alloy, aluminum alloy, and various alloys, and various alloys are exemplified. Among them, the material 100131022 21 201230259 is preferably made of copper or a copper alloy. Copper and copper alloys have higher electrical conductivity. Therefore, the electrical characteristics of the wiring board 2 can be made good. Further, since the copper and the copper-based alloy are excellent in thermal conductivity, the heat dissipation property of the wiring board 2 can also be improved. Further, the average thickness of the conductor patterns 221, 222, 223, 224, and 225 is not particularly limited, but is preferably 5 μη or more and 30 μm or less. Further, a via hole penetrating in the thickness direction is formed in the insulating layer 211, and a conductor post (via pillar) 231 is provided in the via hole. The conductor post 231 penetrates the thickness direction of the insulating layer 211, and the upper end portion is connected to the semiconductor element 3 via the metal bump 31, and the lower end portion is connected to the conductor pattern 22, whereby the conductor pattern 221 is electrically connected to the semiconductor element 3. . In addition, the term "via" means a hole through which the circuit above the insulating layer is electrically connected to the underlying circuit. Further, although not shown in the insulating layer 211, the conductor post (via pillar) that conducts the conductor pattern 221 and the conductor pattern 225 penetrates the thickness direction. A plurality of metal bumps (9) are joined on the upper surface of the substrate 21 of the conductor pattern 225. Each of the metal bumps 400 performs an electrical connection between the upper package 3A and the lower package (more specifically, the electrical connection between the wiring substrate 2 and the wiring substrate tear). Further, each of the metal bumps also has a function of performing mechanical connection (fixing) between the wiring board 2 and the wiring board 301. The plurality of metal bumps 40G are arranged at intervals along the outer peripheral portion of the wiring board 2. In the present embodiment, each of the metal bumps 400 is formed in a substantially spherical shape. In addition, the shape of each metal bump 400 of 100131022 22 201230259 is not limited to this. Further, the size (diameter) of each of the metal bumps 400 is set to such an extent that the semiconductor element 3 and the wiring board 301 are not in contact with each other as will be described later. Further, the constituent material of the metal bump 400 is not particularly limited, and for example, tin-mole, tin-silver, tin-rhodium, tin-silk, tin-recording, tin-silver-secret, Various solders (fresh tin) such as tin-copper, tin-silver-copper. Further, a conductor post (via pillar) 232 penetrating the thickness direction thereof is provided in the insulating layer 212. The conductor post 232 has an upper end connected to the conductor pattern 221 and a lower end connected to the conductor pattern 222. Thereby, the conductor pattern 221 is electrically connected to the conductor pattern 222. Further, a conductor post (via column) 233 penetrating the thickness direction thereof is provided in the insulating layer 213. The conductor post 233 has an upper end connected to the conductor pattern 222 and a lower end connected to the conductor pattern 223. Thereby, the conductor pattern 222 is electrically connected to the conductor pattern 223. Further, a conductor post (via column) 234 penetrating the thickness direction thereof is provided in the insulating layer 214. The conductor post 234 has an upper end connected to the conductor pattern 223 and a lower end connected to the conductor pattern 224. Thereby, the conductor pattern 223 is electrically connected to the conductor pattern 224. Further, the insulating layer 215 is provided with a plurality of openings extending in the thickness direction thereof, and a part (terminal) of the conductor patterns 224 is exposed from the respective openings. Metal bumps 71 are bonded to the respective portions (terminals) exposed by the conductor pattern 224. That is, the plurality of metal bumps 71 are bonded to the surface of the conductor pattern 224 belonging to the second conductor pattern on the opposite side to the substrate 100131022 23 201230259 21 . The metal bump 71 thin semiconductor package 1 is electrically connected to, for example, a mother board which will be described later. The metal bumps 71 are formed in a substantially spherical shape. In addition, the shape of the four-genus bump 71 is not limited to this. The constituent material of the metal bump 71 is not particularly limited, and for example, rhythm, tin, silver, tin, tin, tin, tin, tin, tin, copper, tin, silver, steel can be used. Various solders (solders). Further, a plurality of holes are formed across the entire region in the thickness direction of the substrate 21, and heat transfer columns 24 are provided in the respective via holes. Each of the heat transfer columns 24 penetrates the thickness direction of the entire substrate 21, and the upper end is exposed from the upper surface of the substrate 2, and the lower end is exposed from the lower surface of the substrate 2i. The upper end of the heat-conducting column 24 is in contact with the first! The reinforcing member 4 is in contact with the second reinforcing member 5 at the lower end. II. Each of the heat transfer columns 24 connects the first reinforcing member 4 and the second reinforcing member 5. Each of the four guides (heat transfer portions) 24 has a higher thermal conductivity than the substrate 21 (insulating layer). Thereby, heat can be efficiently supplied from the first contact member 4 to the second reinforcing member 5 via the heat transfer column 24. As a result, the heat dissipation of the semiconductor package 1 can be improved. Furthermore, since each of the heat transfer columns 24 penetrates the thickness direction of the substrate 21, it can be formed simply and accurately similarly to the known conductor posts. Furthermore, each of the heat conducting columns 24 can be hollow or solid. Further, each of the guides 100131022 24 8 201230259 has a cross-sectional shape of the heat column 24, and is not particularly limited, and examples thereof include a circular shape, an elliptical shape, and a polygonal shape. Further, the number of the heat transfer columns 24 is not particularly limited, and may be arbitrarily set to a maximum amount as much as possible without impairing the mechanical strength of the wiring board 2. • Again, each thermally conductive column 24 does not participate in the transmission of electrical signals. Thereby, heat can be more efficiently transmitted from the first reinforcing member 4 to the second reinforcing member via the heat transfer column 24. In the present embodiment, the plurality of heat transfer columns 24 are formed along the wiring substrate 2 when the wiring substrate 2 is viewed in plan. The outer peripheral portions are in a state of being arranged side by side at intervals. In particular, the plurality of thermally conductive columns 24 are preferably arranged side by side at equal intervals in the circumferential direction along the outer peripheral portion of the wiring substrate 2 when the wiring board 2 is viewed in plan. Thereby, the temperature distribution of the wiring substrate 2 can be made uniform. Further, the plurality of thermally conductive columns 24 are disposed so as not to overlap the conductor patterns 22, 222, 224, 224, and 225 when the wiring board 2 is viewed in plan. Thereby, the formation of the heat conducting column 24 is relatively simple, and the short circuit of the conductor patterns 22, 222, 224, 225 due to the heat conducting columns 24 can be prevented. The constituent material of each of the heat transfer columns 24 is not particularly limited as long as it has higher thermal conductivity than the substrate, and it is preferable to use a metal material. = The material is a steel, a copper alloy, for example! Lu, (4) alloys and other kinds of gold and various alloys. In the case of the towel, the metal material is preferably made of steel, a copper alloy, or a alloy. 100131022 25 201230259 Further, the constituent material of the heat-conducting column 24 may be different from the conductor material of the conductor post such as 234, but is preferably the same as the constituent material of the constituent conductor post 234 of the conductor strips 231 to 234. Thereby, the guide 24 can be formed in the same manner as the conductor post 234j. Therefore, the manufacture of the semiconductor package can be simplified, and the semiconductor package 1 can be made low. [Semiconductor Element] ^ Conductor element (first semiconductor element) 3 is, for example, an integrated circuit element. The semiconductor element 3 is connected to a memory and a light-receiving element. The surface (the - surface) and the substrate 21 on the wiring substrate 2 are electrically connected to the conductor pattern belonging to the first conductor pattern, specifically, the semiconductor, and the ends of the scale are cut by gold. 1 is provided with a conductor 231 which is not shown in the figure (4) of the plurality of end-line substrates 2, and is electrically connected to the conductor of the cloth, and the second element is H, and the semiconductor element 3 is the same as the bump 71 of the wiring board 2. , body,, /, is greedy genus «, tin - recorded, scale, ::: solder (solder)., net ', tin-copper, tin-silver-copper, etc., semiconductor components The upper surface of the substrate 2 is formed by the bonding layer 32 and then bonded (bonded) to the wiring. The bonding layer 32 is made of a material such as, for example, an adhesive and an insulating material, and 100131022 8 26 201230259 is made of a cured material filled with a substrate. The substrate to be filled is not particularly limited, and a well-known substrate may be used, or a solder joint for solder bonding for forming an insulating material 81 to be described later may be used. [First reinforcing member] ° first == reinforcing member (reinforcing plate (10) ff)) 4 is bonded to the upper surface of the substrate 21 of the wiring board 2 (the towel-surface thereof) is not bonded to the semiconductor The portion of the component 3 and the substrate 21 are, for example, connectable via an adhesive, and the arrangement of the first reinforcing member 4 is simple. The adhesive is provided with an adhesive function. There is no particular limitation to the rest. Various adhesives can be used, and those having excellent thermal conductivity are preferably used in the same manner as the thermally conductive material 6 described later. The first reinforcing member 4 has a lower thermal coefficient than the substrate 2 Further, the thermal expansion of the substrate 21 can be suppressed. Further, the first reinforcing member 4 is formed in a plate shape. Thereby, the structure of the first reinforcing member 4 can be made simple and small. In the present embodiment, the first reinforcing member 4 is used. The surface on the opposite side to the substrate 21 (i.e., the upper surface) is on the same side as the surface on the opposite side to the substrate η of the semiconductor element 3 (i.e., the upper surface). Thereby, the semiconductor package i can be made thinner and can be effectively suppressed or prevented. The warpage of the wiring substrate 2. Further, when the wiring substrate 3〇1 of the upper package 300 is placed on the upper surface of the first reinforcing member 4, the setting thereof can be stably performed. Further, when the semiconductor package is manufactured, at the time of the first Reinforcement member 4 set 10013102 2 27 201230259 When the semiconductor element 3 is provided, the semiconductor element 3 can be easily disposed. Further, the first reinforcing member 4 is formed to surround the periphery of the semiconductor element 3. In the present embodiment, the first reinforcing member 4 is formed. The annular shape (more specifically, the four-corner annular shape) is formed so as to surround the semiconductor element 3. Thereby, the integrity of the first reinforcing member 4 and the semiconductor element 3 can be increased, and the wiring can be improved by the first reinforcing member 4. Further, the effect of the rigidity of the substrate 2 is further improved. Further, as shown in Fig. 2, a plurality of openings 42 penetrating in the thickness direction are formed in the first reinforcing member 4. The metal protrusions are disposed in the respective opening portions 42. Block 400. In the present embodiment, each of the openings 42 is provided correspondingly to each of the metal bumps 400. Each of the openings 42 is formed so as not to be in contact with each of the metal bumps 400 and to surround each of the metal bumps 400. As a result, by arranging the metal bumps 400 in the opening portion 42, the bonding between the wiring substrate 2 and the wiring substrate 301 via the plurality of metal bumps 400 can be accommodated, and the plan view area of the first reinforcing member 4 can be increased. Further, as shown in Fig. 2, an insulating material 401 is provided between the first reinforcing member 4 and each of the metal bumps 400 (between the wall surface of the opening 42 and the metal bump 400). Thereby, even if the first reinforcing member 4 has conductivity, it is possible to prevent the metal bumps 400 from being short-circuited with each other. By filling the insulating material 401 between the first reinforcing member 4 and each of the metal bumps 400, the integrity of the first reinforcing member 4 and each of the metal bumps 400 can be increased, and the first reinforcing member can be improved. 100131022 28 201230259 4 Thermal conductivity with each metal bump. Further, the edge material 401 is formed by forming four knives (the shape of the lower paste rim) on the side of the metal bump 4 〇〇 substrate 21 and bonded to each of the metal bump pastes. Thereby, the insulating material 401 reinforced the metal bumps Further, the insulating material 401 preferably has thermal conductivity higher than that of the substrate 21 of the wiring board 2. Thereby, the thermal conductivity between the metal bump and the first strong member * can be excellent. The heat dissipation of the semiconductor package is improved. The insulating material 401 is not particularly limited as long as it has insulating properties and contains a resin material. However, it is preferably thermosetting, for example, similar to the insulating material 81 described later. (4) The joint is formed by the tree. Further, the first weak member 4 is closely spaced from each of the metal bumps (between the wall surface of the Φ1.M2 and the outer peripheral surface of the metal bump 4〇〇) The distance is formed so as to extend over the entire circumference of the metal bumps. Thereby, the integrity of the crucible reinforcing member 4 and each of the metal bumps 4〇〇 can be increased, and the wiring board 2 produced by the above can be appropriately exhibited. Reinforcement effect. Further, 'the first reinforcing member 4 is based on the distance from the semiconductor element 3. The distance between the inner circumferential surface 41 of the first reinforcing member 4 and the outer circumferential surface 33 of the semiconductor element 3 is formed so as to be uniform across the semiconductor element 3. Thereby, the first reinforcing member 4 and the semiconductor element 3 are added. In addition, the reinforcing effect of the wiring board 2 by the use of the material can be appropriately exhibited. Further, heat conduction from the semiconductor reinforcing member via the thermal conductive material 6 to be described later can be efficiently and uniformly generated. ^ 100131022 29 201230259 Furthermore, the first The reinforcing member 4 preferably has a thermal coefficient difference of less than 7 ppm/° C. between the + and + conductor elements 3. Thereby, the semi-conductor member 3 and the first reinforcing member 4 can integrally reinforce the wiring substrate 2, Further, it is possible to suppress thermal expansion of the underlying package 500. The composition of the first reinforcing member 4 is re-formed under the premise of having the thermal expansion coefficient as described above, and the rest is not particularly limited, and for example, metal can be used. For the material, the ceramic material, or the like, it is preferable to use the full-brimmed material i. The first reinforcing member 4 is made of a metal material, so that the heat dissipation property of the first reinforcing member 4 can be improved. Package 5 Heat dissipation of the crucible. The metal material is provided before having the thermal expansion coefficient as described above, and the remaining one is not particularly limited, and various domains (4) can be used. From the viewpoint of realizing the dependence and low thermal expansion, it is preferred to use Alloy containing & The Fe-containing alloy may, for example, be pure gold, Fe_c〇Cr "gold, Fe-Co alloy, Fe> vPt enthalpy alloy, Fe-Pd alloy, etc. The Fe-Ni alloy is preferably used. This metal material is excellent in heat dissipation and low in thermal expansion coefficient, and is close to the thermal expansion coefficient of the thermal expansion coefficient of the semiconductor element 3. Therefore, the conductor element 3 and the first one are The reinforcing member 4 can physically reinforce the wiring substrate 2.

Fe-Ni系合金在含有&及奶之前提下，其餘並無特別的 限定’除了 Fe與Ni之外，其餘部分(M)亦可含有c〇、Ti 々、^等金屬中之旧或^以上的金屬。 更具體而言’ Fe,系合金係可舉例如^•遍合金（因 100131022 201230259 瓦，invar)等Fe-Ni合金、Fe-32Ni-5Co合金（超因瓦，The Fe-Ni alloy is removed before the inclusion of & and milk, and the rest is not particularly limited. In addition to Fe and Ni, the remaining portion (M) may also contain old metals such as c〇, Ti 々, and ^ Above the metal. More specifically, the Fe alloy system may, for example, be an Fe-Ni alloy such as an alloy (100131022 201230259 watt, invar) or an Fe-32Ni-5Co alloy (Super Invar,

Super-Invar)、Fe-29Ni-17Co 合金(Kovar)、Fe-36Ni-12Co 合 金（艾林瓦，Elinvar)等 Fe-Ni-Co 合金、Fe-Ni-Cr-Ti 合金、 Ni-28Mo-2Fe 合金等 Ni-Mo-Fe 合金等。又，Fe-Ni-Co 合金 已有依例如 KV_2、KV-4、KV-6、KV-15、KV-25 等 KV 系 列(NEOMAX材料公司製）、Nivarox等商品名市售。又，Fe-Ni 合金已有依例如NS-5、D-l(NEOMAX材料公司製）等商品 名市售。又，Fe-Ni-Cr-Ti合金已有依例如Ni-Span C-902(Daido-Special Metals 公司製）、EL-3(NE〇MAX 材料 公司製）等商品名市售。 再者’ Fe-Co-Cr系合金在含有Fe、Co及Cr的前提下， 其餘並無特別的限定，可舉例如Fe-54Co-9.5Cr(不銹鋼因瓦) 等Fe_C〇-Cr合金。另外，Fe-Co-Cr系合金除了 Fe、c〇及 Cr之外，尚可含有]sfi、Ti、Mo、Pd、Pt等金屬中之i種或 2種以上的金屬。 再者’ Fe-Co系合金在含有Fe及Co的前提下，其餘並無 特別的限定’除了 Fe及C〇之外，尚可含有Ni、Ti、Mo、 Cr、Pd、Pt等金屬中之1種或2種以上的金屬。 再者，Fe-Pt系合金在含有Fe及Pt的前提下，其餘並無 特別的限定’除了 Fe及Pt之外，尚可含有C〇、Ni、Ti、 Mo、Cr、Pd等金屬中之！種或2種以上的金屬。 再者，Fe-Pd系合金在含有！^及Pd的前提下，其餘並無 100131022 31 201230259 特別的限定，除了 Fe及Pd之外，尚可含有an Mo、Cr、Pt等金屬中之！種或2種以上的金屬。 特別’第1補強構件4的熱膨脹係數較佳係〇 5ppm/t以 上且10PPm/t以下、更佳係lppm/t以上且7卯4以下、 特佳係Ippmrc以上且5_/。〇以下。藉此，可縮小半導體 7G件3與第1補強構件4間之熱祕係數差，料可一體地 補強佈線基板2。故，可有效果地防止佈線基板2發生輕曲 情形。 再者’第1補強構件4與半導體元件3之熱雜係數差的 絕對值’較佳係7ppm/°C以下、更佳係5ppm/°c以下、特佳 係2ppm/°C以下。藉此，可縮小半導體元件3與第i補強構 件4間之熱膨脹係數差，該等可一體地補強佈線基板2。故， 可有效果地防止佈線基板2發生趣曲情形。 從上述熱膨脹係數的觀點而言，當構成第1補強構件4 的金屬材料係Fe-Ni系合金之情況，上述Fe-Ni系合金較佳 係Ni含有量為3〇wt%以上且50wt%以下、更佳的Ni含有 量為35wt%以上且45wt%以下。藉此，可使第1補強構件4 的熱膨脹係數接近半導體元件3的熱膨脹係數。此情況，上 述Fe-Ni系合金較佳係^含有量為5〇wt%以上且70wt%以 下、更佳係Fe含有量為55wt°/〇以上且65wt%以下。 再者’當構成第1補強構件4的金屬材料係Fe-Ni系合金 的情況，上述Fe-Ni系合金較佳係Fe與Ni的合計含有量為 100131022 ⑧ 201230259 85wt%以上且i〇〇wt%以下、更佳係Fe與Ni的合計含有量 為90wt°/〇以上且l〇〇wt%以下。即’上述Fe_Ni系合金較佳 係其餘部分(M)的含有量為〇wt%以上且i5wt%以下、更佳 係其餘部分(M)的含有量為〇wt%以上且1〇wt%以下。藉此， 可使第1補強構件4的熱膨脹係數接近半導體元件3的熱膨 脹係數。 再者’第1補強構件4的平均厚度係依照佈線基板2的熱 衫脹係數、佈線基板2的第1補強構件4與第2補強構件5 之形狀、大小、構成材料等而決定，並無特別的限定，例如 為0.02mm以上且0.8mm以下左右。另外’本實施形態中， 第1補強構件4的厚度係呈均勻，但亦可具有厚度不同的部 分。例如亦可使厚度從第i補強構件4的内側朝外側呈連續 件4與半導體元件3之問仫吉亡立# μ ....... ’如圖1與圖2所示，在第1補強構Super-Invar), Fe-29Ni-17Co alloy (Kovar), Fe-36Ni-12Co alloy (Elinvar), Fe-Ni-Co alloy, Fe-Ni-Cr-Ti alloy, Ni-28Mo-2Fe Ni-Mo-Fe alloy such as alloy. Further, Fe-Ni-Co alloys are commercially available under the trade names of KV series (manufactured by NEOMAX Materials Co., Ltd.) such as KV_2, KV-4, KV-6, KV-15, and KV-25, and Nivarox. Further, Fe-Ni alloys are commercially available under the trade names of NS-5 and D-1 (manufactured by NEOMAX Materials Co., Ltd.). Further, the Fe-Ni-Cr-Ti alloy is commercially available under the trade names of, for example, Ni-Span C-902 (manufactured by Daido-Special Metals Co., Ltd.) and EL-3 (manufactured by NE〇MAX Materials Co., Ltd.). Further, the Fe-Co-Cr alloy is not particularly limited as long as it contains Fe, Co, and Cr, and examples thereof include Fe-C〇-Cr alloy such as Fe-54Co-9.5Cr (stainless steel invar). Further, the Fe-Co-Cr alloy may contain, in addition to Fe, c〇, and Cr, one or two or more metals selected from the group consisting of metals such as sfi, Ti, Mo, Pd, and Pt. In addition, the Fe-Co alloy is not particularly limited in the presence of Fe and Co. In addition to Fe and C, it may contain metals such as Ni, Ti, Mo, Cr, Pd, and Pt. One or more metals. Further, the Fe-Pt-based alloy contains Fe and Pt, and the rest is not particularly limited. In addition to Fe and Pt, it may contain C, Ni, Ti, Mo, Cr, Pd and the like. ! Species or more than two kinds of metals. Furthermore, Fe-Pd alloys are included! Under the premise of ^ and Pd, the rest is not 100131022 31 201230259. In addition to Fe and Pd, it can also contain an Mo, Cr, Pt and other metals! Species or more than two kinds of metals. In particular, the thermal expansion coefficient of the first reinforcing member 4 is preferably 5 ppm/t or more and 10 ppm/t or less, more preferably 1 ppm/t or more and 7卯4 or less, and particularly preferably Ippmrc or more and 5_/. 〇The following. Thereby, the difference in thermal coefficient between the semiconductor 7G member 3 and the first reinforcing member 4 can be reduced, and the wiring board 2 can be integrally reinforced. Therefore, it is possible to effectively prevent the wiring substrate 2 from being slightly bent. Further, the absolute value of the difference in thermal coefficient of the first reinforcing member 4 and the semiconductor element 3 is preferably 7 ppm/°C or less, more preferably 5 ppm/°C or less, and particularly preferably 2 ppm/°C or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the i-th reinforcing member 4 can be reduced, and the wiring board 2 can be integrally reinforced. Therefore, it is possible to effectively prevent the wiring board 2 from being in an interesting situation. In the case of the metal material-based Fe-Ni alloy constituting the first reinforcing member 4, the Fe-Ni alloy preferably has a Ni content of 3 〇 wt% or more and 50 wt% or less. More preferably, the Ni content is 35 wt% or more and 45 wt% or less. Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be made close to the thermal expansion coefficient of the semiconductor element 3. In this case, the Fe-Ni-based alloy preferably has a content of 5 Å by weight or more and 70% by weight or less, more preferably an Fe content of 55 wt / 〇 or more and 65% by weight or less. In the case of the metal material-based Fe-Ni-based alloy constituting the first reinforcing member 4, the Fe-Ni-based alloy preferably has a total content of Fe and Ni of 100131022 8 201230259 85 wt% or more and i〇〇wt The total content of Fe and Ni is preferably 90 wt%/〇 or more and 100% or less. That is, the content of the remaining portion (M) of the Fe_Ni-based alloy is preferably 〇wt% or more and i5 wt% or less, and more preferably the content of the remaining portion (M) is 〇wt% or more and 1% by weight or less. Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be made close to the thermal expansion coefficient of the semiconductor element 3. In addition, the average thickness of the first reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, and constituent materials of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2, and the like. The limit is, for example, 0.02 mm or more and 0.8 mm or less. Further, in the present embodiment, the thickness of the first reinforcing member 4 is uniform, but it may have a portion having a different thickness. For example, the thickness of the continuous member 4 and the semiconductor element 3 may be made from the inner side of the i-th reinforcing member 4 to the outside. #μ....... ' As shown in Figs. 1 and 2, in the first 1 reinforcement

填料與樹脂材料而構成的樹脂組成物。 式或階段式減少或增加。 再者，本實施形態中，A resin composition composed of a filler and a resin material. Decrease or increase in stage or stage. Furthermore, in this embodiment,

在呂、碎藻土、氧化J太、j 、石夕藻土、氧化鈦、氧化鐵、氧化鋅、氧化鎮、 金屬肥粒 100131022 33 201230259 鐵等氧化物；氣& & 一 吼化硼、氮化矽、氮化鎵、氮化鈦等氮化物. 氮氧化絲、盡_儿1 飞化鎂等氫氧化物；碳酸鈣(輕質、重質） 酸鎂、白雲石、 只）石灭 ""、片鈉鋁石等碳酸鹽；硫酸鈣、硫酸鋇、访缺 銨、亞硫酸鈣孳#^ ^酸 寻碳酸鹽或亞硫酸鹽；滑石、雲母、黏土 * 璃纖維、石夕酸艇 坡 巧、蒙脫石、膨潤土等矽酸鹽；硼酸鋅、值咖 酸鋇、硼酸鈀、_ 侷硼 侧酸鈣、硼酸鈉等硼酸鹽；碳黑、石累、# 纖維等碳；此饨止 "^ 卜向可舉例如鐵粉、銅粉、鋁粉、辞華、炉 鉬、硼纖維、鍅缺〜 瓜化 、鉀、鈦酸錯酸船。另外，當無機填料 用具導電*1"生:^ ίΛ α、 勺情況’視需要亦可對接觸到熱傳導性材料 的部位施行絕緣處理。 其中’上述無機填料從絕緣性與熱傳導性優異的觀點而 口’較佳為二氧化矽、氧化鋁、矽藻土、氧化鈦、氧化鐵、 氧化鋅氧化鎂、金屬肥粒鐵等氧化物；氮化硼、氮化矽、 氮化鎵、氮化鈦等氮化物。 再者，熱傳導性材料6(樹脂組成物)所使用的樹脂材料係 可舉例如各種熱可塑性樹脂、各種熱硬化性樹脂。 熱傳導性材料6(樹脂組成物)所使用的熱可塑性樹脂係可 舉例如聚乙烯、聚丙烯、乙烯-醋酸乙烯酯系共聚物等聚烯 扭；改質聚烯烴、聚醯胺(例：尼龍6、尼龍46、尼龍66、 尼龍610、尼龍612、尼龍η、尼龍12、尼龍6 12、尼龍 6-66)、熱可塑性聚醯亞胺、芳香族聚酯等液晶聚合物；聚 苯峻、聚苯硫醚、聚碳酸酯、聚甲基丙烯酸甲酯、聚醚、聚 !〇〇13]〇22 34 201230259 醚醚酮、聚醚醯亞胺、聚縮醛、苯乙烯系、聚烯烴系、聚氯 乙烯系、聚胺曱酸酯系、聚酯系、聚醯胺系、聚丁二烯系、 反式聚異戊二烯系、氟橡膠系、氯化聚乙烯系等各種熱可塑 性彈性體等，或者以該等為主的共聚物、摻合體、聚合物混 合體等’可單獨使用該等中之1種或混合使用2種以上。 再者’熱傳導性材料6(樹脂組成物)所使用的熱硬化性樹 脂可舉例如環氧樹脂、酚樹脂、脲樹脂、三聚氰胺樹脂、聚 酯（不飽和聚酯）樹脂、聚醯亞胺樹脂、聚矽氧樹脂、聚胺甲 酸酯樹脂等’可單獨使用該等中之1種或混合使用2種以上。In Lu, crushed algae soil, oxidized J Tai, j, Shixiazao soil, titanium oxide, iron oxide, zinc oxide, oxidized town, metal fertilizer grain 100131022 33 201230259 iron oxide; gas &&& Nitride such as tantalum nitride, gallium nitride or titanium nitride. Nitrogen oxide wire, hydroxide such as magnesium oxide; calcium carbonate (light, heavy) magnesium sulfate, dolomite, only stone "Burn" such as "sodium aluminite"; calcium sulphate, barium sulphate, ammonium sulphate, calcium sulphite 孳 #^ ^ acid to find carbonate or sulfite; talc, mica, clay * glass fiber, stone Citrate, montmorillonite, bentonite, etc.; silicates such as zinc borate, barium citrate, palladium borate, _ boronic acid, sodium borate, etc.; carbon black, stone tired, # fiber, etc. This can be used for example: iron powder, copper powder, aluminum powder, huahua, furnace molybdenum, boron fiber, 鍅 〜 ~ guava, potassium, titanium acid wrong acid boat. In addition, when the inorganic filler is electrically conductive*1" raw: ^ Λ 、 、, the case of the spoon' can also be insulated by the contact with the thermally conductive material. The above-mentioned inorganic filler is preferably an oxide such as cerium oxide, aluminum oxide, diatomaceous earth, titanium oxide, iron oxide, zinc oxide magnesia or metal ferrite, from the viewpoint of excellent insulation and thermal conductivity. Nitride such as boron nitride, tantalum nitride, gallium nitride or titanium nitride. Further, the resin material used for the thermally conductive material 6 (resin composition) may, for example, be various thermoplastic resins or various thermosetting resins. The thermoplastic resin used for the heat conductive material 6 (resin composition) may, for example, be a polystyrene such as polyethylene, polypropylene or an ethylene-vinyl acetate copolymer; a modified polyolefin or a polyamide (for example, nylon) 6, nylon 46, nylon 66, nylon 610, nylon 612, nylon η, nylon 12, nylon 6 12, nylon 6-66), thermoplastic polyimine, aromatic polyester and other liquid crystal polymers; poly benzene, Polyphenylene sulfide, polycarbonate, polymethyl methacrylate, polyether, poly! 〇〇 13] 〇 22 34 201230259 ether ether ketone, polyether oximine, polyacetal, styrene, polyolefin Various types of thermoplasticity such as polyvinyl chloride, polyamine phthalate, polyester, polyamine, polybutadiene, trans-polyisoprene, fluororubber, and chlorinated polyethylene. The elastomer or the like, or a copolymer, a blend, a polymer blend or the like which is mainly used may be used alone or in combination of two or more. Further, the thermosetting resin used in the 'thermal conductive material 6 (resin composition) may, for example, be an epoxy resin, a phenol resin, a urea resin, a melamine resin, a polyester (unsaturated polyester) resin, or a polyimide resin. In the above, one type of these may be used alone or two or more types may be used in combination.

其中，熱傳導性材料6(樹脂組成物)所使用的樹脂材料較 佳係使用熱硬化性樹脂（特別係硬化前呈液狀者），更佳係使 用酚树脂、裱氧樹脂，特佳係使用酚樹脂。藉此，可在第】 補強構件4與半導體元件3之間毫無留間隙地將熱傳導性材 料6真充’且可有效地抑制熱傳導性材料6的熱膨服係數。 。亥酚树脂係可舉例如酚酚醛樹脂、甲酚酚醛樹脂、雙酚A 祕樹脂等祕魏樹脂；未改f的祕賴脂；經諸如桐 油、亞麻仁油、核桃油等改質過的油改質祕_脂等祕 型酚樹脂等等齡樹脂等。 再者’該熱傳導性材料6亦可使用與前述接著層32(填底 材）同樣者，且亦可統括形成熱傳導性材料6與接著層32。 [苐2補強構件] 第2補強構件(補強板)5係接合於佈線基板2的基板21 100131022 35 201230259 下面（另一面）。 该第2補強構件5與基板21係可經由接著劑進行接合。 藉此’第2補強構件5的設置簡單。 该接著劑係在具有接著機能的前提下，其餘並無特別的限 疋’可使用各種接著劑’較佳係熱傳導性優異者，可使用與 後述熱傳導性材料6同樣者。 。玄第2補強構件5係與前述第】補強構件4同樣的，熱膨 脹係數小於基板21。 第2補強構件5係形成為板狀。藉此，第2補強構件 的構造可形成簡單且小型者。 再者，如圖3所示，笛0 $ 第2補強構件5係具備有：沿佈線』 板2(基板川外周部(較導體圖案224更靠外側)設置的部》 (框部X框部)52、與在金屬凸塊71彼此間設置的部分53t 藉由第2觀構件5㈣分52㈣絲板2(基板2购 接。第2補強構件5可有效地補強佈線基板2。又，藉廷 第2補強構件5的部分53與佈祕板2之接合，可提高筹 2補強構件5的剛性。 更具體說明，第2補彳纟μ # ^ .Μ Λ .. 71 θ . 冓件5係具備有依非接觸於前述各 金屬凸塊71且包圍各合麗 51 M. tf- ^ ,凸塊71的方式形成之複數開口部 51。错此，可增加第2補 之面積比例。結果，可使利在佈線基板2的下面所佔 2之剛性的效果優異。用第2_構件5提高佈線基板 100131022 ⑧ 36 201230259 本實施形態中，各開口部51係俯視呈圓形。另外，各開 口部51的俯視形狀並不僅限定於此，亦f為例如橢圓开y 多角形等。 再者，各開口部51係對應各金屬凸塊71(一對一地對應) •設置。藉此’可達第2補強構件5的剛性之均句化。又’亦 •可提升第2補強構件5的散熱性。 再者，第2補強構件5係依與各金屬凸塊71間之距離(俯 視時，開口部51的壁面與金屬凸塊71的外阈面間之距離） 橫跨金屬凸塊71全周呈一定的方式形成。藉此，可增加第 2補強構件5與各金屬凸塊71的—體性，適當發揮由該等 產生的佈線基板2之補強效果。 本實施形態中，在第2補強構件5的下面設有導熱凸塊 91 〇 該導熱凸塊91係具有較佈線基板2的基板21更高之熱傳 導性，例如在後述半導體裳置100中接A於母板·。藉此， 可的熱發散於外部㈣^ 下’其餘並無特別的限定，可^有Μ述的導熱性之前提 特別較佳係使用與前述金屬例如金屬材料、樹脂材料’ 無機填料與樹糾料的導^同樣的構成材料、含有 再者，與前逑第！補強構件者劑等。 較佳係與半導體元件3 同樣的，第2補強構件5 100131022 之熱知脹係數差在7ppm/t：以下。 37 201230259 藉此，第2補強構件5可有效地㈣佈線基板2,並可抑制 半導體封褒1整體的熱膨脹。 再者，第2補強構件5較佳係由金屬材料構成。藉此，可 提局第2補強構件5的散熱性、结果，可提升半導體封裝！ 的散熱性。 該金屬材料並無特別的限定，從實現散熱性與低熱膨服的 觀點而言，較佳係使用系合金。In particular, the resin material used for the heat conductive material 6 (resin composition) is preferably a thermosetting resin (particularly, it is liquid before curing), and more preferably a phenol resin or a silicone resin is used. Phenolic resin. Thereby, the thermally conductive material 6 can be reliably filled with no gap between the first reinforcing member 4 and the semiconductor element 3, and the thermal expansion coefficient of the thermally conductive material 6 can be effectively suppressed. . The phenolic resin may, for example, be a phenolic phenol resin, a cresol novolac resin, a bisphenol A secret resin, or the like; a secret fat which has not been modified; a modified oil such as tung oil, linseed oil, walnut oil, or the like. Modified secret _ phenol such as secret phenol resin and so on. Further, the thermally conductive material 6 may be the same as the above-mentioned adhesive layer 32 (filled with a substrate), and the thermally conductive material 6 and the adhesive layer 32 may be integrally formed. [苐2 reinforcing member] The second reinforcing member (reinforcing plate) 5 is bonded to the substrate 21 of the wiring board 2 100131022 35 201230259 Next (the other surface). The second reinforcing member 5 and the substrate 21 can be joined via an adhesive. Thereby, the arrangement of the second reinforcing member 5 is simple. The adhesive is not particularly limited as long as it has an adhesive function. The various adhesives can be used. It is preferable that the thermal conductivity is excellent, and the same as the thermally conductive material 6 described later can be used. . The second reinforcing member 5 is the same as the above-described first reinforcing member 4, and has a thermal expansion coefficient smaller than that of the substrate 21. The second reinforcing member 5 is formed in a plate shape. Thereby, the structure of the second reinforcing member can be formed into a simple and small size. In addition, as shown in FIG. 3, the rib 0$ second reinforcing member 5 is provided with a portion along the wiring board 2 (the outer peripheral portion of the substrate (outside the conductor pattern 224)" (frame portion X frame portion) 52. The portion 53t provided between the metal bumps 71 is divided by the second viewing member 5 (four) 52 (four) silk plate 2 (the substrate 2 is purchased. The second reinforcing member 5 can effectively reinforce the wiring substrate 2. The portion 53 of the second reinforcing member 5 is joined to the cloth board 2 to increase the rigidity of the reinforcing member 5. More specifically, the second complement #μ # ^ .Μ Λ .. 71 θ . The plurality of openings 51 are formed so as not to be in contact with the respective metal bumps 71 and surround the respective protrusions 51 M. tf- ^ and the bumps 71. In this case, the area ratio of the second complement can be increased. The effect of the rigidity of the second surface of the wiring board 2 can be improved. The wiring board 100101022 is added to the second board member 100. In the present embodiment, each of the openings 51 has a circular shape in plan view. The shape of the plan portion 51 is not limited to this, and f is, for example, an elliptical opening y polygon or the like. Further, each of the opening portions 51 corresponds to each other. The bumps 71 (one-to-one correspondence) are provided. This means that the rigidity of the second reinforcing member 5 can be increased. Further, the heat dissipation of the second reinforcing member 5 can be improved. The reinforcing member 5 is formed so as to be spaced apart from each of the metal bumps 71 (the distance between the wall surface of the opening 51 and the outer threshold surface of the metal bump 71 in plan view) across the entire circumference of the metal bump 71. In this way, the reinforcing property of the second reinforcing member 5 and each of the metal bumps 71 can be increased, and the reinforcing effect of the wiring board 2 generated by the above can be appropriately exhibited. In the present embodiment, the lower surface of the second reinforcing member 5 is provided. The heat conductive bump 91 has a higher thermal conductivity than the substrate 21 of the wiring board 2, for example, in the semiconductor skirt 100 described later, A is connected to the mother board. Thereby, the heat is dissipated to the outside. (4) The following is not particularly limited, and it is particularly preferable to use the same constituent material as the above-mentioned metal such as a metal material, a resin material, an inorganic filler, and a tree material, in addition to the thermal conductivity described above. Contains further, and the former 逑 ! reinforced member, etc. Similarly, in the semiconductor element 3, the thermal expansion coefficient difference of the second reinforcing member 5 100131022 is 7 ppm/t or less. 37 201230259 Thereby, the second reinforcing member 5 can effectively (4) the wiring substrate 2 and suppress the semiconductor package 1 Further, the second reinforcing member 5 is preferably made of a metal material, whereby the heat dissipation property of the second reinforcing member 5 can be improved, and as a result, the heat dissipation of the semiconductor package can be improved. There is no particular limitation, and from the viewpoint of achieving heat dissipation and low heat expansion, it is preferred to use a system alloy.

Fe_Ni系合金係可使用與前述第1補強構件4同樣者。 尤其’第2補強構件5的熱膨脹係數較佳係Q 5ppm/t^ 上且10PPm/t：以下、更佳係lppm/t以上且7ppmrc以下、 特佳係lppm/t：以上且5ppm/t:以下。藉此，可縮小半導體 7L件3與第2補強構件5間之熱膨脹係數差，且第2補強構 件5可有效_強佈、絲板2。故，可有效果驗止佈線基 板2發生輕曲情形。 再者，第2補強構件5與半導體元件3間之熱膨脹係數差 絕對值，較佳係7PPmA：以下、更佳係5ppm/t以下、特佳 係2Ppm/t：以下。藉此，可縮小半導體元件3與第2補強構 件5間之熱膨脹係數差’且第2補強構件5可有效地補強佈 線基板2。故，可有效果地防止佈線基板2發生翹曲情形。 再者’第2補強構件5與第丨補強構件4間之熱膨脹係數 差絕對值，較佳係以下、更佳係lppm/〇C以下、特 佳係0PPm/t。藉此，可縮小第！補強構件4與第2補強構 100131022 38 201230259 件5間之熱膨脹係數差，可防止因該等熱膨 線基板2發生趣曲情形。 脹差所造成 的佈 田此徑親點阳5 … *、 · 战材料較佳係血筮 1補強構件4的構成材料屬於同種或相同。 、/、第 再者，第2補強構件5的平均厚度係依日π ^ ^ L π佈線基板2的瓿 膨脹係數、佈線基板2的第1補強構件4你姑 …' 、 Τ4與苐2補強構件5 之形狀、大小、構成材料等而決定，並|姓σ, …、特別的限定，例如 為0.02mm以上且0.8mm以下左右。 在第2補強構件5與各金屬凸塊71之間設有（填充德緣 材8卜藉此，可防止第2補強構件5與各金屬凸塊7ι間之 接觸。故，f減半導體封裝1的可靠度優異，並可提高第 2補強構件5的剛性與散熱性。 再者’絕緣讨81係形成為包圍著金屬凸塊71的基板21 侧之部分(上部）的周圍形狀’且接合於各金屬凸塊71。藉 此，絕緣材81補強金屬凸塊71。 再者，絕緣材81較佳係具有高於前述佈線基板2之基板 2!的熱傳導性。藉此，可使金屬凸魏與第2補強構件5 間的熱傳科優異’可提升料體轉丨的散熱性。 此種絕緣材81係具有絕緣性，且含有_旨材料而構成。 此種絕緣材81广，特別的限定’較佳係例如由具熱硬化 性的銲錫接合用樹脂所形成者。 此種銲錫接合__以下亦稱「硬化性助焊劑」）係在鲜 100131022 39 201230259 錫接合時發揮助焊劑的作用，藉由 口吗坎考她盯的加熱而硬化， 發揮銲錫接合部之補強材的作用。另外，助焊劑係在鲜錫接 合時會較銲錫紐解，而將金屬與銲錫表面的氧化物、癖汗 等予以除去的㈣。又合用樹脂係當銲錫接合之 際，會將銲錫接合面與銲锡材㈣氧化料㈣物予以去 除’使在保護銲錫接合面的情況下，施行銲錫材料的精煉， 而可進行強度^良好接合。又’銲錫接合用樹脂在鮮锡接 合後並無必要利用洗淨等予以除去，可直接藉由加熱而形成 三次元交聯的樹脂’而發揮作或奸 平作為隹于錫接合部的補強材之作 用。 該銲錫接合用樹脂係可例如含有具雜經基之樹脂⑷及 上述樹脂之硬化劑(Β)而構成。 具盼性經基之樹脂（Α)並無特別的限制，可舉例如紛祕 •fef脂、烧基紛酌 lir樹脂、多元紛酌越樹脂、g分越樹脂、聚乙 稀基系紛樹脂等。 再者’硬化性助焊劑中，具酚性羥基之樹脂(A)的含有量， 較佳係佔硬化性助焊劑整體的20〜80重量％、更佳係25〜60 重量％。若樹脂(A)的含有量未滿20重量％，則將銲錫與金 屬表面的氧化物等髒汙予以除去之作用會降低，會有導致銲 錫接合性不良的可能性。若樹脂(A)的含有量超過80重量 4 ’則無法獲得具有充分物性的硬化物，會有接合強度與可 靠度降低的可能性。 100131022 201230259 再者，具酚性羥基之樹脂(A)的酚性羥基係藉由其還原作 用，而將銲錫與金屬表面的氧化物等髒汙予以除去，故能有 效發揮當作銲錫接合之助焊劑的作用。 再者，具酚性羥基之樹脂(A)的硬化劑(B)係可舉例如環氧 化合物、異氰酸酯化合物等。環氧化合物及異氰酸酯化合物 係可舉例如雙酚系、酚酚醛系、烷基酚酚醛系、雙酚系、英 酉分系、間苯二㈣、等喊質的環氧化合物；$氰酸醋化^ 物；以飽和脂肪族、環狀脂肪族、不飽和脂肪族等骨架為基 礎的經改質環氧化合物、異氰酸酯化合物等。 土 再者，硬化劑⑻的掺合量較佳係硬化劑的環氧基、異氛 酸酯基等反應性官能基為樹脂(Α)的酚性羥基之〇5〜1 $當 量倍、更佳係0H.2當量倍。若硬化_反應性官能基未 滿絲的0.5當量倍，則無法獲得具充分物性的硬化物，會 有補強效果變小、接合強度與可靠度降低的可能性。若 劑的反應性官能基超過羥基的丨5洛旦 心、灶土幻I.5备里倍，則將銲錫與金屬 表面的氧化物等予以除去之作用會降低，會有導軸 接合性不良的可能性。 此種銲錫接合用樹脂(硬化性助焊劑）中，利用㈣性經基 之樹脂⑷與上述樹脂的硬化劑(Β)間之反應，而形成具有良 好物性的硬化物。故’在銲難合後不f糾贼淨將助焊 劑予以除去，可利用硬化物倾銲錫接合部，即便高溫、多 濕被境下仍可保持電絕緣性，可進行接合強度與可靠度較高 100131022 201230259 的鮮錫接合。 另外，如前述的銲錫接合用樹脂係除了具酚性羥基之樹脂 (A)與該樹脂的硬化劑（b)之外，尚可含有硬化性抗氧化劑 (C)、依微結晶狀態分散的具酚性羥基之化合物(D)及該化合 物的硬化劑(E)、溶劑(F)、硬化觸媒、用以提升密接性與耐 濕性的石夕烧偶合劑、用以防止孔隙的消泡劑、或液狀或粉末 難燃劑等。 (上層封裝） 上層封裝（第2封裝)300係具備有佈線基板301及半導體 元件305 ’在佈線基板301之半導體元件305側的面，設有 覆蓋著半導體元件305的密封部307。另外，圖示上層封裝 300的構造僅為一例，本發明並不僅限定於此。 [佈線基板] 佈線基板301係支撐著半導體元件305的基板（第2佈線 基板），例如將其所搭載的半導體元件305、與前述下層封 裝500間之電氣式連接予以中繼的中繼基板（中介層）。又， 佈線基板301的俯視形狀通常係設為正方形、長方形等四角 形。 佈線基板301係具有基板302。該基板302係由具絕緣性 的材料構成，例如由基材(纖維基材）、與該基材中所含浸的 樹脂組成物構成。該基材與樹脂組成物係可使用與前述下層 封裝500的佈線基板2之絕緣層同樣者。另外，圖示例中， 100131022 42 ⑧ 201230259 基板302係由-層的絕緣層構成，值亦可由複數絕緣層構 在此種基板302的下面設有導髀闽〜 nThe Fe_Ni-based alloy system can be the same as the first reinforcing member 4 described above. In particular, the coefficient of thermal expansion of the second reinforcing member 5 is preferably Q 5 ppm/t^ and 10 ppmm/t: or less, more preferably 1 ppm/t or more and 7 ppmrc or less, particularly preferably 1 ppm/t: or more and 5 ppm/t: the following. Thereby, the difference in thermal expansion coefficient between the semiconductor 7L member 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can be effectively reinforced and the core plate 2. Therefore, it is possible to check that the wiring substrate 2 is slightly bent. Further, the absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the semiconductor element 3 is preferably 7 ppm mA: or less, more preferably 5 ppm/t or less, and particularly preferably 2 Ppm/t or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, it is possible to effectively prevent the wiring substrate 2 from being warped. Further, the absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the second reinforcing member 4 is preferably less than or equal to 1 ppm/〇C, and particularly preferably 0 ppm/t. By this, you can narrow the number! The difference in thermal expansion coefficient between the reinforcing member 4 and the second reinforcing structure 100131022 38 201230259 5 prevents the occurrence of an interesting situation due to the thermal expansion substrate 2. The cloth caused by the difference in the expansion of the path is pro-yang 5 ... *, · The warfare material is preferably bloody. 1 The constituent materials of the reinforcing member 4 belong to the same species or the same. Further, the average thickness of the second reinforcing member 5 is 瓿 π ^ ^ 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 布线 ' ' ' ' ' ' 布线 布线 布线 布线 布线 布线The shape, the size, the constituent material, and the like of the member 5 are determined, and the last name is 0.02 mm or more, and is, for example, about 0.02 mm or more and 0.8 mm or less. The second reinforcing member 5 and each of the metal bumps 71 are provided (filling the edge material 8 to prevent contact between the second reinforcing member 5 and each of the metal bumps 7). Therefore, the f-substrate semiconductor package 1 is removed. The reliability of the second reinforcing member 5 is improved, and the rigidity and heat dissipation of the second reinforcing member 5 can be improved. Further, the 'insulation type 81 is formed so as to surround the peripheral shape of the portion (upper portion) on the side of the substrate 21 of the metal bump 71 and is bonded to Each of the metal bumps 71. Thereby, the insulating material 81 reinforces the metal bumps 71. Further, the insulating material 81 preferably has a higher thermal conductivity than the substrate 2! of the wiring board 2. The heat transfer between the second reinforcing member 5 and the second reinforcing member 5 can improve the heat dissipation of the material transfer. The insulating material 81 is made of insulating material and contains a material. The insulating material 81 is wide and special. For example, it is preferably formed of a thermosetting solder bonding resin. Such a solder joint __ hereinafter referred to as a "curable flux" is used as a flux during the soldering of fresh 100131022 39 201230259. , hardened by the heat of the mouth The role of reinforcement material of solder joints. In addition, the flux is removed from the solder when the tin is joined, and the metal and the oxide on the surface of the solder, sweat, etc. are removed (4). In addition, when the solder is joined, the solder joint surface and the solder material (4) oxide material (4) are removed. When the solder joint surface is protected, the solder material is refined, and the strength is good. . Further, the resin for solder bonding does not need to be removed by washing or the like after the bonding of the fresh tin, and the resin which is formed by the three-dimensionally crosslinked resin can be directly formed by heating, and is used as a reinforcing material for the tin joint portion. The role. The resin for solder bonding can be composed, for example, of a resin (4) having a hetero group and a curing agent (?) of the above resin. There is no particular limitation on the resin (Α) having a desired basis, and for example, the secret fef fat, the liki resin, the multi-resin resin, the g-ratio resin, and the polyethylene-based resin. Wait. Further, in the hardening flux, the content of the phenolic hydroxyl group-containing resin (A) is preferably from 20 to 80% by weight, more preferably from 25 to 60% by weight based on the total amount of the curable flux. When the content of the resin (A) is less than 20% by weight, the effect of removing impurities such as oxides on the surface of the metal and the metal may be lowered, and the solder joint property may be deteriorated. When the content of the resin (A) exceeds 80% by weight, a cured product having sufficient physical properties cannot be obtained, and the joint strength and the reliability may be lowered. 100131022 201230259 Further, the phenolic hydroxyl group of the phenolic hydroxyl group-containing resin (A) can remove the solder and the oxide on the metal surface by the reduction action, thereby effectively utilizing the flux as a solder joint. The role. Further, the curing agent (B) of the phenolic hydroxyl group-containing resin (A) may, for example, be an epoxy compound or an isocyanate compound. Examples of the epoxy compound and the isocyanate compound include bisphenol-based, phenol novolac-based, alkylphenol phenolic-based, bisphenol-based, indane-based, isophthalic (tetra), and the like. A chemically modified epoxy compound, an isocyanate compound or the like based on a skeleton such as a saturated aliphatic, a cyclic aliphatic or an unsaturated aliphatic. Further, the blending amount of the hardener (8) is preferably such that the reactive functional groups such as the epoxy group and the isocyanate group of the hardener are phenolic hydroxyl groups of the resin (Α) 〇 5 to 1 equivalent times, more Good system 0H.2 equivalent times. When the hardening-reactive functional group is less than 0.5 equivalent times of the filament, a cured product having sufficient physical properties cannot be obtained, and the reinforcing effect is small, and the joint strength and reliability may be lowered. If the reactive functional group of the reagent exceeds the hydroxyl group, the ruthenium 5 ruthenium and the ruthenium I.5 are reduced, the effect of removing the oxide and the oxide on the metal surface is lowered, and the lead bondability is poor. The possibility. In such a solder joint resin (curable flux), a cured product having good physical properties is formed by a reaction between the resin (4) of the (tetra) radical and the curing agent (Β) of the resin. Therefore, after the welding is difficult, the flux is removed, and the hardened solder joint can be used. Even if the temperature is high and the humidity is maintained, the electrical insulation can be maintained, and the joint strength and reliability can be compared. High tin joints of high 100131022 201230259. In addition, the resin for solder bonding described above may contain a curable antioxidant (C) and a device dispersed in a microcrystalline state in addition to the resin (A) having a phenolic hydroxyl group and the curing agent (b) of the resin. a phenolic hydroxyl group compound (D), a hardener (E) of the compound, a solvent (F), a hardening catalyst, a stone smelting coupling agent for improving adhesion and moisture resistance, and a defoaming agent for preventing pores Agent, or liquid or powder flame retardant, etc. (Upper Package) The upper package (second package) 300 includes a wiring board 301 and a semiconductor element 305' on the surface of the wiring board 301 on the side of the semiconductor element 305, and is provided with a sealing portion 307 that covers the semiconductor element 305. Further, the configuration of the upper package 300 is merely an example, and the present invention is not limited thereto. [Wiring Board] The wiring board 301 is a board (second wiring board) on which the semiconductor element 305 is supported, and for example, a relay board in which the semiconductor element 305 mounted thereon and the lower layer package 500 are electrically connected to each other ( Intermediary layer). Moreover, the planar shape of the wiring board 301 is generally a square shape such as a square or a rectangle. The wiring board 301 has a substrate 302. The substrate 302 is made of an insulating material, for example, a substrate (fiber substrate) and a resin composition impregnated with the substrate. The base material and the resin composition can be the same as those of the wiring board 2 of the lower package 500. In addition, in the example of the figure, 100131022 42 8 201230259 The substrate 302 is composed of a layer of insulating layer, and the value may be formed by a plurality of insulating layers under the substrate 302.

穷導體圖案308。該導體圖案3〇S 係經由前述各金屬凸塊400，接厶认 _ σ於下層封裝500的導體圖 案225。又，在基板302的上面，雖 雖未圖示，但設有經由貝 通基板302的導體柱而電氣式連接 钱於導體圖案308 ’且與+ 導體元件305呈電氣式連接的導體圖案。 違等導體圖案與導體柱係可與前述佈線基板2的導體圖 案及導體柱為同樣構造。 再者，在基板302的下面，依覆蓋導體圖案3〇8的方式設 有絕緣層304。同樣的，在基板302的上面設有絕緣層3〇3。 5亥絕緣層3 03、3 04分別係例如可由公知防焊劑形成。 在此種佈線基板301的上面係接合著半導體元件3〇5。 [半導體元件] 半導體元件（第2半導體元件)3〇5係例如積體電路-& %疋件 (IC) ’更具體而言為例如邏輯1C、記憶體及受發光元件等 另外，半導體元件305的構造及機能分別係可與前述半導體 元件3的構造及機能為相同、亦可為不同。 該半導體元件305係經由複數金屬絲線306，電氣式連接 於在前述佈線基板301的上面側所設置之導體圖案（未 示）。Poor conductor pattern 308. The conductor pattern 3〇S is connected to the conductor pattern 225 of the lower package 500 via the respective metal bumps 400. Further, on the upper surface of the substrate 302, although not shown, a conductor pattern electrically connected to the conductor pattern 308' via the conductor post of the pass-through substrate 302 and electrically connected to the + conductor element 305 is provided. The dummy conductor pattern and the conductor post can be constructed in the same manner as the conductor pattern and the conductor post of the wiring board 2 described above. Further, on the lower surface of the substrate 302, an insulating layer 304 is provided so as to cover the conductor pattern 3?8. Similarly, an insulating layer 3〇3 is provided on the upper surface of the substrate 302. Each of the 5H insulating layers 3 03 and 3 04 can be formed, for example, from a known solder resist. The semiconductor element 3〇5 is bonded to the upper surface of the wiring board 301. [Semiconductor element] Semiconductor element (second semiconductor element) 3〇5 is, for example, an integrated circuit-&% element (IC)' More specifically, for example, logic 1C, memory, and light-receiving element, etc. The structure and function of the 305 may be the same as or different from the structure and function of the semiconductor element 3 described above. The semiconductor element 305 is electrically connected to a conductor pattern (not shown) provided on the upper surface side of the wiring board 301 via a plurality of metal wires 306.

該等各金屬絲線306係例如利用公知焊接搭線 100131022 43 201230259 成。另外，該電氣式連接亦可取代金屬絲線，而與前述下層 封裝500同樣的，利用倒裝焊接實施。 此種半導體元件305係利用密封部307進行密封。 該密封部3〇7係在佈線基板301的上面依覆蓋著半導體_ 件305的方式設置，故可提高上層封裝3〇〇的剛性。故可 防止或抑制上層封裝300的翹曲。 該密封部307 封樹脂。 的構成材料並無特別的限定，可使用公知々 此種上層封裝的佈線基板3G1之下面，係與前述下> ί虞00的半導體凡件3呈非接觸(遠離）。本實施形態中 半導體元件3的上面全域係對佈線基板3()1的下面遠離。辑 此二透過在半導體元件3與佈線基板301間形成的間隙Si 進仃通氣’便可將半導體元件3的熱有效率地朝外邊發气 =體元件3的上面與佈、線基板3〇1的下面間之距二 ㈣W的厚度方向長度)L，從確保前述通氣的觀點而言， 較佳為〇.〇lmm以上且〇.8mm以下。L更佳係〇 〇5_ 且〇.5mm以下。 上 再者本貫施形態中，如前述，因為半導體元件3的上 與第1補強構件4的上面位於同一面，故佈線基板3〇 ㈣1觸構件4之上面遠離(料 剛本貫㈣…第"甫強構件4的上 板3〇1的下面呈非接觸。透過⑷補強構件4與佈線基^ 100131022 201230259 301之間形成的間隙S2進行通氣，可將半導體元件3的熱 有效率地朝外邊發散。故，可使半導體封裝1的散熱性優 異。另外，亦可第1補強構件4的上面其中一部分接觸到佈 線基板301的下面。 根據依如上所說明構成的半導體封裝1，即便與半導體元 件3相接合的部分以外之部分處，因為佈線基板2利用第1 補強構件4進行補強，故增加下層封裝5〇〇整體的剛性。特 別，因為第1補強構件4的熱膨脹係數小於佈線基板2(具 體而言為基板21)，故與半導體元件3橫跨佈線基板2整面 设置的情況同樣的，可抑制或防止因佈線基板2與半導體元 件3間之熱祕係數差所造成的佈線基板2發线曲情形。 再者，因為半導體元件3與佈線基板3〇1呈非接觸，故透 過半導體7L件3與佈線基板301間所形成之間隙施行通氣， 可將半導體元件3的熱有效率地朝外發散。又，因為不需要 提高佈線基板2本身_性，可削薄佈線基板2的厚度，故 可提高佈線基板2的厚度方向熱傳導性，可將來自半導體元 件3的熱經由佈線基板2進行發散。由此，半導體封裝1 的散熱性優異。又，藉由適當選擇第丨補強構件4與第2 補強構件5的構成材料，亦可提高半導體縣丨的散熱性。 此種半導體封裝1的優異散熱性，亦可有效抑制或防止因 佈線基板2與半導體元件3間之__數差所造成的佈線 基板2發生輕曲㈣。結果，可使上層封们〇〇與下層封裳 100131022 45 201230259 500間的電氣式連接可靠度優異。 再者’半導體封裳1中，藉由將第2補強構件5接合於佈 線基板2與半導體元件3相反側之面（下面），形成佈線基板 2由半導體元件3與第2補強構件5夾持的狀態，故可更牢 固地補強佈線基板2,並可_佈線基板2的雙面熱膨服 差。特別因為第2補強構件5係在後述金屬凸塊71間亦有 設置，故可牢固地補強佈線基板2。 (半導體封裝之製造方法） 如以上所說明的半導體封裝丨_如可依如下進行製造。 以下’根據圖4，針對半導體封裝！之製造方法一例進二于 簡單說明。另外，半導體封裝1之製造方法並不僅限定於此。 [1] ' 首先，如圖4(a)所示’準備金屬層221a鱼箱、，μ， /、了貝/文片211Α 的積層體，在該積層體靠預浸片211Α側之面黏貼第^、、 構件4。 、補強 的樹脂組成物之 形成前述佈線基 此處’預浸片211A係由前述絕緣層211 未硬化物（半硬化物）含浸於基材中而構成， 板2的絕緣層211。 再者，金屬層221A係用以形成前述佈線基板2之導體圖 案221，由與導體圖案221的構成材料為同樣之材料構成θ。 [2] 其次’如圖4(b)所示’在預浸片211Α中形成貫通孔 100131022 46 201230259 2111(介層洞）。 貝通孔2111的形成方法並無特別的限定，例如可利用照 射雷射而形成。 此處田射係可使用例如c〇2雷射、UV_YAG雷射等。 另外’貫通孔211卜亦可例如利用鑽床等機械加工而形成。 [3] 其次’如圖4(c)所示’在貫通孔2111内形成導體柱231 與導體圖案225。 導體柱231的形成方法並無特別的限定，可使用例如填充 導電性糊劑的方法、利用無電解電鍍施行埋入的方法、利用 電解電鍍施行埋入的方法等。 再者，導體圖案225的形成方法並無特別的限定，可使用 例如塗佈導電性糊劑的方法、利用無電解電鍍進行成膜的方 法等。 [4] 其次，如圖4(d)所示，藉由對金屬層221A施行圖案化而 形成導體圖案221。 該圖案化的方法並無特別的限定，最好使用蝕刻。 如上述，形成絕緣層211、導體圖案221及導體柱231。 [5] 其次，與上述步驟[1]〜[4]同樣的，分別準備用以形成絕緣 層212、213、214、215及導體圖案222、223、224之由預 100131022 47 201230259 浸片與金屬層構成的積層體，而形成導體圖案222、223、 224 及導體柱 232、233、234、235。 再者，將用以形成絕緣層211、212、213、214、215的預 浸片進行積層後，再使用與導體柱231、232、233、234、 235同樣的方法，形成導熱柱24。 然後，使用以形成絕緣層211、212、213、214、215的預 浸片進行硬化（完全硬化），如圖4(e)所示，獲得佈線基板2。 將用以形成絕緣層211、212、213、214、215的預浸片進 行積層之方法，係可舉例如真空壓合、層壓等。該等之中較 佳係利用真空壓合施行的接合方法。藉此，可提升用以形成 絕緣層211、212、213、214、215之預浸片的密接強度。 使用以形成絕緣層211、212、213、214、215的預浸片硬 化之方法’並無特別的限定，可適當使用例如熱處理。 另外’導熱柱24的形成亦可在形成各導體柱231、232、 233、234、235之同時，也在用以形成各絕緣層211、212、 213、214、215的預浸片中形成導熱柱，藉由將該等預浸片 進行積層’而將該等導熱柱予以連接形成。 [6] 其次’在佈線基板2的下面塗佈絕緣材81A之後，再將 金屬球(銲錫球)71A利用銲錫迴焊施行銲錫接合。藉此形成 金屬凸塊71與絕緣材81。 該銲錫接合並無特別的限定，依佈線基板2的下面抵接著 100131022 48 ⑧ 201230259 各金屬凸塊71的方式配置，於此狀態下，藉由施行例如 200〜280°〇 10〜60秒鐘加熱便可實施。 再者，絕緣材81A係形成前述絕緣材81，再利用例如加 熱而硬化。Each of the metal wires 306 is formed, for example, by a known welding wire 100131022 43 201230259. Further, this electrical connection may be implemented by flip chip bonding in place of the metal wire as in the case of the lower package 500 described above. Such a semiconductor element 305 is sealed by a sealing portion 307. Since the sealing portion 3〇7 is provided on the upper surface of the wiring board 301 so as to cover the semiconductor element 305, the rigidity of the upper package 3〇〇 can be improved. Therefore, warpage of the upper package 300 can be prevented or suppressed. The sealing portion 307 seals the resin. The constituent material is not particularly limited, and the underside of the wiring board 3G1 which is known as such an upper layer can be used in a non-contact (away) from the semiconductor element 3 of the above-mentioned > In the present embodiment, the entire upper surface of the semiconductor element 3 is separated from the lower surface of the wiring board 3 () 1 . According to the second aspect, the heat of the semiconductor element 3 is efficiently radiated outward by the gap Si formed between the semiconductor element 3 and the wiring substrate 301. The upper surface of the body element 3 and the cloth and the wire substrate 3〇1 The distance between the lower side of the second (four) W in the thickness direction L) is preferably 〇.1 mm or more and 〇.8 mm or less from the viewpoint of ensuring the above-described ventilation. L is better system 〇5_ and 〇.5mm or less. In the above-described embodiment, as described above, since the upper surface of the semiconductor element 3 and the upper surface of the first reinforcing member 4 are located on the same surface, the wiring substrate 3 (4) is separated from the upper surface of the contact member 4 (the material is just the same (four)... "The lower surface of the upper plate 3〇1 of the bare member 4 is non-contact. The heat is efficiently transmitted to the gap S2 formed between the reinforcing member 4 and the wiring substrate 100101022 201230259 301. Therefore, the semiconductor package 1 can be excellent in heat dissipation. Further, a part of the upper surface of the first reinforcing member 4 may be in contact with the lower surface of the wiring board 301. According to the semiconductor package 1 configured as described above, even with the semiconductor In the portion other than the portion where the elements 3 are joined, since the wiring board 2 is reinforced by the first reinforcing member 4, the rigidity of the entire lower package 5 is increased. In particular, since the thermal expansion coefficient of the first reinforcing member 4 is smaller than that of the wiring substrate 2 (specifically, the substrate 21), the wiring board 2 and the semiconductor element 3 can be suppressed or prevented, similarly to the case where the semiconductor element 3 is provided over the entire surface of the wiring board 2. In the case where the wiring element 2 is in a line-changing condition due to the difference in the thermal coefficient, the semiconductor element 3 is in non-contact with the wiring board 3〇1, so that the gap formed between the semiconductor 7L member 3 and the wiring substrate 301 is ventilated. The heat of the semiconductor element 3 can be efficiently dissipated outward. Further, since it is not necessary to increase the thickness of the wiring board 2 itself, the thickness of the wiring board 2 can be thinned, so that the thermal conductivity of the wiring board 2 in the thickness direction can be improved. The heat from the semiconductor element 3 is diverged via the wiring board 2. This makes the semiconductor package 1 excellent in heat dissipation properties. Further, by appropriately selecting the constituent materials of the second reinforcing member 4 and the second reinforcing member 5, the semiconductor can be improved. The heat dissipation of the semiconductor package 1. The excellent heat dissipation of the semiconductor package 1 can also effectively suppress or prevent the wiring substrate 2 from being slightly bucked by the difference in the number between the wiring board 2 and the semiconductor element 3 (four). The electrical connection between the upper seal and the lower seal 100131022 45 201230259 500 is excellent. Further, in the semiconductor seal 1, the second reinforcing member 5 is joined to the cloth. The surface (the lower surface) of the substrate 2 opposite to the semiconductor element 3 forms a state in which the wiring board 2 is sandwiched between the semiconductor element 3 and the second reinforcing member 5, so that the wiring board 2 can be more firmly reinforced, and the wiring board 2 can be reinforced. In particular, since the second reinforcing member 5 is provided between the metal bumps 71 to be described later, the wiring board 2 can be firmly reinforced. (Manufacturing method of the semiconductor package) The semiconductor package as described above For example, the manufacturing method of the semiconductor package can be described briefly with reference to Fig. 4. The method of manufacturing the semiconductor package 1 is not limited thereto. [1] ' First, as shown in the figure 4(a) shows a laminated body in which the metal layer 221a fish tank, μ, /, and the shell/text sheet 211Α are prepared, and the first and second members are adhered to the surface of the layered body on the side of the prepreg sheet 211. The reinforcing resin composition forms the wiring layer. Here, the prepreg sheet 211A is composed of the insulating layer 211 unhardened (semi-hardened material) impregnated into the substrate, and the insulating layer 211 of the board 2. Further, the metal layer 221A is a conductor pattern 221 for forming the wiring board 2, and is made of the same material as that of the conductor pattern 221. [2] Next, as shown in Fig. 4(b), through holes 100131022 46 201230259 2111 (interlayer holes) are formed in the prepreg sheet 211 . The method of forming the beton hole 2111 is not particularly limited, and can be formed, for example, by using a laser. Here, for example, a c〇2 laser, a UV_YAG laser, or the like can be used. Further, the through hole 211 can be formed, for example, by machining using a drill press or the like. [3] Next, as shown in Fig. 4(c), the conductor post 231 and the conductor pattern 225 are formed in the through hole 2111. The method for forming the conductor post 231 is not particularly limited, and for example, a method of filling a conductive paste, a method of embedding by electroless plating, a method of embedding by electrolytic plating, or the like can be used. Further, the method of forming the conductor pattern 225 is not particularly limited, and for example, a method of applying a conductive paste, a method of forming a film by electroless plating, or the like can be used. [4] Next, as shown in Fig. 4(d), the conductor pattern 221 is formed by patterning the metal layer 221A. The method of patterning is not particularly limited, and etching is preferably used. As described above, the insulating layer 211, the conductor pattern 221, and the conductor post 231 are formed. [5] Next, in the same manner as the above steps [1] to [4], prepare the insulating layer 212, 213, 214, 215 and the conductor patterns 222, 223, 224, respectively, by pre-100131022 47 201230259 dip sheet and metal The layered body is formed to form conductor patterns 222, 223, and 224 and conductor posts 232, 233, 234, and 235. Further, after the prepreg sheets for forming the insulating layers 211, 212, 213, 214, and 215 are laminated, the heat transfer columns 24 are formed by the same method as the conductor posts 231, 232, 233, 234, and 235. Then, hardening (complete hardening) is performed using the prepreg sheets forming the insulating layers 211, 212, 213, 214, 215, and as shown in Fig. 4(e), the wiring substrate 2 is obtained. The method of laminating the prepreg sheets for forming the insulating layers 211, 212, 213, 214, and 215 may be, for example, vacuum pressing, lamination, or the like. Among these, the joining method by vacuum pressing is preferred. Thereby, the adhesion strength of the prepreg for forming the insulating layers 211, 212, 213, 214, 215 can be improved. The method of using the prepreg to form the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, and for example, heat treatment can be suitably used. In addition, the formation of the heat conducting column 24 can also form heat conduction in the prepreg sheets for forming the insulating layers 211, 212, 213, 214, 215 while forming the respective conductor posts 231, 232, 233, 234, 235. The pillars are formed by laminating the prepreg sheets and joining the thermally conductive columns. [6] Next, after the insulating material 81A is applied to the lower surface of the wiring board 2, the metal balls (solder balls) 71A are solder-welded by solder reflow. Thereby, the metal bumps 71 and the insulating material 81 are formed. The solder joint is not particularly limited, and is disposed such that the lower surface of the wiring board 2 is in contact with each of the metal bumps 71 of 100131022 48 8 201230259, and in this state, heating is performed by, for example, 200 to 280 ° 〇 10 to 60 seconds. It can be implemented. Further, the insulating material 81A is formed by forming the insulating material 81, and is cured by, for example, heating.

' 在形成絕緣材81之際，例如圖4(f)所示，將絕緣材81A ' 塗佈於佈線基板2的下面，施行如前述之銲錫接合後，藉由 加熱使絕緣材81A硬化而獲得絕緣材81。When the insulating material 81 is formed, for example, as shown in FIG. 4(f), the insulating material 81A' is applied to the lower surface of the wiring board 2, and after the solder bonding as described above, the insulating material 81A is cured by heating. Insulating material 81.

依此所獲得之絕緣材81係如前述般依包圍金屬 B 周圍的方式形成。 此時’絕緣材81Α係在銲錫接合時具有助焊劑的機能， 且依利用與金屬球間之界面張力而環狀補強鲜錫接合 部周邊的形狀進行硬化。 [7] /、人如圖4(g)所示，在佈線基板2的下面接合第2補強 構件5 X ’在佈線基板2的上面塗佈填底材後，將半導體 兀件3由金屬凸塊31利用銲錫迴焊進行接合。另外，此 5冑底材係、使用與前述絕緣材81相同具助焊劑活性的 又亦可搭載半導體元件3，使用助焊劑或銲錫膏等 =1以使半導體元件3接合於佈線基板2之後，再使-般 ' 、力式填底材填充於佈線基板2與半導體元件3之間並 硬化。 再者在佈線基板2的上面，與前述金屬凸塊71與絕緣 100131022 49 201230259 材81的形成同樣的，形成金屬凸塊4〇〇A與絕緣材4〇1 ^ 然後’在半導體元件3與第〗補強構件4之間填充熱傳導 性材料6。 如上述便可獲得下層封裝5〇〇 [8] 其次，如圖4(h)所示，準備上層封裝3〇〇，經由金屬凸塊 400A(金屬凸塊400) ’將上層封裝3〇〇與下層封裝5〇〇利用 銲錫接合而接合。此時，若在無加壓狀態下施行接合，隨接 合後的金屬凸塊40G之冷卻，金屬凸塊働會朝厚度方向膨 脹’在上述接合後，可使上層封裝·的佈線基板3〇ι之下 面、與下層賴5G0的半導體元件3之上面成為遠離狀態。 另外’接合時’在上層封裝3⑻與下層封裝⑽之間配置間 隔物，於接合後，藉由移除該間隔物，亦可使經接 上 層封裝300的佈線基板301之下面、與下層封裂_的半導 體元件3之上面呈遠離狀態。此情 J在如前述配置間 隔物的狀態下，朝此二個封裝相互靠近的方向對該等進行加 壓。 依上述，可獲得半導體封裝i。 <第2實施形態> 其次，針對本發明第2實施形態進行說明。 圖5所不係本發明第2實施形態的半導體 立 圖。另夕卜，以下的說明中，為求說明上、:不意剖視 乃1更，將圖5中的 100131022 50 201230259 上側稱「上」，將下侧稱「下」。又，圖5中，為求說明上 方便，半導體封裝的各部位有誇張描繪情形。 、 处以下’針對第2實施形態的半導體封裝，以與前述實施形 態的不同處為中心進行說明，相關同樣的事項則省略說明: 另外，圖5中，相關與前述實施形態同樣的構成係賦予° 的元件符號。 第2實施形態的半導體封裝係除了補強構件（第1補強構 件）的構造不同之外，其餘均與第丨實施形態同樣。 如圖5所示，半導體封裝1A係上層封裝3〇〇與下層封裝 500A經由複數金屬凸塊4〇〇進行接合。 下層封裝500A係在佈線基板2的上面接合著第i補 件4A。 該第1補強構件4 A與基板21相反側的面（即上面），係位 於較半導體元件3與基板21相反側的面（即上面）更靠基板 21側（即下侧）。藉此，當製造半導體封裝i之際，於第ι 補強構件4A设置後才设置半導體元件3時，可使半導體元 件3的設置較為容易。 本實施形態中，第1補強構件4A的上面與佈線基板3〇1 的下面間之距離（即間隙S2的厚度方向長度)L2，係大於半 導體元件3的上面與佈線基板301的下面間之距離（即間隙 S1的厚度方向長度)L1。藉此，可透過在第】補強構件4A 與佈線基板301間所形成的間隙S2，有效率地進行通氣。 100131022 51 201230259 此種Ί補強構件4A的厚度與金屬凸塊3i的厚度之合 計厚度，T於半導體元件3的厚Lb，可簡單且確實 地形成如前述之間隙S2。 再者，將半導體元件3的厚度與金屬凸塊31的厚度之合 。十厚度a又為T1 ’將第i補強構件4a的厚度設為Τ2時，η 較佳係0.04以上且〇 96以下、更佳係〇 ι以上且㈧以下。 製造半導體封裝1之際，當於佈線基板2上接合著第1補強 構件4Α的狀態下設置半導體元件3日夺，可使料導體元件 3的設置(黏著作業)作業性優異。χ，亦可確保第i補強構 件4A必要的補強機能。 再者，第1補強構件4A與佈線基板301間之距離（即間隙 S2的厚度方向長度)L2，從確保如前述通氣的觀點而々，較 佳係0.015mm以上且〇.8mm以下。L2更佳係0 〇5mm以上 直0.5mm以下。 利用如上所έ兒明之第2實施形態的半導體封裝1 a，亦可 防止佈線基板2的翹曲，並可提高散熱性。 <第3實施形態> 其次’針對本發明第3實施形態進行說明。 圖6所示係本發明第3實施形態的半導體封装示音剖視 圖。另外，以下的說明中，為求說明上的方便，將圖6中的 為求說明上的 上側稱「上」，將下侧稱「下」。又，圖6中 方便’半導體封裝的各部位有誇張描繪情形。 100131022 52 ⑧ 201230259 以下，針對第3實施形態的半導體封装，以與前述實施带 態的不同處為中心進行說明，相關同樣的事項則省略說明: 另外，圖6中，相關與前述眘祐艰能 1貫鉍形態冋樣的構成係賦予相同 的元件符號。 第3實施形態的半導體封裝係除了省略第丄補強構件、導The insulating material 81 thus obtained is formed so as to surround the periphery of the metal B as described above. At this time, the insulating material 81 has a function of a flux during solder bonding, and is hardened by a shape that surrounds the vicinity of the joint portion of the fresh tin by the interfacial tension with the metal ball. [7] /, as shown in Fig. 4 (g), the second reinforcing member 5 X ' is bonded to the lower surface of the wiring board 2, and after the substrate is coated on the upper surface of the wiring board 2, the semiconductor element 3 is made of metal convex Block 31 is joined by solder reflow. In addition, the semiconductor element 3 may be mounted on the substrate having the same flux as the insulating material 81, and a flux, solder paste or the like may be used to make the semiconductor element 3 bonded to the wiring substrate 2, Further, a force-filled substrate is filled between the wiring board 2 and the semiconductor element 3 and hardened. Further, on the upper surface of the wiring substrate 2, the metal bumps 4A and the insulating material 4〇1 are formed in the same manner as the above-described metal bumps 71 and the insulating 100131022 49 201230259 material 81. Then, the semiconductor element 3 and the The heat conductive material 6 is filled between the reinforcing members 4. As described above, the lower package 5 〇〇 [8] can be obtained. Next, as shown in FIG. 4( h ), the upper package 3 准备 is prepared, and the upper package 3 〇〇 is formed via the metal bump 400A (metal bump 400 ) The lower package 5 is bonded by solder bonding. At this time, if the bonding is performed in a non-pressurized state, the metal bumps are expanded in the thickness direction in accordance with the cooling of the bonded metal bumps 40G. After the bonding, the wiring substrate 3 of the upper package can be packaged. The lower surface of the semiconductor element 3 below the lower layer 5G0 is in a state of being distant. In addition, a spacer is disposed between the upper package 3 (8) and the lower package (10) during the bonding, and after the bonding, the spacer and the lower layer of the wiring substrate 301 of the upper package 300 can be sealed by removing the spacer. The upper surface of the semiconductor element 3 is in a distant state. In this case, in the state in which the spacers are arranged as described above, the two packages are pressed toward each other in the direction in which they are close to each other. According to the above, the semiconductor package i can be obtained. <Second Embodiment> Next, a second embodiment of the present invention will be described. Fig. 5 is not a schematic view of a semiconductor according to a second embodiment of the present invention. In addition, in the following description, for the sake of explanation, it is not intended to be a cross-section, but the upper side of the 100131022 50 201230259 in FIG. 5 is referred to as "upper" and the lower side is referred to as "lower". Further, in Fig. 5, for convenience of explanation, each portion of the semiconductor package has an exaggerated drawing. In the following description of the semiconductor package of the second embodiment, the differences from the above-described embodiments will be mainly described, and the same matters will be omitted. In addition, in FIG. 5, the same configuration as that of the above-described embodiment is given. The symbol of the component. The semiconductor package of the second embodiment is the same as the third embodiment except that the structure of the reinforcing member (first reinforcing member) is different. As shown in FIG. 5, the semiconductor package 1A is an upper package 3A and a lower package 500A is bonded via a plurality of metal bumps 4A. The lower package 500A is bonded to the i-th complement 4A on the upper surface of the wiring board 2. The surface (i.e., the upper surface) of the first reinforcing member 4A on the opposite side to the substrate 21 is located closer to the substrate 21 side (i.e., the lower side) than the surface (i.e., the upper surface) of the semiconductor element 3 opposite to the substrate 21. Thereby, when the semiconductor package i is manufactured, when the semiconductor element 3 is provided after the first reinforcing member 4A is disposed, the semiconductor element 3 can be easily disposed. In the present embodiment, the distance between the upper surface of the first reinforcing member 4A and the lower surface of the wiring board 3〇1 (that is, the length in the thickness direction of the gap S2) L2 is larger than the distance between the upper surface of the semiconductor element 3 and the lower surface of the wiring board 301. (ie, the length in the thickness direction of the gap S1) L1. Thereby, ventilation can be efficiently performed through the gap S2 formed between the first reinforcing member 4A and the wiring board 301. 100131022 51 201230259 The total thickness of the thickness of the crucible reinforcing member 4A and the thickness of the metal bump 3i, T is the thickness Lb of the semiconductor element 3, and the gap S2 as described above can be formed simply and surely. Further, the thickness of the semiconductor element 3 is combined with the thickness of the metal bump 31. When the thickness of the i-th reinforcing member 4a is Τ2, the η is preferably 0.04 or more and 〇96 or less, more preferably 〇 or more and (eight) or less. When the semiconductor package 1 is manufactured, the semiconductor element 3 is placed in a state in which the first reinforcing member 4A is bonded to the wiring board 2, and the workability of the material conductor element 3 (adhesive work) can be excellent. χ, it can also ensure the necessary reinforcing function of the i-th reinforcing member 4A. In addition, the distance between the first reinforcing member 4A and the wiring board 301 (i.e., the length in the thickness direction of the gap S2) L2 is preferably 0.015 mm or more and 〇8 mm or less from the viewpoint of ensuring ventilation as described above. L2 is better than 0 〇 5mm or more and straight below 0.5mm. According to the semiconductor package 1a of the second embodiment as described above, it is possible to prevent warpage of the wiring board 2 and to improve heat dissipation. <Third Embodiment> Next, a third embodiment of the present invention will be described. Fig. 6 is a cross-sectional view showing the semiconductor package according to a third embodiment of the present invention. In the following description, for convenience of explanation, the upper side in FIG. 6 is referred to as "upper" and the lower side is referred to as "lower". Further, in Fig. 6, it is convenient that each part of the semiconductor package has an exaggerated drawing. 100131022 52 8 201230259 The semiconductor package of the third embodiment will be described focusing on the difference from the above-described embodiment, and the description of the same matters will be omitted. In addition, in FIG. 6, the related and the aforementioned cautions are difficult. The composition of the cross-section is given the same component symbol. The semiconductor package of the third embodiment is not limited to the third reinforcing member and the guide.

熱柱、熱傳導性材料及導熱凸塊之外，其餘均與第i實㈣ 態同樣。 V 如圖6所不’ +導體封農1B係上層封裝與下層封裝 500B，經由複數金屬凸塊4〇〇進行接合。 下層封裝500B係除了省略導熱柱24之外，其餘均具有 與前述第i實施形態的佈線基板2同樣構造之佈線基板 2B。在該佈線基板2B的下面上，接合著與前述第丨實施形 態的第2補強構件5同樣構造之補強構件5B。另一方面， 在佈線基板2B的上面，並未接合以佈線基板2B之補強作 為目的之補強構件。Except for the hot column, the thermally conductive material and the thermal conductive bump, the rest are the same as the i-th (four) state. V is as shown in Fig. 6. The conductor package 1B is an upper package and a lower package 500B, and is bonded via a plurality of metal bumps 4'. The lower package 500B has the wiring board 2B having the same structure as the wiring board 2 of the above-described i-th embodiment except that the heat transfer column 24 is omitted. On the lower surface of the wiring board 2B, a reinforcing member 5B having the same structure as the second reinforcing member 5 of the second embodiment described above is joined. On the other hand, on the upper surface of the wiring board 2B, the reinforcing member for the reinforcement of the wiring board 2B is not joined.

具有此種下層封裝500B的半導體封裝1B，可在佈線基板 2B上的半導體元件3周圍擴大佈線基板3〇1與佈線基板2B 間所形成的間隙。故，利用透過該間隙的通氣，亦可達半導 體元件3的有效率散熱效果。 藉由如上所說明第3實施形態的半導體封裝1B，亦可防 止佈線基板2B的翹曲，並可提高散熱性。 (半導體裝置） 100131022 53 201230259 其次，針對半導體裝置之製造方法及半導體裝置，根據較 佳實施形態進行說明。 圖7所示係本發明半導體裝置的實施形態一例之示意剖 視圖。 如圖7所示，半導體裝置1〇〇係具備有母板(基板)2〇〇、 與在該母板200上搭載的半導體封裝1。 此種半導體裝置10〇中，半導體封裝1的金屬凸塊71係 接合於母板200的端子201。藉此，半導體封裝i與母板2〇〇 電氣式連接，並在該等之間進行電氣信號的傳輸。又，經由 該接合部’可將半導體封裝1的熱發散至母板200。 再者，半導體封裝1的導熱凸塊91係接合於母板200的 散熱用端子。經由該接合部，可將半導體封裝1的熱有 效率地發散於母板200。當此種導熱凸塊91係由與前述金 屬凸塊71同樣的構成材料構成，便可在金屬凸塊71的接合 之同時，統括地對母板200施行接合。 根據依如上所說明的半導體裝置1 〇〇，因為可具備如前述 散熱性與可靠度均優異的半導體封裝1，故町靠度優異。 以上’針對本發明的半導體封裝及半導體裝置，根據圖示 實施形態進行說明，惟本發明並不僅侷限於該等。 例如前述實施形態中’第1補強構件4係依橫跨半導體元 件3全周而包圍之狀態設置’惟並不僅限定於此，例如亦可 形成半導體元件3周圍其中一部分有缺損的部分(缺口）。 100131022 54 201230259 再者’依照第1補強構件4的剛性、佈線基板2的厚度等， 亦可省略第2補強構件5。 再者，前述實施形態中，將第1補強構件4與第2補強構 件5相連接的熱傳部係使用貫通基板21的導熱柱24，但例 如亦可使用在基板21外側設置的熱傳構件（金屬構件）。此 情況，可使科熱性接著劑，將熱傳構件接 21、第1補強構件4與第2麵構件5,亦可為由基板t 的侧面側將基板21、第1補強構件4及第2補強構件5從 上下方向銜入的形態。 再者，在第1補強構件4中形成的開口部亦可非與各金屬 凸塊働一對一地對應。即，在第1補強構件4中’亦可依 相對於複數個金屬凸塊彻才對應i個的方式而形成開口 部。 再者，在第2補強構件5中形成的開口部亦可非與各金屬 凸塊71 ―對―地對應。即，在第2補強構件5中，亦可依 相對於複數個金屬凸塊71才對應i個的方式而形成開口部。 <第4實施形態> 口 其次，針對本發明第4實施形態進行說明。 圖8所示係本發明第4實施形態的半導體封裝示意剖視 圖。另外’以下的說明中’為求說明上的方便，將圖8中的 上側稱「上」，將下侧稱「下」。又，圖8中，為求說明上的 方便，半導賴裝的各部位有職描繪情形。 100131022 55 201230259 以下，針對第4實施形態的半導體封裝’以與前述實施形 態的不同處為中心進行說明，相關同樣的事項則省略說明。 另外，圖8中，相關與前述實施形態同樣的構成係碑予相同 的元件符號。 第4實施形態的半導體封裝係除了第1半導體元件與第2 佈線基板呈相接觸之外，其餘均與第1實施形態同樣。 (半導體封裝） 如圖8所示，因為半導體元件3與佈線基板301相接觸， 故可將半導體元件3的熱通過佈線基板301有效率地朝外發 散。 再者，各金屬凸塊400的大小（直徑)係設定為半導體元件 3與佈線基板301相接觸的程度。 [半導體元件] 上層封裝300的佈線基板301之下面，接觸到前述下層封 裝500的半導體元件3。本實施形態中，半導體元件3的上 面大致全域均接觸到佈線基板3〇1的下面。藉此，可將半導 體元件3的熱通過佈線基板观有效率地朝外發散。另外， 亦可半導體树3的上面其中-部分未接觸到佈線基板3〇1 的下面。 當半導體元件3與佈線基板3()1間形成有間隙的情況，該 間隙較佳係填“與前述熱傳導性材料6同樣的熱傳導性 材料(熱傳導性接著劑）。此情況，較佳係例如將半導體元件 100131022 ⑧ 56 201230259 3與佈線基板301經由熱傳導性材料進行接著。藉此，可簡 單且確實地使半導體元件3與佈線基板301間之熱傳導性為 優異。又，藉由使半導體元件3與佈線基板301進行接著， 可補強佈線基板301，可增加半導體封裝1的整體剛性。 再者’本實施形態中，如前述’因為半導體元件3的上面 與第1補強構件4的上面係位於同一面上，故佈線基板 的下面會接觸到前述下層封裝500的第1補強構件4之上面 (面接觸）。本實施形態中，第1補強構件4的上面幾乎全域 均接觸到佈線基板301的下面。依此，藉由第1補強構件4 對佈線基板301呈接觸，可經由第1補強構件4進行佈線基 板2與佈線基板301間之導熱。故，可使半導體封裝！的散 熱性優異。另外，亦可第1補強構件4的上面其中一部分未 接觸到佈線基板301的下面。 當第1補強構件4與佈線基板301間有形成間隙的情況， 較佳係在該間隙中填充著與前述熱傳導性材料6同樣的熱 傳導性材料(熱傳導性接著劑）。此情況，較佳係例如將第i 補強構件4與佈線基板301經由熱傳導性材料而進行接著。 藉此，可簡單且確實地使第丨補強構件4與佈線基板3〇1 間的熱傳導性優異。又’藉由使第i補強構件4與佈線基板 3〇1接著’佈線基板301亦可利用第丨補強構件4進行補強， 可增加半導體封裝1的整體剛性。 再者，因為半導體元件3與佈線基板3〇1相接 觸，故可將 100131022 57 201230259 半導元件3的熱通過佈線基板3 01而有效率地朝外發散。 (半導體封骏之製造方法） 如圖11(h)所示，準備上層封裝3〇〇，經由金屬凸塊 400Α(金屬凸塊4〇〇)，將上層封裝3〇〇與下層封裝5㈧利用 銲錫接合進行接合。此時，將上層封裝3〇〇與下層封裝 朝相互罪近的方向對該等加壓。藉此，在上述接合後，可使 上層封裝300的佈線基板301之下面、與下層封裝5〇〇的半 導體元件3之上面相接觸。 如上述便可獲得半導體封裝1。 <第5實施形態> 其次’針對本發明第5實施形態進行說明。 圖12所示係本發明第5實施形態的半導體封裝示意剖視 圖。又，圖12中，為求說明上的方便，半導體封裝的各部 位有誇張描繪情形。 以下，針對第5實施形態的半導體封裝，以與前述實施形 態的不同處為中心進行說明’相關同樣的事項則省略說明。 另外，圖12中，相關與前述實施形態同樣的構成係賦予相 同的元件符號。 第5實施形態的半導體封裝係除了第丨半導體元件與第2 佈線基板呈相接觸之外，其餘均與第2實施形態同樣。 如圖12所示，第丨補強構件4Α係餅佈線基板3〇1為非 接觸。藉此，可透過在第1補強構件4八與佈線基板3〇1間 100131022 58 201230259 形成的間隙s進行通氣。故，可使半導體封奘 衣的散熱性 優異。另外，第1補強構件4A亦可部分性具有對佈線美板 301接觸的部分。此情況’亦可在第1補強構件4八與佈線 基板301之間形成用以通氣的間隙。 •此種第1補強構件4A的厚度係薄於半導體元件3的厚产 • 與金屬凸塊31的厚度之合計厚度。藉此，可簡單且確實地 形成前述之間隙S。 再者’第1補強構件4A與佈線基板301間的距離（即間隙 S的厚度方向長度)L ’從確保如前述通氣的觀點而言，較佳 係0.02mm以上且0.5mm以下左右。 <第6實施形態> 其次，針對本發明第6實施形態進行說明。 圖13所示係本發明第6實施形態的半導體封裝示意剖視 圖。又’圖13中，為求說明上的方便’半導體封震的各部 位有誇張描繪情形。 以下，針對第6實施形態的半導體封裝，以與前述實施形 ‘ 良的不同處為中心進行說明，相關同樣的事項則省略說明。 另外，圖13中，相關與前述實施形態同樣的構成係賦予相 同的元件符號。 第6 A知*形態的半導體封農係除了第1半導體元件與第2 佈線基板為相接觸之外，其餘均與第3實施形態同樣。 (半導體裝置） 100131022 59 201230259 圖14所示係本發明半導體裝置的實施形態一例示意剖視 圖。 如圖14所示，半導體裝置1〇〇係具備有母板(基板)2〇〇 與格載於s亥母板2〇〇上的半導體封裝1。 (產業上之可利用性） 本發明可提供能防止因熱而造成不良情況發生的半導體 封裝及半導體裝置。 【圖式簡單說明】 圖1係本發明第1實施形態的半導體封裝示意剖視圖。 圖2係圖1所示半導體封裝所具備之下層封裝的俯視圖。 圖3係圖1所示半導體封裝所具備之下層封裝的底視圖。 圖4係圖1所示半導體封裝的製造方法一例圖。 圖5係本發明第2實施形態的半導體封裝示意剖視圖。 圖6係本發明第3實施形態的半導體封裝示意剖視圖。 圖7係本發明半導體裝置的實施形態一例示意剖視圖。 圖8係本發明第4實施形態的半導體封裝示意剖視圖。 圖9係圖8所示半導體封裝所具備之下層封裝的俯視圖。 圖10係圖8所示半導體封裝所具備之下層封裝的底視圖。 圖11係圖8所示半導體封裝的製造方法一例圖。 圖12係本發明第5實施形態的半導體封裝示意剖視圖。 圖13係本發明第6實施形態的半導體封裝示意剖視圖。 圖14係本發明半導體裝置的實施形態一例示意剖視圖。 100131022 60 201230259 【主要元件符號說明】 1 半導體封裝 1A 半導體封裝 1B 半導體封裝 2 佈線基板 3 半導體元件 4A 第1補強構件 4 第1補強構件 5 第2補強構件 5B 補強構件 6 熱傳導性材料 21 基板 24 導熱柱 31 金屬凸塊 32 接著層 33 外周面 41 内周面 42 開口部 51 開口部 52 部分 53 部分 71 金屬凸塊 100131022 61 金屬球 絕緣材 絕緣材 導熱凸塊 半導體裝置 母板 端子 端子 絕緣層 預浸片 絕緣層 絕緣層 絕緣層 絕緣層 導體圖案 金屬層 導體圖案 金屬層 導體圖案 導體圖案 導體圖案 導體柱 62 201230259 232 導體柱 233 導體柱 234 導體柱 300 上層封裝 301 佈線基板 302 基板 303 絕緣層 304 絕緣層 305 半導體元件 306 金屬絲線 307 密封部 308 導體圖案 400 金屬凸塊 400A 金屬凸塊 401 絕緣材 500 下層封裝 500A 下層封裝 500B 下層封裝 600 上層封裝 2111 貫通孔 S 間隙 SI 間隙 100131022 63 201230259 S2 T2 間隙厚度 100131022In the semiconductor package 1B having such a lower package 500B, a gap formed between the wiring substrate 3〇1 and the wiring substrate 2B can be enlarged around the semiconductor element 3 on the wiring substrate 2B. Therefore, the efficient heat dissipation effect of the semiconductor element 3 can be achieved by the ventilation through the gap. According to the semiconductor package 1B of the third embodiment, the warpage of the wiring board 2B can be prevented, and heat dissipation can be improved. (Semiconductor device) 100131022 53 201230259 Next, a method of manufacturing a semiconductor device and a semiconductor device will be described based on a preferred embodiment. Fig. 7 is a schematic cross-sectional view showing an example of an embodiment of a semiconductor device of the present invention. As shown in FIG. 7, the semiconductor device 1 is provided with a mother board (substrate) 2A and a semiconductor package 1 mounted on the mother board 200. In such a semiconductor device 10, the metal bumps 71 of the semiconductor package 1 are bonded to the terminals 201 of the mother board 200. Thereby, the semiconductor package i is electrically connected to the motherboard 2, and electrical signals are transmitted between the two. Further, the heat of the semiconductor package 1 can be dissipated to the mother board 200 via the bonding portion'. Further, the heat transfer bump 91 of the semiconductor package 1 is bonded to the heat dissipation terminal of the mother board 200. The heat of the semiconductor package 1 can be efficiently dissipated to the mother board 200 via the joint portion. When the heat transfer bumps 91 are made of the same constituent material as the metal bumps 71, the mother pads 200 can be integrally joined while the metal bumps 71 are joined. According to the semiconductor device 1 described above, the semiconductor package 1 having excellent heat dissipation and reliability as described above can be provided, and thus the susceptibility is excellent. The semiconductor package and the semiconductor device of the present invention have been described above based on the embodiments shown in the drawings, but the present invention is not limited thereto. For example, in the above-described embodiment, the first reinforcing member 4 is provided in a state of being surrounded by the entire circumference of the semiconductor element 3, and is not limited thereto. For example, a portion (notch) in which a part of the semiconductor element 3 is defective may be formed. . 100131022 54 201230259 Further, the second reinforcing member 5 may be omitted in accordance with the rigidity of the first reinforcing member 4, the thickness of the wiring board 2, and the like. In the above embodiment, the heat transfer portion that connects the first reinforcing member 4 and the second reinforcing member 5 uses the heat transfer column 24 that penetrates the substrate 21. However, for example, a heat transfer member provided outside the substrate 21 may be used. (Metal components). In this case, the heat transfer member may be connected to the heat transfer member 21, the first reinforcement member 4, and the second surface member 5, or the substrate 21, the first reinforcement member 4, and the second substrate may be provided on the side surface side of the substrate t. The form in which the reinforcing member 5 is engaged from the vertical direction. Further, the openings formed in the first reinforcing member 4 may not correspond to the respective metal bumps one-to-one. In other words, in the first reinforcing member 4, the opening portion may be formed so as to correspond to the plurality of metal bumps. Further, the opening formed in the second reinforcing member 5 may not correspond to the respective metal bumps 71. In other words, in the second reinforcing member 5, the opening portion may be formed in such a manner that one of the plurality of metal bumps 71 corresponds to one. <Fourth Embodiment> Port Next, a fourth embodiment of the present invention will be described. Fig. 8 is a schematic cross-sectional view showing a semiconductor package in accordance with a fourth embodiment of the present invention. In the following description, for convenience of explanation, the upper side in Fig. 8 is referred to as "upper" and the lower side is referred to as "lower". Further, in Fig. 8, for the sake of convenience in explanation, each part of the semi-guided device is in a position to be drawn. 100131022 55 201230259 The semiconductor package ′ according to the fourth embodiment will be described focusing on differences from the above-described embodiments, and the description of the same matters will be omitted. In addition, in FIG. 8, the same components as those of the above-described embodiment are denoted by the same reference numerals. The semiconductor package of the fourth embodiment is the same as the first embodiment except that the first semiconductor element and the second wiring substrate are in contact with each other. (Semiconductor Package) As shown in Fig. 8, since the semiconductor element 3 is in contact with the wiring board 301, the heat of the semiconductor element 3 can be efficiently radiated outward through the wiring board 301. Further, the size (diameter) of each of the metal bumps 400 is set to such an extent that the semiconductor element 3 is in contact with the wiring substrate 301. [Semiconductor Element] The lower surface of the wiring substrate 301 of the upper package 300 is in contact with the semiconductor element 3 of the lower layer package 500. In the present embodiment, the upper surface of the semiconductor element 3 is substantially in contact with the lower surface of the wiring board 3〇1. Thereby, the heat of the semiconductor element 3 can be efficiently dissipated outward through the wiring substrate. Alternatively, the upper portion of the semiconductor tree 3 may not be in contact with the underside of the wiring substrate 3〇1. When a gap is formed between the semiconductor element 3 and the wiring board 3 (1), the gap is preferably "the same heat conductive material (thermal conductive adhesive) as the heat conductive material 6. In this case, for example, it is preferable to The semiconductor element 100131022 8 56 201230259 3 and the wiring board 301 are connected via a thermally conductive material. Thereby, the thermal conductivity between the semiconductor element 3 and the wiring board 301 can be easily and surely made excellent. Further, by making the semiconductor element 3 In addition to the wiring board 301, the wiring board 301 can be reinforced, and the overall rigidity of the semiconductor package 1 can be increased. In the present embodiment, the above is the same as the upper surface of the first reinforcing member 4. On the surface, the lower surface of the wiring board contacts the upper surface (surface contact) of the first reinforcing member 4 of the lower package 500. In the present embodiment, the upper surface of the first reinforcing member 4 is almost entirely in contact with the lower surface of the wiring substrate 301. With this, the first reinforcing member 4 comes into contact with the wiring board 301, and the wiring board 2 and the wiring board 301 can be made via the first reinforcing member 4. In addition, the heat dissipation of the semiconductor package can be excellent. Further, a part of the upper surface of the first reinforcing member 4 may not be in contact with the lower surface of the wiring board 301. When the first reinforcing member 4 and the wiring substrate 301 are provided In the case where a gap is formed, it is preferable that the gap is filled with a heat conductive material (thermal conductive adhesive) similar to the heat conductive material 6. In this case, for example, the i-th reinforcing member 4 and the wiring substrate 301 are preferably passed through, for example. The heat conductive material is subsequently used. Thereby, the thermal conductivity between the second reinforcing member 4 and the wiring board 3〇1 can be easily and surely obtained. Further, by the ith reinforcing member 4 and the wiring substrate 3〇1 The wiring board 301 can be reinforced by the second reinforcing member 4, and the overall rigidity of the semiconductor package 1 can be increased. Further, since the semiconductor element 3 is in contact with the wiring board 3〇1, the 100131022 57 201230259 semi-conductive element 3 can be used. The heat is efficiently dissipated outward through the wiring substrate 301. (Manufacturing Method of Semiconductor Seal) As shown in FIG. 11(h), the upper package 3A is prepared via the metal bump 40. 0 Α (metal bump 4 〇〇), the upper package 3 〇〇 and the lower package 5 (8) are joined by solder bonding. At this time, the upper package 3 〇〇 and the lower package are pressed in a direction close to each other. Thereby, after the bonding, the lower surface of the wiring substrate 301 of the upper package 300 can be brought into contact with the upper surface of the semiconductor element 3 of the lower package 5. The semiconductor package 1 can be obtained as described above. > Next, a fifth embodiment of the present invention will be described. Fig. 12 is a schematic cross-sectional view showing a semiconductor package according to a fifth embodiment of the present invention. Further, in Fig. 12, for the convenience of explanation, each part of the semiconductor package has Exaggerated depiction of the situation. In the semiconductor package of the fifth embodiment, the description will be given focusing on the differences from the above-described embodiment. In Fig. 12, the same components as those of the above-described embodiment are denoted by the same reference numerals. The semiconductor package of the fifth embodiment is the same as the second embodiment except that the second semiconductor element and the second wiring substrate are in contact with each other. As shown in Fig. 12, the second reinforcing member 4 is not in contact with the cake wiring substrate 3〇1. Thereby, ventilation can be performed through the gap s formed between the first reinforcing member 4 8 and the wiring board 3〇1, 100131022 58 201230259. Therefore, the semiconductor package can be excellent in heat dissipation. Further, the first reinforcing member 4A may partially have a portion in contact with the wiring board 301. In this case, a gap for ventilation may be formed between the first reinforcing member 4 and the wiring board 301. The thickness of the first reinforcing member 4A is thinner than the thickness of the semiconductor element 3 and the thickness of the metal bump 31. Thereby, the aforementioned gap S can be formed simply and surely. Further, the distance between the first reinforcing member 4A and the wiring board 301 (i.e., the length in the thickness direction of the gap S) L' is preferably 0.02 mm or more and 0.5 mm or less from the viewpoint of ensuring ventilation. <Sixth Embodiment> Next, a sixth embodiment of the present invention will be described. Fig. 13 is a schematic cross-sectional view showing a semiconductor package in accordance with a sixth embodiment of the present invention. Further, in Fig. 13, for convenience of explanation, the respective portions of the semiconductor shock are exaggeratedly drawn. In the semiconductor package of the sixth embodiment, the differences from the above-described embodiment will be mainly described, and the description of the same matters will be omitted. In addition, in Fig. 13, the same components as those of the above-described embodiment are denoted by the same reference numerals. The semiconductor sealing system of the sixth aspect is the same as the third embodiment except that the first semiconductor element and the second wiring substrate are in contact with each other. (Semiconductor device) 100131022 59 201230259 Fig. 14 is a schematic cross-sectional view showing an embodiment of a semiconductor device of the present invention. As shown in FIG. 14, the semiconductor device 1 is provided with a mother package (substrate) 2A and a semiconductor package 1 mounted on a s- mother board 2A. (Industrial Applicability) The present invention can provide a semiconductor package and a semiconductor device capable of preventing occurrence of defects due to heat. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a semiconductor package according to a first embodiment of the present invention. 2 is a top plan view of the underlying package of the semiconductor package shown in FIG. 1. 3 is a bottom view of the underlying package of the semiconductor package shown in FIG. 1. 4 is a view showing an example of a method of manufacturing the semiconductor package shown in FIG. 1. Fig. 5 is a schematic cross-sectional view showing a semiconductor package according to a second embodiment of the present invention. Fig. 6 is a schematic cross-sectional view showing a semiconductor package according to a third embodiment of the present invention. Fig. 7 is a schematic cross-sectional view showing an embodiment of a semiconductor device of the present invention. Fig. 8 is a schematic cross-sectional view showing a semiconductor package according to a fourth embodiment of the present invention. 9 is a top plan view of the underlying package of the semiconductor package shown in FIG. 8. FIG. 10 is a bottom view of the underlying package of the semiconductor package shown in FIG. 8. FIG. Fig. 11 is a view showing an example of a method of manufacturing the semiconductor package shown in Fig. 8. Figure 12 is a schematic cross-sectional view showing a semiconductor package according to a fifth embodiment of the present invention. Figure 13 is a schematic cross-sectional view showing a semiconductor package in a sixth embodiment of the present invention. Fig. 14 is a schematic cross-sectional view showing an embodiment of a semiconductor device of the present invention. 100131022 60 201230259 [Description of main components] 1 Semiconductor package 1A Semiconductor package 1B Semiconductor package 2 Wiring board 3 Semiconductor component 4A First reinforcing member 4 First reinforcing member 5 Second reinforcing member 5B Reinforcing member 6 Thermal conductive material 21 Substrate 24 Heat conduction Column 31 Metal bump 32 Next layer 33 Outer peripheral surface 41 Inner peripheral surface 42 Opening portion 51 Opening portion 52 Part 53 Part 71 Metal bump 100131022 61 Metal ball insulation material Thermal conductive bump Semiconductor device Mother board terminal terminal Insulation layer prepreg Sheet insulation layer insulation layer insulation layer conductor pattern metal layer conductor pattern metal layer conductor pattern conductor pattern conductor pattern conductor post 62 201230259 232 conductor post 233 conductor post 234 conductor post 300 upper layer package 301 wiring substrate 302 substrate 303 insulating layer 304 insulation layer 305 Semiconductor component 306 Metal wire 307 Sealing part 308 Conductor pattern 400 Metal bump 400A Metal bump 401 Insulator 500 Lower package 500A Lower package 500B Lower package 600 Upper package 2111 Through hole S Clearance gap SI 100131022 63 201230259 S2 T2 gap thickness 100 131 022

Claims (1)

201230259 七、申請專利範圍： 1.一種半導體封裝，係具備有： 第1佈線基板； ψ 第1半導體70件，其係接合於上述第1佈線基板其中-面； 補強構件’其係接合於上述第i佈線基板靠上述第i半導 體元件側的面未接合上述第1半導體元件的部分處，且執膨 脹係數小於上述第1佈線基板； 上述補強構件設置在與上述第 個以上之金屬凸塊而接合於上 第2佈線基板，其係相對於 1佈線基板相反側，且經由2 述第1佈線基板；以及 第2半導體元件，其择垃 1糸接合於上述第2佈線基板與上述第 1佈線基板相反側的面丨 上述第1半導體元件係對上述第2佈祕板呈非接觸 2 -種半導體封I係具備有： 第1佈線基板； 第1半導體元件，其传技 节接合於上述第1佈線基板其中一面； 補強構件，其係接合於★结 、上迷第1佈線基板靠上述第1半導 體元件側的面未接合上丨水# I第1半導體元件的部分處，且熱膨 脹係數小於上述第1佈線基^反； ' 對於上述補強構件設置在與上述第 由2個以上之金屬凸塊而接合於上 第2佈線基板’其係冲目 1佈線基板相反側，且經 述第1佈線基板；以及 100131022 65 201230259 第2半導體元件，其係接合於上述第2佈線基板與上述第 1佈線基板相反側的面； 上述第1半導體元件係對上述第2佈線基板呈接觸。 3. —種半導體封裝，係具備有： 第1佈線基板； 第1半導體元件，其係接合於上述第1佈線基板其中一面； 補強構件，其係接合於上述第1佈線基板與上述第1半導 體元件相反側的面，且熱膨脹係數小於上述第1佈線基板； 第2佈線基板，其係相對於上述第1半導體元件設置在與 上述第1佈線基板相反側，且經由2個以上之金屬凸塊而接 合於上述第1佈線基板；以及 第2半導體元件，其係接合於上述第2佈線基板與上述第 1佈線基板相反側的面； 上述第1半導體元件係對上述第2佈線基板呈非接觸。 4. 一種半導體封裝，係具備有： 第1佈線基板； 第1半導體元件，其係接合於上述第1佈線基板其中一面； 補強構件，其係接合於上述第1佈線基板與上述第1半導 體元件相反側的面，且熱膨脹係數小於上述第1佈線基板； 第2佈線基板，其係相對於上述第1半導體元件設置在與 上述第1佈線基板相反側，且經由2個以上金屬凸塊而接合 於上述第1佈線基板；以及 100131022 66 ⑧ 201230259 第2半導體元件’其係接合於 1佈線基板相反側的面； 上述苐2佈線基板與上述第 上述第1半導體元件係對上述第2佈線基板呈接 5.-種半導體封裝’係具備有： 第1佈線基板； 第1半導體7L件，其係接合於上述第i佈線基板其中一面； 第1補強構件，其係接合於上述第i佈線基板靠上述第1 半導體糾側的面未接合上述第1半導體元件的部分處，且 熱膨脹係數小於上述第1佈線基板； 第2補強構件，其係接合於上述第i佈線基板與上述第1 半導體元件相反側的面，且熱膨脹係數小於上述第i佈線基 板； 第2佈線基板，其係相對於上述第1觀構件設置在與上 述第1佈線基板相反側’且經由2個以上之金屬凸塊而接合 於上述第1佈線基板；以及 第2半導體元件，其係接合於上述第2佈線基板與上述第 1佈線基板相反側的面； 上述第1半導體元件係對上述第2佈線基板呈非接觸。 6.—種半導體封裝’係具備有： 第1佈線基板； 第工半導體元件，其係接合於上述^佈線基板其中一面； 第1補強構件’其係接合於上述第i舞基板靠上述第1 100131022 67 201230259 半導體元件侧的面未接合上述第1半導體元件的部分處，且 熱膨脹係數小於上述第1佈線基板； 第2補強構件，其係接合於上述第i佈綠基板與上述第i 半導體元件相反侧的面’且熱膨脹係數小於上述第1佈線其 板； . 第2佈線基板，其係相對於上述第1補強構件設置在與上 „ 述第1佈線基板相反側，且經由2個以上之金屬凸塊而接合 於上述第1佈線基板；以及 第2半導體元件，其係接合於上述第2佈線基板與上述第 1佈線基板相反側的面； 上述第1半導體元件係對上述第2佈線基板呈接觸。 7·如申請專利範圍第5或6項之半導體封裝，其中，上述 第1補強構件係形成包圍上述第1半導體元件周_形狀。 8.如申請專利範圍第卜3、5及7項中任一項之半導體封 裝’其中’上4第1半導體元件與上述第2佈線基板間之距 離係0.01mm以上且〇 8mm以下。 9·如申μ專利圍第5至8項中任—項之半導體封裝，其 V 中，上述第1補強構件係對上述第2佈線基板呈非接觸。 10.如申請專利範圍第6或7項之半導體封裝，其中，上 述第1補強構件係對上述第2佈線基板呈接觸。 11·如申請專利範圍帛9項之半導體封裝，其中，上述第1 補強構件與上述第2佈線基板間之距離，係大於上述第1 100131022 ⑧ 68 201230259 半導體元件與上述第2佈線基板間之距離。 12. 如申请專利範圍第5至n項中任一項之半導體封裝， 其中’上述第1補強構件係具有依對上述各金屬凸塊呈非接 觸且包圍上述各金屬凸塊之方式形成的2個以上開口部。 13. 如申請專利範圍第5至12項中任一項之半導體封裝， 其中’在上述第1補強構件與上述各金屬凸塊之間設有絕緣 材。 14. 如申請專利範圍第5至13射任—項之半導體封裳， 其中，上述第1補強構件與上述第2補強構件分別與上述第 1半導體元件間之熱膨脹係數差在7ppm/t：以下。 15. 如申μ專利範圍第5至14項中任—項之半導體封裝， 其中’上述第1補強構件與上述第2補強構件分別係形成板 如申請專利範圍第 q π d 土 U ·*·貝甲仕一項之半導體封裝， 其中，上述第1補強構件與上述第2補強構件分別係由金屬 材料構成。 17.如申請專利範圍第16項之半導體封裝，其中，上述金 屬材料係Fe-Ni系合金。 種半導收裝置，係具備有申請專利範圍第i至^項 中任一項之半導體封裝。 、 ^-種半導體料之製造方法，料導體龍係申請專 利乾圍第丨至17項中任—項之半導體封裝；該製造方法包 100131022 69 201230259 括有： 將第1補強構件接合於第1佈線基板的步驟； 將第1半導體元件接合於上述第1佈線基板，而形成下層 封裝的步驟； 將第2半導體元件接合於第2佈線基板，而形成上層封裝 的步驟；以及 經由2個以上之金屬凸塊，將上述上層封裝與上述下層封 裝予以接合的步驟。 20. —種半導體封裝之製造方法，該半導體封裝係申請專 利範圍第1至17項中任一項之半導體封裝；該製造方法包 括有： 將第2補強構件接合於第1佈線基板的步驟； 在上述第1佈線基板與上述第2補強構件相反側的面，接 合第1半導體元件而形成下層封裝的步驟； 將第2半導體元件接合於第2佈線基板，而形成上層封裝 的步驟；以及 經由2個以上之金屬凸塊，將上述上層封裝與上述下層封 裝予以接合的步驟。 21. —種半導體封裝之製造方法，該半導體封裝係申請專 利範圍第1至17項中任一項之半導體封裝；該製造方法包 括有： 將第1補強構件接合於第1佈線基板的步驟； 100131022 70 ⑧ 201230259 將第2補強構件接合於上述第1佈線基板的步驟； 在上述第1佈線基板與上述第2補強構件相反側的面，接 合第1半導體元件而形成下層封裝的步驟； 麝 將第2半導體元件接合於第2佈線基板，而形成上 的步驟；以及 衣 絰由2個以上之金屬凸塊，將上述上層封裳與上述下 裝予以接合的步驟。 97 、、22·如中請專利範圍第19《21項之半導體封裝之製造方 法’其中’將第1補強構件接合於上述第1佈線基板的步驟， 係包括有： 準備金屬層與預浸片的積層體，並在上述積層體的預浸片 側之面接合第1補強構件的副步驟； 在上述預次片中形成貫通孔的副步驟； 在上述貫通孔中形成導體柱的副步驟； 藉由對上述至屬層施行圖案化而形成導體圖案的副步 驟；以及 使上述預浸片硬化的副步驟。 申請專利範圍第19至22項中任—項之半導體封展 之製造方法’其中，隨上述金屬凸塊的冷卻，上述金屬凸塊 係朝厚度方向祕，使上述±層封裝的第2佈線基板與上述 下層封裝的第1半導體元件成為遠離之狀態。 从如申請專利範圍第19至22項中任一項之半導體封裝 100131022 201230259 之 .製造方法，其中’在上述上層封裝與 置間隔物，並在上述上層封裝與上述下層^下層封裝之間配 由移除上賴隔物，而使上述上層封日料之接合後，藉 述下層封裝的第i半導體元件成為遠離之狀離。線基板與上 2 5.如申請專利範圍第19至2 2項中任一狀 之製造方法，其中，朝上 、V體封裴 近之方向，料等/ 展與上述下層封袭互相靠 鱼上述下μ 4壓’而使上述上層封裝的第2佈唆其4 ㈣⑷半恤件成綱之狀態基板 100131022 72 201230259 四、指定代表圖： (一) 本案指定代表圖為：第（1 )圖。 (二) 本代表圖之元件符號簡單說明： 1 半導體封裝 2 佈線基板 3 半導體元件 4 第1補強構件 5 第2補強構件 6 熱傳導性材料 21 基板 24 導熱柱 31 金屬凸塊 32 接著層 51 開口部 71 金屬凸塊 81 絕緣材 91 導熱凸塊 211 絕緣層 212 絕緣層 213 絕緣層 214 絕緣層 215 絕緣層 221 導體圖案 222 導體圖案 223 導體圖案 224 導體圖案 225 導體圖案 231 導體柱 232 導體柱 233 導體柱 234 導體柱 300 上層封裝 301 佈線基板 302 基板 303 絕緣層 304 絕緣層 305 半導體元件 306 金屬絲線 307 密封部 308 導體圖案 400 金屬凸塊 401 絕緣材 500 下層封裝 S1 間隙 S2 間隙 五、本案若有化學式時，請揭示最能顯示發明特徵的化學式： 無 100131022 3201230259 VII. Patent application scope: 1. A semiconductor package comprising: a first wiring substrate; ψ a first semiconductor 70 bonded to a surface of the first wiring substrate; and a reinforcing member s bonded thereto a portion of the i-th wiring substrate on which the surface on the i-th semiconductor element side is not bonded to the first semiconductor element, and an expansion coefficient is smaller than the first wiring substrate; and the reinforcing member is provided on the first or more metal bumps The second wiring substrate is bonded to the second wiring substrate, and is connected to the second wiring substrate and the first wiring via the first wiring substrate and the second semiconductor device. The first semiconductor element is provided on the opposite side of the substrate, and the second secret element is provided in a non-contact type. The semiconductor device is provided with a first semiconductor substrate, and the first semiconductor element is bonded to the first semiconductor element. One of the wiring boards; the reinforcing member is joined to the first junction, and the first wiring substrate is not bonded to the surface of the first semiconductor element; a portion of the conductor element having a thermal expansion coefficient smaller than that of the first wiring substrate; 'the reinforcing member is provided on the second and second wiring substrates in combination with the second or more metal bumps' The second semiconductor element is bonded to the surface of the second wiring substrate opposite to the first wiring substrate, and the first semiconductor element is opposite to the first semiconductor substrate, and the first semiconductor substrate, 100131022 65 201230259 The second wiring substrate is in contact. 3. A semiconductor package comprising: a first wiring substrate; a first semiconductor element bonded to one of the first wiring substrates; and a reinforcing member bonded to the first wiring substrate and the first semiconductor a surface on the opposite side of the element and having a thermal expansion coefficient smaller than the first wiring substrate; and a second wiring substrate provided on the opposite side of the first wiring substrate from the first semiconductor element and having two or more metal bumps And bonding to the first wiring substrate; and the second semiconductor element is bonded to a surface of the second wiring substrate opposite to the first wiring substrate; and the first semiconductor element is non-contact with the second wiring substrate . A semiconductor package comprising: a first wiring substrate; a first semiconductor element bonded to one of the first wiring substrates; and a reinforcing member bonded to the first wiring substrate and the first semiconductor element The surface on the opposite side has a thermal expansion coefficient smaller than that of the first wiring substrate, and the second wiring substrate is provided on the opposite side of the first wiring substrate from the first semiconductor element, and is bonded via two or more metal bumps. The first semiconductor substrate and the first semiconductor device are bonded to a surface on the opposite side of the one wiring substrate, and the second wiring substrate and the first semiconductor device are paired with the second wiring substrate. The fifth semiconductor package includes: a first wiring substrate; a first semiconductor 7L that is bonded to one of the ith wiring substrates; and a first reinforcing member that is bonded to the ith wiring substrate The surface of the first semiconductor correction side is not joined to the first semiconductor element, and the thermal expansion coefficient is smaller than the first wiring substrate; a strong member that is bonded to a surface of the ith wiring substrate opposite to the first semiconductor element and has a thermal expansion coefficient smaller than the ith wiring substrate; and a second wiring substrate that is provided to the first viewing member The first wiring substrate is bonded to the first wiring substrate via two or more metal bumps on the opposite side of the first wiring substrate; and the second semiconductor element is bonded to the second wiring substrate on the opposite side of the first wiring substrate The first semiconductor element is in non-contact with respect to the second wiring substrate. 6. The semiconductor package is characterized in that: the first wiring substrate; the semiconductor device is bonded to one of the wiring substrates; and the first reinforcing member is bonded to the first dance substrate by the first 100131022 67 201230259 The semiconductor element side surface is not joined to the first semiconductor element, and the thermal expansion coefficient is smaller than the first wiring substrate; and the second reinforcing member is bonded to the ith green substrate and the ith semiconductor element The surface on the opposite side and the coefficient of thermal expansion is smaller than the plate of the first wiring; the second wiring board is provided on the opposite side of the first wiring substrate with respect to the first reinforcing member, and passes through two or more a metal bump is bonded to the first wiring substrate; and a second semiconductor element is bonded to a surface of the second wiring substrate opposite to the first wiring substrate; and the first semiconductor element is paired with the second wiring substrate The semiconductor package of claim 5, wherein the first reinforcing member is formed to surround the first semiconductor element 8. The semiconductor package of any one of the fourth semiconductor device of the above-mentioned fourth aspect, wherein the distance between the first semiconductor element and the second wiring substrate is 0.01 mm or more and 〇 The semiconductor package of any one of the items of the fifth aspect of the invention, wherein the first reinforcing member is in non-contact with the second wiring substrate. The semiconductor package of the sixth or seventh aspect, wherein the first reinforcing member is in contact with the second wiring substrate. The semiconductor package according to claim 9 wherein the first reinforcing member and the second wiring are The distance between the substrates is greater than the distance between the semiconductor device and the second wiring substrate. The semiconductor package according to any one of claims 5 to n, wherein the first The reinforcing member has two or more openings formed so as to be in contact with each of the metal bumps and to surround the metal bumps. 13. The semiconductor package according to any one of claims 5 to 12,Wherein the insulating material is provided between the first reinforcing member and each of the metal bumps. 14. The semiconductor sealing body of the fifth to the third aspect of the patent application, wherein the first reinforcing member and the first The difference in thermal expansion coefficient between the reinforcing member and the first semiconductor element is 7 ppm/t or less. 15. The semiconductor package according to any one of claims 5 to 14, wherein the first reinforcing member is Each of the second reinforcing members is formed of a semiconductor package according to the patent application scope q π d soil U ·*·Beijiashi, wherein the first reinforcing member and the second reinforcing member are respectively made of a metal material. . 17. The semiconductor package of claim 16, wherein the metal material is an Fe-Ni alloy. A semi-conducting device is provided with a semiconductor package according to any one of claims 1 to 4. , the manufacturing method of the semiconductor material, the semiconductor package of the material conductor dragon system patent 干 丨 丨 丨 17 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体a step of wiring the substrate; a step of bonding the first semiconductor element to the first wiring substrate to form a lower package; a step of bonding the second semiconductor element to the second wiring substrate to form an upper package; and passing two or more a metal bump for bonding the upper package and the lower package. A semiconductor package according to any one of claims 1 to 17, wherein the manufacturing method comprises: a step of bonding a second reinforcing member to the first wiring substrate; a step of forming a lower layer package by bonding the first semiconductor element on a surface of the first wiring substrate opposite to the second reinforcing member; a step of bonding the second semiconductor element to the second wiring substrate to form an upper layer package; and Two or more metal bumps are used to join the upper package and the lower package. A semiconductor package according to any one of claims 1 to 17, wherein the manufacturing method comprises: a step of bonding the first reinforcing member to the first wiring substrate; 100131022 70 8 201230259 The step of bonding the second reinforcing member to the first wiring board; and the step of bonding the first semiconductor element to the surface of the first wiring board opposite to the second reinforcing member to form a lower layer package; a step of forming a second semiconductor element bonded to the second wiring substrate to form an upper portion; and a step of bonding the upper layer sealing member to the lower package by two or more metal bumps. 97, 22, and the method of manufacturing a semiconductor package of the 19th aspect of the invention, wherein the step of bonding the first reinforcing member to the first wiring substrate includes: preparing a metal layer and a prepreg a sub-step of joining the first reinforcing member on the surface of the prepreg side of the laminated body; a sub-step of forming a through-hole in the pre-stage; and a sub-step of forming a conductor post in the through-hole; a sub-step of forming a conductor pattern by patterning the above-mentioned sub-layer; and a sub-step of hardening the prepreg. The method of manufacturing a semiconductor package according to any one of the items 19 to 22, wherein, in the cooling of the metal bump, the metal bump is secreted in a thickness direction, and the second wiring substrate of the ± layer package is provided The first semiconductor element in the lower package is in a state of being apart from the first semiconductor element. The manufacturing method of the semiconductor package 100131022 201230259, as in any one of claims 19 to 22, wherein 'the upper layer package and the spacer are disposed, and the upper layer package and the lower layer lower layer package are disposed between After the upper spacer is removed and the upper layer of the upper layer is bonded, the i-th semiconductor element of the lower package is separated from the left. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The lower layer 4' is used to make the second layer of the upper package, and the 4th (4)th (4) half-shirt is in a state of the substrate. 100131022 72 201230259 IV. Designated representative figure: (1) The representative figure of the case is: (1) . (2) A brief description of the components of the drawing: 1 semiconductor package 2 wiring substrate 3 semiconductor element 4 first reinforcing member 5 second reinforcing member 6 thermally conductive material 21 substrate 24 heat conducting column 31 metal bump 32 next layer 51 opening 71 Metal bump 81 Insulating material 91 Thermal conductive bump 211 Insulating layer 212 Insulating layer 213 Insulating layer 214 Insulating layer 215 Insulating layer 221 Conductor pattern 222 Conductor pattern 223 Conductor pattern 224 Conductor pattern 225 Conductor pattern 231 Conductor column 232 Conductor column 233 Conductor column 234 conductor post 300 upper package 301 wiring substrate 302 substrate 303 insulating layer 304 insulating layer 305 semiconductor element 306 metal wire 307 sealing portion 308 conductor pattern 400 metal bump 401 insulating material 500 lower layer package S1 gap S2 gap five, if there is a chemical formula in this case Please reveal the chemical formula that best shows the characteristics of the invention: None 100131022 3
TW100131022A 2010-09-17 2011-08-30 A semiconductor package and a semiconductor equipment TW201230259A (en)

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