JP5333220B2 - Semiconductor device mounting structure and semiconductor device mounting method - Google Patents

Semiconductor device mounting structure and semiconductor device mounting method Download PDF

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Publication number
JP5333220B2
JP5333220B2 JP2009530009A JP2009530009A JP5333220B2 JP 5333220 B2 JP5333220 B2 JP 5333220B2 JP 2009530009 A JP2009530009 A JP 2009530009A JP 2009530009 A JP2009530009 A JP 2009530009A JP 5333220 B2 JP5333220 B2 JP 5333220B2
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resin
conductive particles
conductive
electrode pad
semiconductor element
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JPWO2009028239A1 (en
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明 大内
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NEC Corp
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NEC Corp
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0212—Resin particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0221—Insulating particles having an electrically conductive coating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10984—Component carrying a connection agent, e.g. solder, adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder

Abstract

Disclosed are a structure and method for mounting a bare chip or a chip size package with high connection reliability. Specifically, a bump for electrically connecting an electrode pad of a semiconductor element and an electrode pad of a wiring board is composed of a plurality of conductive particles, each of which is obtained by forming a metal layer around a core portion which is composed of a first resin. The metal layers as the outermost layers of the conductive particles are melted and combine the conductive particles together, and the conductive particles are covered and protected by a second resin.

Description

本発明は、半導体素子、特にフリップチップ、ＣＳＰ（Chip Size Package）を配線基板に搭載した半導体装置の実装構造及び実装方法に関する。   The present invention relates to a mounting structure and a mounting method of a semiconductor device in which a semiconductor element, particularly a flip chip and a CSP (Chip Size Package) are mounted on a wiring board.

電子機器の急速な発達に伴い、半導体素子を配線基板に搭載した半導体装置にはこれまで以上に高機能化が求められるようになった。半導体装置の多機能化に伴い半導体素子の入出力端子数は増加し、また半導体素子を高速動作させるため配線基板の配線長の短縮化が求められている。このような要求を実現するために開発された接続工法としてフリップチップ接続が挙げられる。   With the rapid development of electronic devices, semiconductor devices having semiconductor elements mounted on a wiring board are required to have higher functionality than ever. With the increase in the number of functions of semiconductor devices, the number of input / output terminals of a semiconductor element increases, and in order to operate the semiconductor element at high speed, it is required to shorten the wiring length of the wiring board. As a connection method developed in order to realize such a requirement, flip chip connection can be mentioned.

フリップチップ接続は半導体装置の配線基板の配線面のエリア上に接続パッドを設けることができるため多ピン化に適している。また、ワイヤボンディング（ＷＢ）やテープオートメイティッドボンディング（ＴＯＢ）の様な引き出し線を必要としないため配線長の短縮化が可能である。   The flip-chip connection is suitable for increasing the number of pins because a connection pad can be provided on the wiring surface area of the wiring board of the semiconductor device. In addition, since there is no need for lead wires such as wire bonding (WB) and tape automated bonding (TOB), the wiring length can be shortened.

以上のような理由から電子機器に用いられる半導体素子の配線基板への実装には、フリップチップ接続を使用したものが増加している。   For the reasons described above, the number of semiconductor devices used in electronic devices using flip chip connection is increasing for mounting on wiring boards.

現在、フリップチップに使用される一般的なバンプ電極の材質としては、Ａｕやはんだ等が用いられている。
はんだの材質の例としてはＳｎ−Ｐｂ共晶はんだが挙げられるが、Ｓｎ−Ｐｂ共晶はんだに限定されず、たとえばＳｎ−Ｐｂ（共晶を除く）、Ｓｎ−Ａｇ、Ｓｎ−Ｃｕ、Ｓｎ−Ｓｂ、Ｓｎ−Ｚｎ、Ｓｎ−Ｂｉおよびこれら前記した材料に特定の添加元素をさらに加えた材料を挙げることができ、これらが適宜用いられる。At present, Au, solder, or the like is used as a material for a general bump electrode used in a flip chip.
Examples of the solder material include Sn—Pb eutectic solder, but are not limited to Sn—Pb eutectic solder. For example, Sn—Pb (excluding eutectic), Sn—Ag, Sn—Cu, Sn— Examples include Sb, Sn—Zn, Sn—Bi, and materials obtained by further adding a specific additive element to the above-described materials, and these are used as appropriate.

一方、フリップチップ接続される半導体素子の多くは、半導体素子−配線基板間の熱膨張差による応力を緩和するため、半導体素子−配線基板の隙間を樹脂封止することにより、接続信頼性を確保する必要がある（例えば、特許文献１参照。）。
他のバンプ電極材質の例としては、導電性樹脂バンプを使用したもの（例えば、特許文献２参照。）、樹脂コアの周囲に金属層が施されたボールバンプを導電性接着剤で接合したもの（例えば、特許文献３参照。）等が挙げられる。
他に半導体装置としては特許文献４〜１１が挙げられる。
特開平１１−２３３５５８号公報 特開２０００−３３２０５３号公報 特開平１０−１７３００６号公報 特開２０００−１８８２９９号公報 特開２００２−２７１００５号公報 特開２００４−２７３４０１号公報 特開２００４−３５６１３８号公報 特開昭６３−０５５５２７号公報 特開平０９−１２７５２２号公報 特開平１０−０５４９９０号公報 特開平１１−００７０２４号公報 On the other hand, in many of the semiconductor elements that are flip-chip connected, the connection reliability is ensured by resin-sealing the gap between the semiconductor element and the wiring board in order to relieve stress due to the difference in thermal expansion between the semiconductor element and the wiring board. (For example, refer to Patent Document 1).
Examples of other bump electrode materials include those using conductive resin bumps (see, for example, Patent Document 2), and those obtained by bonding ball bumps having a metal layer around a resin core with a conductive adhesive. (For example, refer to Patent Document 3).
Other semiconductor devices include Patent Documents 4 to 11.
Japanese Patent Laid-Open No. 11-233558 JP 2000-332053 A Japanese Patent Laid-Open No. 10-173006 JP 2000-188299 A JP 2002-271005 A JP 2004-273401 A JP 2004-356138 A JP 63-055527 A JP 09-127522 A JP 10-054990 A JP-A-11-007024

ところで、特許文献１に記載の発明においては、半導体素子−配線基板間がはんだバンプのみの場合、弾性率が高いはんだバンプは半導体素子−配線基板間の熱膨張差により高い応力が発生し、はんだバンプが破壊する問題がある。
そこではんだバンプにかかる応力を緩和する目的で半導体素子と配線基板との間の隙間をアンダーフィル樹脂で封止することで接続信頼性を向上できるが、はんだバンプの弾性率の方がアンダーフィル樹脂に比較してはるかに高い。例えばＳｎ−３ＡＧ−０．５Ｃｕはんだの弾性率は約４０ＧＰａであるのに対し、アンダーフィル樹脂の弾性率は充填剤を混入して高弾性率化した場合でも１０ＧＰａ程度である。
このため、弾性率の高いはんだ部分に依然として応力が集中して、繰返しの温度変化等により、はんだバンプにクラックが発生するという課題がある。By the way, in the invention described in Patent Document 1, when only a solder bump is provided between the semiconductor element and the wiring board, the solder bump having a high elastic modulus generates a high stress due to a difference in thermal expansion between the semiconductor element and the wiring board. There is a problem that the bump breaks.
Therefore, the connection reliability can be improved by sealing the gap between the semiconductor element and the wiring board with an underfill resin in order to relieve the stress applied to the solder bump. However, the elastic modulus of the solder bump is better than the underfill resin. Much higher compared to. For example, the elastic modulus of Sn-3AG-0.5Cu solder is about 40 GPa, whereas the elastic modulus of the underfill resin is about 10 GPa even when the elastic modulus is increased by mixing a filler.
For this reason, there is a problem that stress is still concentrated on the solder portion having a high elastic modulus, and cracks are generated in the solder bump due to repeated temperature changes.

そこで、はんだバンプの弾性率を下げる試みとして、例えば特許文献２記載の発明のように導電性樹脂バンプにより、半導体素子と配線基板とを接続する構造が提案されている。この場合、導電性樹脂を使用することにより、はんだバンプに比較し低弾性化を図ることが可能となる。ただし、この方法では、導電性樹脂に重量比で８０ｗｔ％（重量％）の多量の金属粒子を添加して、導電性を確保しているため、この多量の金属粒子の影響でバンプ自体の弾性率が上昇し、バンプ材質の低弾性化効果が小さくなる。例をあげると、エポキシ樹脂自身の弾性率は２ＧＰａ程度であっても、この従来例のように金属フィラーを多量に混入することにより、導電性樹脂としての弾性率は、１０ＧＰａ程度まで上昇してしまうという課題がある。   Therefore, as an attempt to lower the elastic modulus of the solder bump, a structure in which a semiconductor element and a wiring board are connected by a conductive resin bump as in the invention described in Patent Document 2, for example, has been proposed. In this case, by using a conductive resin, it is possible to achieve low elasticity compared to solder bumps. However, in this method, since a large amount of metal particles of 80 wt% (weight%) is added to the conductive resin to ensure conductivity, the elasticity of the bump itself is affected by the large amount of metal particles. The rate increases and the effect of reducing the elasticity of the bump material is reduced. For example, even if the elastic modulus of the epoxy resin itself is about 2 GPa, the elastic modulus as a conductive resin increases to about 10 GPa by mixing a large amount of metal filler as in this conventional example. There is a problem of end.

はんだバンプ自体の弾性率をさらに低下させる試みとして、例えば特許文献３に記載の発明のように樹脂コアの周囲に金属層が施されたボールバンプを導電性接着剤で接合したものがある。この場合、バンプの体積の大部分を占めているのは樹脂であり、バンプの低弾性化には有効な手段となる。
しかし、この方法の場合、バンプの周囲は金属層であるため、半導体素子と配線基板との間を封止せずに使用した場合、隙間に異物等が混入すると、異物がバンプ間を繋いでショートが発生するという課題がある。さらに適用する半導体素子の電極パッドのピッチに合わせて、それぞれ専用のサイズの樹脂コアボールを用意しなければならず、バンプの製造コストがかかるという課題がある。
ピッチに対してバンプサイズが大きすぎる場合は、隣のバンプとショートする課題があり、ピッチに対してバンプサイズが小さすぎる場合は、接続信頼性が低下するという課題がある。
さらにバンプ形成性に関しては、先に導電性樹脂等の接着用材料をパッド上のみに塗布した後、個々の樹脂コアボールバンプをパッド上に整列させてパッドと接合する必要があるため、バンプ形成に手間がかかるという課題があった。As an attempt to further reduce the elastic modulus of the solder bump itself, for example, as in the invention described in Patent Document 3, there is a method in which a ball bump in which a metal layer is applied around a resin core is joined with a conductive adhesive. In this case, the resin occupies most of the volume of the bump, which is an effective means for reducing the elasticity of the bump.
However, in this method, the periphery of the bump is a metal layer, so if it is used without sealing between the semiconductor element and the wiring board, if a foreign object or the like enters the gap, the foreign object connects the bumps and shorts. There is a problem that occurs. Furthermore, a resin core ball having a dedicated size must be prepared in accordance with the pitch of the electrode pads of the semiconductor element to be applied, and there is a problem that the manufacturing cost of the bump is increased.
When the bump size is too large with respect to the pitch, there is a problem of short-circuiting with the adjacent bump, and when the bump size is too small with respect to the pitch, there is a problem that connection reliability is lowered.
Furthermore, regarding bump formability, it is necessary to first apply adhesive material such as conductive resin only on the pad, and then align the individual resin core ball bumps on the pad and bond them to the pad. There was a problem that it took time and effort.

以上述べたように、フリップチップ接続は、高性能化に適した構造であるため、将来的に需要増が見込まれるが、高信頼性確保するとともに、低コスト化、実装工程削減等の課題が残っている。   As mentioned above, flip-chip connection is a structure suitable for high performance, so demand is expected to increase in the future. However, there are issues such as ensuring high reliability, reducing costs, and reducing mounting processes. Remaining.

そこで、本発明の目的は、フリップチップ接続やＣＳＰ接続において、課題となっているバンプの低弾性化により高信頼性の確保が可能であると同時に簡易な実装工程で製作可能な半導体装置の実装構造及び実装方法を提供するものである。   Therefore, an object of the present invention is to mount a semiconductor device that can ensure high reliability by reducing the elasticity of bumps, which is a problem in flip chip connection and CSP connection, and can be manufactured by a simple mounting process. A structure and a mounting method are provided.

請求項１記載の発明では、半導体素子の電極パッドと配線基板の電極パッドとが向かい合って接続された半導体装置の実装構造において、前記半導体素子の電極パッドと前記配線基板の電極パッドとを電気的に接続するバンプは、第１の樹脂からなるコア部の表面に金属層が施された複数の導電粒子からなり、導電粒子の金属層は溶融して各導電粒子間を結合しており、かつ導電粒子を第２の樹脂で被覆したことを特徴とする。   According to the first aspect of the present invention, in the mounting structure of the semiconductor device in which the electrode pad of the semiconductor element and the electrode pad of the wiring board are connected to face each other, the electrode pad of the semiconductor element and the electrode pad of the wiring board are electrically connected The bumps connected to each other are composed of a plurality of conductive particles having a metal layer applied to the surface of the core portion made of the first resin, and the metal layers of the conductive particles are melted to bond the conductive particles, and The conductive particles are covered with a second resin.

請求項２記載の発明では、前記バンプ中の導電粒子の比重が、前記バンプ中の導電粒子以外の絶縁部分の比重の３倍以下であることを特徴とする。   The invention according to claim 2 is characterized in that the specific gravity of the conductive particles in the bump is not more than three times the specific gravity of the insulating portion other than the conductive particles in the bump.

請求項３記載の発明では、前記第１の樹脂は熱硬化性樹脂であり、前記バンプ中には導電粒子とともに第２の樹脂と同じ比重のフィラーが混入されていることを特徴とする。   The invention according to claim 3 is characterized in that the first resin is a thermosetting resin, and fillers having the same specific gravity as the second resin are mixed together with the conductive particles in the bumps.

請求項４記載の発明では、前記第２の樹脂は、前記金属層に形成された酸化膜を除去する成分を含むことを特徴とする。   According to a fourth aspect of the present invention, the second resin includes a component that removes an oxide film formed on the metal layer.

請求項５記載の発明では、前記第１の樹脂は、熱硬化性樹脂であることを特徴とする。   The invention according to claim 5 is characterized in that the first resin is a thermosetting resin.

請求項６記載の発明では、前記バンプの周囲を第３の樹脂で封止したことを特徴とする。   The invention according to claim 6 is characterized in that the periphery of the bump is sealed with a third resin.

請求項７記載の発明では、半導体素子の電極パッドまたは配線基板の電極パッドの少なくとも一方に、第１の樹脂からなるコア部の表面に金属層が形成された複数の導電粒子と第２の樹脂とを含んだ導電性ペーストを供給する工程と、前記半導体素子を前記配線基板に位置合わせして搭載するとともに、前記半導体素子と前記配線基板との間の隙間を一定に制御した状態で加熱を行ない、前記導電粒子の周囲の金属を溶融させて前記導電粒子間の表面を結合させる工程と、前記導電性ペーストを硬化させる工程とを含むことを特徴とする。   According to a seventh aspect of the present invention, a plurality of conductive particles and a second resin in which a metal layer is formed on the surface of the core portion made of the first resin on at least one of the electrode pad of the semiconductor element or the electrode pad of the wiring board And a step of supplying a conductive paste containing the semiconductor element, and mounting the semiconductor element in alignment with the wiring board, and heating in a state in which a gap between the semiconductor element and the wiring board is controlled to be constant. Performing a step of melting the metal around the conductive particles to bond the surfaces between the conductive particles, and a step of curing the conductive paste.

請求項８記載の発明では、半導体素子の電極パッドまたは配線基板の電極パッドの少なくとも一方に、第１の樹脂からなるコア部の表面に金属層が形成された複数の導電粒子と第２の樹脂とを含んだ導電性ペーストを供給する工程と、前記半導体素子を前記配線基板に位置合わせして搭載するとともに、前記半導体素子と前記配線基板との間の隙間を一定に制御した状態で加熱を行ない、前記導電粒子の周囲の金属を溶融させて前記導電粒子間の表面を結合させる工程と、前記導電性ペーストを硬化させる工程と、硬化した前記導電性ペーストと前記両電極パッドとの間に第３の樹脂を封止した後硬化させる工程とを含むことを特徴とする。   According to an eighth aspect of the present invention, a plurality of conductive particles and a second resin in which a metal layer is formed on the surface of a core portion made of a first resin on at least one of an electrode pad of a semiconductor element or an electrode pad of a wiring board And a step of supplying a conductive paste containing the semiconductor element, and mounting the semiconductor element in alignment with the wiring board, and heating in a state in which a gap between the semiconductor element and the wiring board is controlled to be constant. Performing a step of melting the metal around the conductive particles to bond the surfaces between the conductive particles, a step of curing the conductive paste, and between the cured conductive paste and the two electrode pads. And a step of curing after sealing the third resin.

本発明によれば、半導体素子の電極パッドと配線基板の電極パッドを電気的に接続するバンプは、コア部である第１の樹脂の周囲に金属層が施された複数の導電粒子からなり、導電粒子の最外層の金属層は溶融して各導電粒子間を結合しており、かつ導電粒子を第２の樹脂で被覆して保護する。これにより、高信頼性の確保が可能であると同時に簡易な実装工程で製作可能な半導体装置の実装構造及び実装方法の提供を実現することができる。   According to the present invention, the bump that electrically connects the electrode pad of the semiconductor element and the electrode pad of the wiring board is composed of a plurality of conductive particles in which a metal layer is applied around the first resin that is the core part, The outermost metal layer of the conductive particles melts and bonds between the conductive particles, and the conductive particles are covered with a second resin for protection. Accordingly, it is possible to provide a semiconductor device mounting structure and a mounting method that can ensure high reliability and can be manufactured by a simple mounting process.

本発明に係る半導体装置の実装構造の一実施の形態は、半導体素子の電極パッドと配線基板の電極パッドとが向かい合って接続された半導体装置の実装構造において、半導体素子の電極パッドと配線基板の電極パッドとを電気的に接続するバンプは、第１の樹脂からなるコア部の表面に金属層が施された複数の導電粒子からなり、導電粒子の金属層は溶融して各導電粒子間を結合しており、かつ導電粒子を第２の樹脂で被覆したことを特徴とする。 One embodiment of a mounting structure of a semiconductor device according to the present invention is a mounting structure of a semiconductor device in which an electrode pad of a semiconductor element and an electrode pad of a wiring board are connected to face each other. The bumps that electrically connect the electrode pads are composed of a plurality of conductive particles in which a metal layer is applied to the surface of the core portion made of the first resin, and the metal layer of the conductive particles melts to form a space between the conductive particles. The conductive particles are bonded and covered with a second resin.

上記構成によれば、バンプの体積の大部分を占めているのが樹脂である為、バンプの弾性率を低くすることができる。このバンプの弾性率を低くする効果により半導体素子と配線基板との間の熱膨張差により生じる応力を緩和すること（応力緩和効果）が可能になる。この応力緩和効果はバンプ破壊の防止のみでなく、半導体素子や配線基板（プリント基板）のクラックを防止する効果がある。さらにバンプ中の各導電粒子間の結合部分は周囲の第２の樹脂（絶縁樹脂）によって被覆されて保護されている為、応力がかかっても結合部分が破壊されにくい。これらの効果により、高信頼性を確保することが容易になる。
また、本構造は導電粒子の表面が溶融して各導電粒子間で結合する為、バンプ体積の大部分を絶縁性樹脂が占めている場合でも、安定した導通を確保可能である。さらに本構造はバンプ形成の際、導電粒子と絶縁樹脂（第２の樹脂）とをペースト化したものを、スクリーン印刷等により電極パッド上のみに選択的に供給することでバンプ形成が可能であるため、バンプ形成工程がシンプルかつ容易である。According to the above configuration, since the resin occupies most of the bump volume, the elastic modulus of the bump can be lowered. Due to the effect of lowering the elastic modulus of the bump, it is possible to relieve the stress generated by the difference in thermal expansion between the semiconductor element and the wiring board (stress relaxation effect). This stress relaxation effect is effective not only in preventing bump destruction but also in preventing cracks in semiconductor elements and wiring boards (printed boards). Further, since the joint portion between the conductive particles in the bump is covered and protected by the surrounding second resin (insulating resin), the joint portion is not easily broken even when stress is applied. These effects make it easy to ensure high reliability.
In addition, since the surface of the conductive particles melts and bonds between the conductive particles in this structure, stable conduction can be ensured even when the insulating resin occupies most of the bump volume. Furthermore, this structure enables bump formation by selectively supplying a paste of conductive particles and insulating resin (second resin) only on the electrode pad by screen printing or the like. Therefore, the bump forming process is simple and easy.

本発明に係る半導体装置の実装構造の他の実施の形態は、バンプに関して、バンプ中の導電粒子の比重が、バンプ中の導電粒子以外の絶縁部分の比重の３倍以下であることを特徴とする。   Another embodiment of the semiconductor device mounting structure according to the present invention is characterized in that the specific gravity of the conductive particles in the bump is not more than three times the specific gravity of the insulating portion other than the conductive particles in the bump. To do.

上記構成によれば、バンプ中の導電粒子の比重と絶縁樹脂の比重の差を抑えることにより、熱がかかって絶縁樹脂の粘度が低下する場合でも、フィラーの沈殿が発生せずバンプ中の導電粒子は均一分散する為、半導体素子と配線基板との間の安定した導通確保を実現することができる。   According to the above configuration, by suppressing the difference between the specific gravity of the conductive particles in the bump and the specific gravity of the insulating resin, even when heat is applied and the viscosity of the insulating resin is reduced, the filler does not precipitate and the conductive in the bump is not generated. Since the particles are uniformly dispersed, stable conduction between the semiconductor element and the wiring board can be realized.

本発明に係る半導体装置の実装構造の他の実施の形態は、第１の樹脂は熱硬化性樹脂であり、バンプ中には導電粒子とともに第２の樹脂と同じ比重のフィラーが混入されていることを特徴とする。   In another embodiment of the semiconductor device mounting structure according to the present invention, the first resin is a thermosetting resin, and the filler has the same specific gravity as the second resin together with the conductive particles in the bumps. It is characterized by that.

上記構成によれば、導電粒子の表面の金属層の厚さを厚くした場合、バンプの形成及び接合時に導電粒子が沈殿しやすくなるが、第２の樹脂と同じ比重であるフィラーを混入させておくことにより、バンプの形成及び接合時に導電粒子の沈殿を抑制し、良好な導電粒子の接続を達成することが可能となる。   According to the above configuration, when the thickness of the metal layer on the surface of the conductive particles is increased, the conductive particles are likely to precipitate during the formation and bonding of the bumps, but a filler having the same specific gravity as the second resin is mixed. Accordingly, it is possible to suppress the precipitation of the conductive particles during the formation and bonding of the bumps and achieve a good connection of the conductive particles.

本発明に係る半導体装置の実装構造の他の実施の形態は、第２の樹脂は、金属層に形成された酸化膜を除去する成分を含むことを特徴とする。   Another embodiment of the semiconductor device mounting structure according to the present invention is characterized in that the second resin includes a component for removing the oxide film formed on the metal layer.

上記構成によれば、導電粒子表面の金属層を溶融させて結合させる際に金属層の表面の酸化膜を樹脂の持つ酸化膜除去作用により除去可能となる為、導電粒子表面の安定した結合を実現することが可能となる。   According to the above configuration, when the metal layer on the surface of the conductive particles is melted and bonded, the oxide film on the surface of the metal layer can be removed by the oxide film removing action of the resin, so that stable bonding of the surface of the conductive particles can be achieved. It can be realized.

本発明に係る半導体装置の実装構造の他の実施の形態は、第１の樹脂は、熱硬化性樹脂であることを特徴とする。   Another embodiment of the semiconductor device mounting structure according to the present invention is characterized in that the first resin is a thermosetting resin.

上記構成によれば、様々な温度条件下においても導電粒子のコア部の第１の樹脂が溶融することが無い為、導電粒子は常に安定した形状を保つことができる。従って導電粒子の表面が溶融して結合する状態においても、コア部が安定していることにより導電粒子の配列および形状が大きく崩れることなく結合できるため、半導体素子と配線基板との間の導通確保が容易になる。   According to the above configuration, since the first resin in the core portion of the conductive particles does not melt even under various temperature conditions, the conductive particles can always maintain a stable shape. Therefore, even when the surface of the conductive particles is melted and bonded, the core part is stable, so that the arrangement and shape of the conductive particles can be bonded without greatly breaking, so that conduction between the semiconductor element and the wiring board is ensured. Becomes easier.

本発明に係る半導体装置の実装構造の他の実施の形態は、バンプの周囲を第３の樹脂で封止したことを特徴とする。   Another embodiment of the semiconductor device mounting structure according to the present invention is characterized in that the periphery of the bump is sealed with a third resin.

上記構成によれば、バンプの周囲をアンダーフィル樹脂で封止することで、バンプへの応力がさらに低減化され、さらなる高信頼性を確保することが可能となる。   According to the above configuration, by sealing the periphery of the bump with the underfill resin, the stress on the bump is further reduced, and further high reliability can be ensured.

本発明に係る半導体装置の実装方法の一実施の形態は、半導体素子の電極パッドまたは配線基板の電極パッドの少なくとも一方に、第１の樹脂からなるコア部の表面に金属層が形成された複数の導電粒子と第２の樹脂とを含んだ導電性ペーストを供給する工程と、半導体素子を配線基板に位置合わせして搭載するとともに、半導体素子と配線基板との間の隙間を一定に制御した状態で加熱を行ない、導電粒子の周囲の金属を溶融させて導電粒子間の表面を結合させる工程と、導電性ペーストを硬化させる工程とを含むことを特徴とする。   One embodiment of a semiconductor device mounting method according to the present invention includes a plurality of metal layers formed on a surface of a core portion made of a first resin on at least one of an electrode pad of a semiconductor element or an electrode pad of a wiring board. Supplying the conductive paste containing the conductive particles and the second resin, mounting the semiconductor element in alignment with the wiring board, and controlling the gap between the semiconductor element and the wiring board to be constant Heating in a state, melting the metal around the conductive particles to bond the surfaces between the conductive particles, and curing the conductive paste.

上記構成によれば、半導体素子の配線基板への実装において良好な導通状態と弾性率が低いバンプを実現することができる。   According to the above configuration, it is possible to realize a good conductive state and a low elastic modulus bump when the semiconductor element is mounted on the wiring board.

本発明に係る半導体装置の実装方法の他の実施の形態は、半導体素子の電極パッドまたは配線基板の電極パッドの少なくとも一方に、第１の樹脂からなるコア部の表面に金属層が形成された複数の導電粒子と第２の樹脂とを含んだ導電性ペーストを供給する工程と、半導体素子を配線基板に位置合わせして搭載するとともに、半導体素子と配線基板との間の隙間を一定に制御した状態で加熱を行ない、導電粒子の周囲の金属を溶融させて導電粒子間の表面を結合させる工程と、導電性ペーストを硬化させる工程と、硬化した導電性ペーストと両電極パッドとの間に第３の樹脂を封止した後硬化させる工程とを含むことを特徴とする。   In another embodiment of the semiconductor device mounting method according to the present invention, a metal layer is formed on the surface of the core portion made of the first resin on at least one of the electrode pad of the semiconductor element or the electrode pad of the wiring board. A step of supplying a conductive paste containing a plurality of conductive particles and a second resin, and mounting the semiconductor element in alignment with the wiring board, and controlling the gap between the semiconductor element and the wiring board to be constant Heating in such a state that the metal around the conductive particles is melted to bond the surfaces between the conductive particles, the conductive paste is cured, and the cured conductive paste and the electrode pads are between And a step of curing after sealing the third resin.

上記構成によれば、半導体素子の配線基板への実装において良好な導通状態と弾性率が低いバンプを実現することができる。   According to the above configuration, it is possible to realize a good conductive state and a low elastic modulus bump when the semiconductor element is mounted on the wiring board.

〔効果〕
以上において、本発明によれば、バンプの体積の大部分を占めているのが樹脂である為、バンプの弾性率を低くすることができる。このようなバンプの弾性率を低くする効果により半導体素子と配線基板との間の熱膨張差により生じる応力を緩和することが可能になる。この応力緩和効果はバンプ破壊の防止のみでなく、半導体素子や配線基板のクラックを防止する効果がある。さらにバンプ中の各粒子間の結合部分は周囲の絶縁樹脂によって保護されている為、応力がかかっても結合部分が破壊されにくい。〔effect〕
In the above, according to the present invention, since the resin occupies most of the volume of the bump, the elastic modulus of the bump can be lowered. Due to the effect of reducing the elastic modulus of the bump, it is possible to relieve the stress caused by the difference in thermal expansion between the semiconductor element and the wiring board. This stress relaxation effect is effective not only in preventing bump destruction but also in preventing cracks in semiconductor elements and wiring boards. Furthermore, since the joint portion between each particle in the bump is protected by the surrounding insulating resin, the joint portion is not easily broken even when stress is applied.

これらの効果により、高信頼性を確保することが容易になる。また、導電粒子の表面が溶融して各粒子間で結合する為、バンプ体積の大部分を絶縁性樹脂が占めている場合でも、安定した導通を確保可能である。さらに本構造はバンプ形成の際、導電粒子と絶縁樹脂をペースト化したものを、スクリーン印刷等によりパッド上のみに選択的に供給することでバンプ形成が可能であるため、バンプ形成工程がシンプルかつ容易である。   These effects make it easy to ensure high reliability. Further, since the surfaces of the conductive particles are melted and bonded to each other, stable conduction can be ensured even when the insulating resin occupies most of the bump volume. Furthermore, the bump formation process is simple and simple because bumps can be formed by selectively supplying a paste of conductive particles and insulating resin only on the pad by screen printing or the like. Easy.

なお、上述した実施の形態は、本発明の好適な実施の形態の一例を示すものであり、本発明はそれに限定されることなく、その要旨を逸脱しない範囲内において、種々変形実施が可能である。
以下実施例につき本発明を詳細に説明する。The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there.
Hereinafter, the present invention will be described in detail with reference to examples.

フリップチップ実装工法を用いた電子部品装置に関して、本発明の実施例について説明するが、適用する電子部品はＣＳＰ、ＢＧＡ（Ball Grid Array）、ベアチップ等、いずれの形態でも良く特に限定されるものではない。   An embodiment of the present invention will be described with respect to an electronic component device using a flip chip mounting method, but the electronic component to be applied may be any form such as CSP, BGA (Ball Grid Array), bare chip, etc. Absent.

まず、本発明に係る半導体装置の実装構造の一例ついて、図１（ａ）、（ｂ）を用いて詳細に述べる。
なお、図１（ａ）は本発明に係る半導体装置の一例を示す部分断面図であり、図１（ｂ）は、導電性樹脂バンプ６を形成している導電粒子の断面模式図であり、図１（ｃ）は、導電性樹脂バンプの部分拡大図であり、図１（ｄ）は導電性樹脂バンプの導電粒子間の結合状態の模式図である。First, an example of a semiconductor device mounting structure according to the present invention will be described in detail with reference to FIGS.
FIG. 1A is a partial cross-sectional view showing an example of a semiconductor device according to the present invention, and FIG. 1B is a schematic cross-sectional view of conductive particles forming a conductive resin bump 6. FIG.1 (c) is the elements on larger scale of a conductive resin bump, FIG.1 (d) is a schematic diagram of the coupling | bonding state between the conductive particles of a conductive resin bump.

図１（ａ）に示す半導体装置１００の半導体素子１の電極パッド３と配線基板２の電極パッド４との間は、導電性樹脂バンプ６で接続されており、半導体素子１と配線基板２との電気的接続を達成している。配線基板２の電極パッド４の一例として銅配線の表面にニッケルメッキがされており、さらにそのニッケルメッキの上に金メッキが形成されている。   The electrode pad 3 of the semiconductor element 1 of the semiconductor device 100 shown in FIG. 1A and the electrode pad 4 of the wiring board 2 are connected by a conductive resin bump 6, and the semiconductor element 1 and the wiring board 2 are connected to each other. Has achieved electrical connection. As an example of the electrode pad 4 of the wiring board 2, the surface of the copper wiring is nickel-plated, and further, the gold plating is formed on the nickel plating.

導電性樹脂バンプ７の基材となる第２の樹脂９は、アクリル樹脂、メラミン樹脂、エポキシ樹脂、ポリオレフィン樹脂、ポリウレタン樹脂、ポリカーボネート樹脂、ポリスチレン樹脂、ポリエーテル樹脂、ポリアミド樹脂、ポリイミド樹脂、フッ素樹脂、ポリエステル樹脂、フェノール樹脂、フルオレン樹脂、ベンゾシクロブテン樹脂、シリコーン樹脂等様々な材料があるが、特に限定されるものではなく、これらを１種あるいは２種以上組み合わせて用いることもできる。粘度、コスト、耐熱性、接着性等の面に優れるエポキシ樹脂が一般に用いられるが、２５℃の室温において液状である樹脂が望ましい。   The second resin 9 serving as the base material of the conductive resin bump 7 is acrylic resin, melamine resin, epoxy resin, polyolefin resin, polyurethane resin, polycarbonate resin, polystyrene resin, polyether resin, polyamide resin, polyimide resin, fluorine resin. There are various materials such as a polyester resin, a phenol resin, a fluorene resin, a benzocyclobutene resin, and a silicone resin, but there is no particular limitation, and these can be used alone or in combination of two or more. Epoxy resins that are excellent in terms of viscosity, cost, heat resistance, adhesiveness and the like are generally used, but resins that are liquid at room temperature of 25 ° C. are desirable.

さらに導電性樹脂バンプ６の基材となる第２の樹脂９に酸化膜除去作用を付加することで導電粒子同士の接合性を飛躍的に向上させることができ、有効である。エポキシ樹脂にフラックス作用を与えるには、（メタ）アクリル酸、マレイン酸などの不飽和酸、蓚酸、マロン酸などの有機二酸、クエン酸などの有機酸をはじめ、炭化水素の側鎖に、ハロゲン基、水酸基、ニトリル基、ベンジル基、カルボキシル基等を少なくとも１つ以上を添加することにより可能である。第２の樹脂９にこれらの添加剤を３〜１０ｗｔ％（重量％）加えても良く、エポキシ樹脂の硬化剤と主剤との反応時に生成される前記物質を利用して、酸化膜除去を行なっても良い。   Furthermore, by adding an oxide film removing action to the second resin 9 which is a base material of the conductive resin bump 6, the bonding property between the conductive particles can be drastically improved, which is effective. In order to give a flux action to the epoxy resin, unsaturated acids such as (meth) acrylic acid and maleic acid, organic diacids such as oxalic acid and malonic acid, organic acids such as citric acid, and hydrocarbon side chains, It is possible by adding at least one halogen group, hydroxyl group, nitrile group, benzyl group, carboxyl group or the like. These additives may be added to the second resin 9 in an amount of 3 to 10 wt% (weight%), and the oxide film is removed by using the substance generated during the reaction between the epoxy resin curing agent and the main agent. May be.

エポキシ樹脂の主剤と硬化剤との混合比は、主剤６０〜９０ｗｔ％（重量％）に対して、硬化剤１０〜４０ｗｔ％（重量％）が望ましい。   The mixing ratio of the epoxy resin main agent and the curing agent is preferably 10 to 40 wt% (wt%) with respect to 60 to 90 wt% (wt%) of the main agent.

導電性樹脂バンプ６に添加されている導電粒子５の形状は、針状、球状、フレーク状等、さまざまであり、特に限定されないが球状が一般的である。その構造は図１（ｂ）に示すように、コア部としての第１の樹脂（樹脂コア）７に金属層（以下、導電層と称す。）８をメッキ等により形成したものである。このように導電粒子５に第１の樹脂（樹脂コア）７を使用することで、通常、金属である導電粒子５自体の物性を第１の樹脂（樹脂コア）７の物性に限りなく近づけることが可能となり、導電性樹脂バンプ６の低弾性化が実現できる。   The shape of the conductive particles 5 added to the conductive resin bump 6 is various such as a needle shape, a spherical shape, and a flake shape, and is not particularly limited, but a spherical shape is common. As shown in FIG. 1B, the structure is such that a metal layer (hereinafter referred to as a conductive layer) 8 is formed on a first resin (resin core) 7 as a core portion by plating or the like. As described above, by using the first resin (resin core) 7 for the conductive particles 5, the physical properties of the conductive particles 5, which are usually metals, are brought as close as possible to the physical properties of the first resin (resin core) 7. This makes it possible to reduce the elasticity of the conductive resin bump 6.

導電粒子５のコア部に用いる樹脂としては、メラミン樹脂、エポキシ樹脂、ポリオレフィン樹脂、ポリウレタン樹脂、ポリイミド樹脂、フッ素樹脂、ポリエステル樹脂、フェノール樹脂、シリコーン樹脂等があげられるが、熱硬化性樹脂である方がより好ましい。その理由は、様々な温度条件下においてもコアの樹脂が溶融することが無い為、常に安定した形状を保つことができる。
従って導電粒子５の表面が溶融して結合する状態においても、コア部が安定していることにより導電粒子５の配列および形状が大きく崩れることなく結合できるため、半導体素子１と配線基板２との間の導通確保が容易になるからである。Examples of the resin used for the core portion of the conductive particles 5 include a melamine resin, an epoxy resin, a polyolefin resin, a polyurethane resin, a polyimide resin, a fluororesin, a polyester resin, a phenol resin, and a silicone resin, and are thermosetting resins. Is more preferable. The reason is that the core resin does not melt even under various temperature conditions, so that a stable shape can always be maintained.
Therefore, even when the surfaces of the conductive particles 5 are melted and bonded, the core portion is stable, so that the arrangement and shape of the conductive particles 5 can be bonded without being greatly damaged. This is because it is easy to ensure conduction between the two.

第１の樹脂（樹脂コア）７の周囲にメッキ等により、金属の導電層８を形成する際に、層間の密着力を向上させる目的で第１の樹脂（樹脂コア）７の周囲を粗化させることが有効である。第１の樹脂（樹脂コア）７を覆う導電層８については、例えば、第１の樹脂７の表面にＣｕ層、Ｃｕ層の周囲にＳｎ／Ｐｂはんだ層のように２層以上形成することが望ましいが、最外周の金属層８は実装工程中に溶融する物質である必要があり、例としては、Ｓｎ／Ｐｂ、Ｓｎ／Ａｇ、Ｓｎ／Ｃｕ、Ｓｎ／Ｓｂ、Ｓｎ／Ｚｎ、Ｓｎ／Ｂｉおよびこれら前記した材料に特定の添加元素をさらに加えた材料を挙げることができ、これらを適宜用いることができる。   When the metal conductive layer 8 is formed around the first resin (resin core) 7 by plating or the like, the periphery of the first resin (resin core) 7 is roughened for the purpose of improving the adhesion between the layers. It is effective to make it. For the conductive layer 8 covering the first resin (resin core) 7, for example, two or more layers such as a Cu layer on the surface of the first resin 7 and a Sn / Pb solder layer around the Cu layer may be formed. Desirably, the outermost metal layer 8 must be a material that melts during the mounting process. Examples include Sn / Pb, Sn / Ag, Sn / Cu, Sn / Sb, Sn / Zn, and Sn / Bi. In addition, a material obtained by further adding a specific additive element to these materials described above can be used, and these can be used as appropriate.

導電粒子５の平均粒径は、１０〜２０μｍ程度、導電粒子５の導電層８の厚さは１〜２μｍ程度が目安となるが、バンプピッチが微細の場合には、粒径を小さくすることもある。導電性樹脂バンプ６に添加されている導電粒子５の量に関しては、粒子形状や粒子材質、製造方法等により異なるので、一概に規定することは出来ないが、一例をあげるとすれば、樹脂に対する導電粒子５の体積比率で考えた場合、２０〜５０％程度であることが望ましい。   The average particle size of the conductive particles 5 is about 10 to 20 μm, and the thickness of the conductive layer 8 of the conductive particles 5 is about 1 to 2 μm. However, if the bump pitch is fine, the particle size should be reduced. There is also. The amount of the conductive particles 5 added to the conductive resin bump 6 varies depending on the particle shape, particle material, manufacturing method, and the like, and thus cannot be defined generally. When considered in terms of the volume ratio of the conductive particles 5, it is preferably about 20 to 50%.

ここで問題になるのが、バンプ接合時に導電粒子５が重力の影響で沈殿して配線基板２側あるいは半導体素子１側の一方に偏り、半導体素子１と配線基板２との導通を得られない現象が発生することである。この現象は導電性樹脂バンプ６中の絶縁樹脂は接合時の加熱により極端に粘度が低下することに起因し、対策としては導電性樹脂バンプ６中の導電粒子（第１の樹脂７＋導電層８）と導電性樹脂バンプ６中の絶縁部分の比重を可能な限り合わせることが望ましい。また、別の対策としては、比重の大きい導電粒子５を微細にすることで沈殿しにくくする等が考えられる。   The problem here is that the conductive particles 5 precipitate due to the influence of gravity during bump bonding and are biased to one of the wiring board 2 side or the semiconductor element 1 side, and the conduction between the semiconductor element 1 and the wiring board 2 cannot be obtained. The phenomenon occurs. This phenomenon is caused by the fact that the viscosity of the insulating resin in the conductive resin bump 6 is extremely reduced by heating at the time of bonding. As a countermeasure, the conductive particles in the conductive resin bump 6 (first resin 7 + conductive layer 8). It is desirable to match the specific gravity of the insulating portion in the conductive resin bump 6 as much as possible. Further, as another countermeasure, it is conceivable that the conductive particles 5 having a large specific gravity are made fine to make it difficult to precipitate.

本発明に用いる導電粒子５の場合、第１の樹脂７が存在する分だけ比重が大きくなるのを抑える効果があるが、多層構造になっている為、粒径を微細にすることが困難となる。
また一方で導電層８の厚さを薄くすれば、低応力効果及び比重の低減に有利であるが、導電層８が薄いと導電層８の溶融接続が困難になる為、所定の厚さを確保する必要がある。In the case of the conductive particles 5 used in the present invention, there is an effect of suppressing the specific gravity from being increased by the presence of the first resin 7, but it is difficult to make the particle size fine because of the multilayer structure. Become.
On the other hand, if the thickness of the conductive layer 8 is reduced, it is advantageous for the low stress effect and the reduction of the specific gravity. However, if the conductive layer 8 is thin, it becomes difficult to melt and connect the conductive layer 8. It is necessary to secure.

そこで導電性樹脂バンプ６中の導電粒子５や絶縁樹脂（第２の樹脂）９について、具体例に基づいて詳細に説明する。
導電粒子５間の良好な溶融接続を得るためには、導電粒子５の直径（金属層を含めた直径）に対して導電層８の厚さが１０％以上であることが望ましい。例えば導電粒子５の直径が１０μｍの場合、導電層８の厚さは１μｍ以上となる。
Therefore, the conductive particles 5 and the insulating resin (second resin) 9 in the conductive resin bump 6 will be described in detail based on specific examples.
In order to obtain a good fusion connection between the conductive particles 5, the thickness of the conductive layer 8 is preferably 10% or more with respect to the diameter of the conductive particles 5 (the diameter including the metal layer). For example, when the diameter of the conductive particles 5 is 10 μm, the thickness of the conductive layer 8 is 1 μm or more.

ここで、導電粒子５の直径を１０μｍとし、導電層８の厚さを１μｍとし、導電粒子５の第１の樹脂７に低弾性であるシリコーン系樹脂（比重０．９５）を使用し、導電層８にＳｎ／Ａｇはんだ（比重７．３）を使用すると、導電粒子５の合計の比重は２．６７となる。
導電性樹脂バンプ６中の絶縁樹脂（第２の樹脂）９にエポキシ樹脂（比重１．１７）を用いた場合、導電粒子５の比重は絶縁部分の比重の３倍以内となり、導電粒子５同士間の良好な接続と導電性樹脂バンプ６中の導電粒子５の均一な分散を同時に満たすことが可能となり、半導体素子１と配線基板２との良好な接続が達成できる。Here, the diameter of the conductive particles 5 is 10 μm, the thickness of the conductive layer 8 is 1 μm, and a low-elasticity silicone resin (specific gravity 0.95) is used for the first resin 7 of the conductive particles 5. When Sn / Ag solder (specific gravity 7.3) is used for the layer 8, the total specific gravity of the conductive particles 5 is 2.67.
When an epoxy resin (specific gravity 1.17) is used for the insulating resin (second resin) 9 in the conductive resin bump 6, the specific gravity of the conductive particles 5 is within three times the specific gravity of the insulating portion, and the conductive particles 5 It is possible to simultaneously satisfy the good connection between them and the uniform dispersion of the conductive particles 5 in the conductive resin bump 6, and the good connection between the semiconductor element 1 and the wiring board 2 can be achieved.

さらに導電性樹脂バンプ６の形成及び接合時の導電粒子５の沈殿を抑制する手段として、図２に示すように導電性樹脂バンプ６中の第２の樹脂（絶縁樹脂）９と同じ比重であるフィラー１２を混入することが効果的である。比重が同じフィラー１２は硬化前の液状の第２の樹脂９中においても沈殿することがなく、第２の樹脂９中で浮遊するため、このフィラー１２の影響で硬化前の液状の第２の樹脂９中における導電粒子５の沈殿を抑制することが出来るからである。   Further, as a means for suppressing the formation of the conductive resin bump 6 and the precipitation of the conductive particles 5 at the time of bonding, it has the same specific gravity as the second resin (insulating resin) 9 in the conductive resin bump 6 as shown in FIG. It is effective to mix the filler 12. The filler 12 having the same specific gravity does not precipitate in the liquid second resin 9 before curing, and floats in the second resin 9, so that the liquid second resin before curing is affected by the filler 12. This is because precipitation of the conductive particles 5 in the resin 9 can be suppressed.

図２は本発明に係る半導体装置の実装構造の変形例を示す部分断面図である。
このフィラー１２は、例えば第２の樹脂と同じ樹脂を硬化させたものをフィラー１２として混入させることが出来る。ただし、この場合、このフィラー１２を多量に混入すると、導電粒子５の沈殿を防止する効果はあるが導電粒子５同士間の接合に対しては悪影響を及ぼすため、混入量としては、導電粒子５に対して５０ｖｏｌ％以下であることが望ましい。FIG. 2 is a partial sectional view showing a modification of the mounting structure of the semiconductor device according to the present invention.
As the filler 12, for example, a cured product of the same resin as the second resin can be mixed as the filler 12. However, in this case, if a large amount of the filler 12 is mixed, there is an effect of preventing the precipitation of the conductive particles 5, but adversely affects the bonding between the conductive particles 5. It is desirable that it is 50 vol% or less.

また、このフィラー１２の平均粒径及び最大粒径は、導電粒子５の平均粒径及び最大粒以下であることが望ましい。その理由は、フィラー１２の粒径が大きいと、導電粒子５と分離しやすくなり、導電粒子５の沈殿抑制効果を得にくくなるためである。また、フィラー１２が導電性を得るために周囲にメッキ処理をすることも可能である。メッキの種類としては、Ｃｕ、Ｎｉ、Ａｕ等があげられるが、メッキ厚は０．１μｍ以下とごく薄くすることが望ましい。   The average particle size and the maximum particle size of the filler 12 are desirably equal to or less than the average particle size and the maximum particle of the conductive particles 5. The reason is that if the particle size of the filler 12 is large, the filler 12 is easily separated from the conductive particles 5, and it is difficult to obtain the effect of suppressing the precipitation of the conductive particles 5. Moreover, it is also possible to perform a plating process around the filler 12 in order to obtain conductivity. Examples of the type of plating include Cu, Ni, Au, etc., but it is desirable that the plating thickness be as thin as 0.1 μm or less.

導電粒子５同士間の接続状態については、図１（ｄ）に示すように実装工程中の加熱により、最外層の金属層８が溶融して、隣接する導電粒子５や半導体素子１側の電極パッド３や配線基板２側の電極パッド４と金属結合した後、再び固化している。このため、半導体素子１と配線基板２とは確実な導通を確保することが可能となる。
これらの導電粒子５及び導電粒子間結合部分は、第２の樹脂（絶縁樹脂）９に保護されている為、熱応力や落下衝撃、搬送中に生じる外力等に対しても強く、高信頼性を確保することが出来る。さらに本バンプ構造の場合、導電粒子５の最外層の導電層８が溶融して導電粒子５間で金属結合が行なわれる際に、金属部分同士が濡れて結合する為、濡れ現象の際に発現する金属部分の表面張力により、導電粒子５が電極パッド３上及び導電性樹脂バンプ６の中心部分に集合する現象が発現する。As for the connection state between the conductive particles 5, as shown in FIG. 1D, the outermost metal layer 8 is melted by heating during the mounting process, and the adjacent conductive particles 5 and the electrode on the semiconductor element 1 side. After metal bonding with the pad 3 and the electrode pad 4 on the wiring board 2 side, it is solidified again. For this reason, it is possible to ensure reliable conduction between the semiconductor element 1 and the wiring board 2.
Since these conductive particles 5 and the conductive particle bonding portions are protected by the second resin (insulating resin) 9, they are resistant to thermal stress, drop impact, external force generated during transportation, and the like. Can be secured. Further, in the case of this bump structure, when the outermost conductive layer 8 of the conductive particles 5 is melted and metal bonding is performed between the conductive particles 5, the metal portions are wetted and bonded to each other. Due to the surface tension of the metal part, the phenomenon that the conductive particles 5 gather on the electrode pad 3 and the central part of the conductive resin bump 6 appears.

なお、この集合現象を発現させるためには、金属層８の溶融時に第２の樹脂（絶縁樹脂）９は、ほとんど未硬化の状態で十分に粘度が低く、導電性樹脂バンプ６内で導電粒子５が移動可能であることが条件となる。さらに導電粒子５の導電層８の溶融する部分の厚さが厚いほど、集合現象が発現しやすい。この集合現象が発現することにより、導電性樹脂バンプ６の最外層は、第２の樹脂（絶縁樹脂）９で覆われることになるため、本バンプ構造は、導電性樹脂バンプ６の表面は第２の樹脂（絶縁樹脂）９による絶縁性を有し、導電性樹脂バンプ６内は導電粒子５により導電性を有する構造を得ることが可能となる。   In order to develop this aggregation phenomenon, the second resin (insulating resin) 9 is sufficiently uncured in the uncured state when the metal layer 8 is melted, and the conductive resin bumps 6 have conductive particles. The condition is that 5 is movable. Furthermore, as the thickness of the portion of the conductive particle 5 where the conductive layer 8 melts is thicker, the aggregation phenomenon is more likely to occur. As a result of this collective phenomenon, the outermost layer of the conductive resin bump 6 is covered with the second resin (insulating resin) 9, so that the surface of the conductive resin bump 6 is the first in this bump structure. It is possible to obtain a structure having conductivity by the conductive particles 5 in the conductive resin bump 6.

従って本発明の実装構造に関しては、半導体素子１と配線基板２と間の隙間に異物が混入した際でも、バンプ外周部が絶縁性を有しているためにバンプ間ショートによる不具合を防ぐことが可能となる。   Therefore, with respect to the mounting structure of the present invention, even when foreign matter is mixed into the gap between the semiconductor element 1 and the wiring substrate 2, the outer periphery of the bump has an insulating property, so that a problem due to a short between the bumps can be prevented. It becomes possible.

次に本発明の実装構造を実現する為の実装方法の一例を図を参照して詳細に述べる。
図３（ａ）、（ｂ）は本発明の半導体装置の実装方法の一例を示す工程図である。
まず、図３（ａ）に示すように、半導体素子１及び配線基板２を用意し、半導体素子１の電極パッド３上に導電性樹脂バンプ６を形成する。導電性樹脂バンプ６の形成方法はスクリーン印刷法が一般的であるが、他の方法、例えばディスペンスによる塗布等でも可能である。なお、図３（ａ）では、半導体素子１側に導電性樹脂バンプ６を形成しているが、本発明は限定されるものではなく、配線基板２側のみでもよく、あるいは半導体素子１及び配線基板２の両方に導線性樹脂バンプ６を形成しても良い。このとき、形成した導電性樹脂バンプ６は、未硬化の状態にしておく。Next, an example of a mounting method for realizing the mounting structure of the present invention will be described in detail with reference to the drawings.
3A and 3B are process diagrams showing an example of a semiconductor device mounting method according to the present invention.
First, as shown in FIG. 3A, the semiconductor element 1 and the wiring substrate 2 are prepared, and the conductive resin bump 6 is formed on the electrode pad 3 of the semiconductor element 1. The method for forming the conductive resin bump 6 is generally a screen printing method, but other methods such as application by dispensing are also possible. In FIG. 3A, the conductive resin bump 6 is formed on the semiconductor element 1 side. However, the present invention is not limited, and may be only on the wiring board 2 side, or the semiconductor element 1 and the wiring. Conductive resin bumps 6 may be formed on both of the substrates 2. At this time, the formed conductive resin bump 6 is left in an uncured state.

次に半導体素子１と配線基板２との位置合わせを行った後、マウンタの搭載高さ位置制御機能を使って、半導体素子１側の導電性樹脂バンプ６と配線基板２側の導電性樹脂バンプ６とを確実に接触させる。これと共に導電性樹脂バンプ６が潰れて隣同士の導電性樹脂バンプ６がショートしない高さで保持したまま導電粒子５の金属層８の溶融温度以上の温度で加熱を行ない、導電粒子５の金属層８を溶融させて導電粒子５同士間を結合させる。一例をあげると、Pb／Sn共晶はんだの場合は、融点が１８３℃であるため、２００℃程度に加熱すると良い。   Next, after aligning the semiconductor element 1 and the wiring board 2, using the mounting height position control function of the mounter, the conductive resin bump 6 on the semiconductor element 1 side and the conductive resin bump on the wiring board 2 side are used. 6 is brought into contact with each other. At the same time, the conductive resin bumps 6 are crushed and the conductive resin bumps 6 adjacent to each other are heated at a temperature not lower than the melting temperature of the metal layer 8 of the conductive particles 5 while being held at such a height that the metal of the conductive particles 5 is obtained. The layer 8 is melted to bond the conductive particles 5 together. As an example, in the case of Pb / Sn eutectic solder, the melting point is 183 ° C., so it is preferable to heat to about 200 ° C.

この工程で注意すべきことは、導電粒子５の金属部分（導電層８）同士が濡れて結合する際の濡れ現象で発現する金属部分の表面張力により、導電粒子５が電極パッド５上及び導電性樹脂バンプ６の中心部分に集まる現象を妨げないようにすることである。そのためには、金属層８の溶融時に第２の樹脂（絶縁樹脂）９は、ほとんど未硬化の状態で十分に粘度が低く、導電性樹脂バンプ６内で導電粒子５が移動可能であることが条件となる。このため、導電層８を構成する金属の融点に比較し、必要以上に温度を高くすると、第２の樹脂（絶縁樹脂）９の硬化が早まって、粘度上昇により導電粒子５の移動が困難となるので注意が必要である。   What should be noted in this step is that the conductive particles 5 are on the electrode pads 5 and conductive due to the surface tension of the metal parts that are manifested by the wetting phenomenon when the metal parts (conductive layer 8) of the conductive particles 5 are wet and bonded together. This is to prevent the phenomenon of gathering at the central portion of the conductive resin bump 6 from being disturbed. For this purpose, the second resin (insulating resin) 9 is sufficiently uncured and has a sufficiently low viscosity when the metal layer 8 is melted, and the conductive particles 5 can move within the conductive resin bumps 6. It becomes a condition. For this reason, if the temperature is increased more than necessary compared to the melting point of the metal constituting the conductive layer 8, the second resin (insulating resin) 9 is hardened quickly, and it is difficult to move the conductive particles 5 due to an increase in viscosity. It is necessary to be careful.

なお、この現象を確実に行なう為に、第２の樹脂（絶縁樹脂）９の硬化を遅らせることも有効であり、その手段としては、エポキシ樹脂の主剤と硬化剤との配合量及び反応促進剤の添加量を調整することで可能となる。導電粒子５同士間の金属結合が完了した後、少なくとも半導体素子１の自重で未硬化の導電性樹脂バンプ６が潰れなくなる程度まで導電性樹脂バンプ６の硬化を進める。その後、加熱オーブン等を用いて、第２の樹脂（絶縁樹脂）９を完全に硬化させることで、本発明の実装構造が完成する（図３（ｂ））。   In order to reliably perform this phenomenon, it is also effective to delay the curing of the second resin (insulating resin) 9, and the means thereof is the blending amount of the main component of epoxy resin and the curing agent and the reaction accelerator. It becomes possible by adjusting the amount of addition. After the metal bonding between the conductive particles 5 is completed, the curing of the conductive resin bumps 6 is advanced to the extent that the uncured conductive resin bumps 6 are not crushed by the weight of the semiconductor element 1 at least. Then, the mounting structure of the present invention is completed by completely curing the second resin (insulating resin) 9 using a heating oven or the like (FIG. 3B).

また、別の方法としては、配線基板２への半導体素子１の搭載時に半導体素子１の自重で未硬化の導電性樹脂バンプ６が潰れない工夫をしておくことで、マウンタに高さ位置制御機能が無くても実装することが可能である。
一例をあげると、導通を確保する必要がない電極パッド３、４等に半導体素子１の自重を支えて高さの確保が可能なダミーバンプをあらかじめ形成しておけばよい。その後の工程は、前記と同様に実施することが可能である。As another method, when mounting the semiconductor element 1 on the wiring board 2, the unpositioned conductive resin bump 6 is not crushed by the weight of the semiconductor element 1, so that the height position control is performed on the mounter. Even if there is no function, it can be implemented.
As an example, dummy bumps that can secure the height by supporting the self-weight of the semiconductor element 1 may be formed in advance on the electrode pads 3 and 4 that do not need to ensure conduction. Subsequent steps can be performed in the same manner as described above.

なお、上述した実施例は、本発明の好適な実施例を示すものであり、本発明はそれに限定されることなく、その要旨を逸脱しない範囲内において、種々変形実施が可能である。   The above-described embodiments show preferred embodiments of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention.

図４は本発明に係る半導体装置の他の実装断面構造を示す模式図である。図５（ａ）〜（ｃ）は本発明の半導体装置の実装方法の他の一例を示す工程図である。尚、図５（ａ）、（ｂ）は図３（ａ）、（ｂ）と同様であるため説明を省略する。
本発明の実装構造は、図４に示すように半導体素子１と配線基板２との間の隙間を第３の樹脂（アンダーフィル樹脂）１０で封止することも可能である。
すなわち、図５（ｃ）に示すように半導体素子１と配線基板２との間の隙間を第３の樹脂（アンダーフィル樹脂）１０で封止する場合は、毛細管現象を利用して第３の樹脂（アンダーフィル樹脂）１０を充填し、第３の樹脂１０を硬化することで、本発明の実装構造が完了する。FIG. 4 is a schematic view showing another mounting cross-sectional structure of the semiconductor device according to the present invention. 5A to 5C are process diagrams showing another example of the semiconductor device mounting method of the present invention. 5 (a) and 5 (b) are the same as FIGS. 3 (a) and 3 (b), and a description thereof will be omitted.
In the mounting structure of the present invention, the gap between the semiconductor element 1 and the wiring board 2 can be sealed with a third resin (underfill resin) 10 as shown in FIG.
That is, when the gap between the semiconductor element 1 and the wiring substrate 2 is sealed with the third resin (underfill resin) 10 as shown in FIG. The mounting structure of the present invention is completed by filling the resin (underfill resin) 10 and curing the third resin 10.

第３の樹脂（アンダーフィル樹脂）１０については、導電性樹脂バンプ６に使用した第２の樹脂（絶縁樹脂）９と同系統のものを用いることが可能であり、無機充填剤を混入して、第３の樹脂（アンダーフィル樹脂）１０の熱膨張係数や弾性率を調整することも可能である。無機充填剤は、球状シリカが一般的であり、平均粒径は２〜３μｍが一般的であるが、本発明はこれに限定されない。
このように構成しても実施例１と同様の効果が得られる。The third resin (underfill resin) 10 can be of the same type as the second resin (insulating resin) 9 used for the conductive resin bump 6 and is mixed with an inorganic filler. It is also possible to adjust the thermal expansion coefficient and elastic modulus of the third resin (underfill resin) 10. The inorganic filler is generally spherical silica, and the average particle size is generally 2 to 3 μm, but the present invention is not limited to this.
Even if comprised in this way, the effect similar to Example 1 is acquired.

〔効果〕
フリップチップやＣＳＰのように、半導体素子の電極パッドと配線基板の電極パッドとが向かい合って接続される場合、半導体素子の熱膨張係数と配線基板の熱膨張係数との間に差がある場合でも、本発明の実装構造を適用すればよい。これは、導電性樹脂バンプの体積の大部分を占めているのが樹脂であり、導電性樹脂バンプの弾性率を低くすることができるためである。この効果により半導体素子置と配線基板との熱膨張差により生じる応力を緩和することが可能になる。この応力緩和効果は導電性樹脂バンプの破壊の防止のみでなく、半導体素子や配線基板のクラックを防止する効果がある。〔effect〕
Even when there is a difference between the thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the wiring board when the electrode pad of the semiconductor element and the electrode pad of the wiring board are connected to face each other like a flip chip or a CSP. The mounting structure of the present invention may be applied. This is because the resin occupies most of the volume of the conductive resin bump, and the elastic modulus of the conductive resin bump can be lowered. This effect makes it possible to relieve the stress caused by the difference in thermal expansion between the semiconductor element placement and the wiring board. This stress relaxation effect is effective not only in preventing the destruction of the conductive resin bumps but also in preventing cracks in the semiconductor element and the wiring board.

さらに導電性樹脂バンプ中の各導電粒子間の結合部分は周囲の絶縁樹脂によって保護されている為、応力がかかっても結合部分が破壊されにくい。これらの効果により、高信頼性を確保することが容易になる。また、導電粒子の表面が溶融して各導電粒子間で結合する為、導電性樹脂バンプ体積の大部分を絶縁性樹脂が占めている場合でも、安定した導通を確保可能である。さらに本バンプ構造は、導電性樹脂バンプの表面は第２の樹脂（絶縁樹脂）による絶縁性を有し、導電性樹脂バンプ内は導電粒子により導電性を有する構造を得ることが可能となる。従って半導体素子１と配線基板２との間の隙間に異物が混入した際でも、導電性樹脂バンプの最外層が絶縁性を有しているためにバンプ間ショートによる不具合を防ぐことが可能となる。   Furthermore, since the joint portion between the conductive particles in the conductive resin bump is protected by the surrounding insulating resin, the joint portion is not easily broken even when stress is applied. These effects make it easy to ensure high reliability. In addition, since the surface of the conductive particles melts and bonds between the conductive particles, stable conduction can be ensured even when the insulating resin occupies most of the conductive resin bump volume. Further, in this bump structure, the surface of the conductive resin bump has an insulating property by the second resin (insulating resin), and it becomes possible to obtain a conductive structure by the conductive particles in the conductive resin bump. Therefore, even when foreign matter is mixed in the gap between the semiconductor element 1 and the wiring board 2, the outermost layer of the conductive resin bumps has an insulating property, so that it is possible to prevent problems due to shorts between the bumps. .

この出願は、２００７年８月２７日に出願された日本出願特願２００７−２２００１０を基礎とする優先権を主張し、その開示の全てをここに取り込む。   This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2007-222010 for which it applied on August 27, 2007, and takes in those the indications of all here.

（ａ）は本発明に係る半導体装置の一例を示す部分断面図であり、（ｂ）は、導電性樹脂バンプ６を形成している導電粒子の断面模式図であり、（ｃ）は、導電性樹脂バンプの部分拡大図であり、（ｄ）は導電性樹脂バンプの導電粒子間の結合状態の模式図である。(A) is a fragmentary sectional view which shows an example of the semiconductor device which concerns on this invention, (b) is a cross-sectional schematic diagram of the electroconductive particle which forms the conductive resin bump 6, (c) is electroconductive. It is the elements on larger scale of a conductive resin bump, (d) is a schematic diagram of the coupling | bonding state between the conductive particles of a conductive resin bump. 本発明に係る半導体装置の実装構造の変形例を示す部分断面図である。It is a fragmentary sectional view which shows the modification of the mounting structure of the semiconductor device which concerns on this invention. （ａ）〜（ｂ）は本発明の半導体装置の実装方法の一例を示す工程図である。(A)-(b) is process drawing which shows an example of the mounting method of the semiconductor device of this invention. 本発明に係る半導体装置の他の実装断面構造を示す模式図である。It is a schematic diagram which shows the other mounting cross-section of the semiconductor device which concerns on this invention. （ａ）〜（ｃ）は本発明の半導体装置の実装方法の他の一例を示す工程図である。(A)-(c) is process drawing which shows another example of the mounting method of the semiconductor device of this invention.

符号の説明Explanation of symbols

１ 半導体素子
２ 配線基板
３ 電極パッド（ＬＳＩ側）
４ 電極パッド（配線基板側）
５ 導電粒子
６ 導電性樹脂バンプ
７ 第１の樹脂（樹脂コア）
８ 導電層
９ 第２の樹脂（絶縁樹脂）
１０ 第３の樹脂（アンダーフィル樹脂）
１１ 金属結合部
１２ フィラー
１００ 半導体装置1 Semiconductor element 2 Wiring board 3 Electrode pad (LSI side)
4 Electrode pads (wiring board side)
5 Conductive Particle 6 Conductive Resin Bump 7 First Resin (Resin Core)
8 Conductive layer 9 Second resin (insulating resin)
10 Third resin (underfill resin)
11 Metal Bonding Section 12 Filler 100 Semiconductor Device

Claims (10)

半導体素子に形成された第１の電極パッドと配線基板に形成された第２の電極パッドとが向かい合って接続された半導体装置の実装構造において、前記第１の電極パッドと前記第２の電極パッドとを電気的に接続するバンプは、第１の樹脂からなるコア部の表面に金属層が施された複数の導電粒子と、前記導電粒子を被覆する第２の樹脂を備え、前記導電粒子の前記金属層は各導電粒子間を結合していることを特徴とする半導体装置の実装構造。 In a mounting structure of a semiconductor device in which a first electrode pad formed on a semiconductor element and a second electrode pad formed on a wiring board are connected to face each other, the first electrode pad and the second electrode pad The bumps that electrically connect the conductive particles are provided with a plurality of conductive particles having a metal layer on the surface of the core portion made of the first resin, and a second resin that covers the conductive particles. mounting structure of the metal layer and wherein a bonded between each conductive particle. 前記金属層の少なくとも一部を溶融して各導電粒子間を結合したことを特徴とする請求項１記載の半導体装置の実装構造。   2. The semiconductor device mounting structure according to claim 1, wherein at least a part of the metal layer is melted to bond the conductive particles. 前記バンプ中の導電粒子の比重が、前記バンプ中の導電粒子以外の絶縁部分の比重の３倍以下であることを特徴とする請求項１または２に記載の半導体装置の実装構造。   3. The semiconductor device mounting structure according to claim 1, wherein the specific gravity of the conductive particles in the bump is three times or less the specific gravity of an insulating portion other than the conductive particles in the bump. 前記第１の樹脂は熱硬化性樹脂であり、前記バンプ中には導電粒子とともに第２の樹脂と同じ比重のフィラーが混入されていることを特徴とする請求項１から３のいずれか１項に記載の半導体装置の実装構造。   The said 1st resin is a thermosetting resin, The filler of the same specific gravity as 2nd resin is mixed with the conductive particle in the said bump, The any one of Claim 1 to 3 characterized by the above-mentioned. 2. A mounting structure of the semiconductor device according to 1. 前記第２の樹脂は、前記金属層に形成された酸化膜を除去する成分を含むことを特徴とする請求項１から４のいずれか１項に記載の半導体装置の実装構造。   5. The mounting structure of a semiconductor device according to claim 1, wherein the second resin includes a component for removing an oxide film formed on the metal layer. 6. 前記第１の樹脂は、熱硬化性樹脂であることを特徴とする請求項１から５のいずれか１項に記載の半導体装置の実装構造。   The semiconductor device mounting structure according to claim 1, wherein the first resin is a thermosetting resin. 前記バンプの周囲を第３の樹脂で封止したことを特徴とする請求項１から６のいずれか１項に記載の半導体装置の実装構造。   7. The semiconductor device mounting structure according to claim 1, wherein the periphery of the bump is sealed with a third resin. 前記半導体素子がチップサイズパッケージであることを特徴とする請求項１から７のいずれか１項に記載の半導体装置の実装構造。8. The semiconductor device mounting structure according to claim 1, wherein the semiconductor element is a chip size package. 半導体素子の電極パッドまたは配線基板の電極パッドの少なくとも一方に、第１の樹脂からなるコア部の表面に金属層が形成された複数の導電粒子と第２の樹脂とを含んだ導電性ペーストを供給する工程と、
前記半導体素子の前記電極パッドと前記配線基板の前記電極パッドが向かい合い、前記半導体素子の前記電極パッドと前記配線基板の前記電極パッドの間に前記導電性ペーストが配置されるように前記半導体素子を前記配線基板に位置合わせして搭載するとともに、前記半導体素子と前記配線基板との間の隙間を一定に制御した状態で加熱を行ない、前記導電粒子の周囲の金属を溶融させて前記導電粒子間の表面を結合させる工程と、
前記導電性ペーストを硬化させる工程と、を含むことを特徴とする半導体装置の実装方法。 A conductive paste including a plurality of conductive particles having a metal layer formed on a surface of a core portion made of a first resin and a second resin is applied to at least one of an electrode pad of a semiconductor element or an electrode pad of a wiring board. Supplying, and
The semiconductor element is arranged such that the electrode pad of the semiconductor element and the electrode pad of the wiring board face each other, and the conductive paste is disposed between the electrode pad of the semiconductor element and the electrode pad of the wiring board. In addition to being mounted in alignment with the wiring board, heating is performed in a state where the gap between the semiconductor element and the wiring board is controlled to be constant, and the metal around the conductive particles is melted so that the gap between the conductive particles is increased. Bonding the surfaces of
Curing the conductive paste, and mounting the semiconductor device. 半導体素子の電極パッドまたは配線基板の電極パッドの少なくとも一方に、第１の樹脂からなるコア部の表面に金属層が形成された複数の導電粒子と第２の樹脂とを含んだ導電性ペーストを供給する工程と、
前記半導体素子の前記電極パッドと前記配線基板の前記電極パッドが向かい合い、前記半導体素子の前記電極パッドと前記配線基板の前記電極パッドの間に前記導電性ペーストが配置されるように前記半導体素子を前記配線基板に位置合わせして搭載するとともに、前記半導体素子と前記配線基板との間の隙間を一定に制御した状態で加熱を行ない、前記導電粒子の周囲の金属を溶融させて前記導電粒子間の表面を結合させる工程と、
前記導電性ペーストを硬化させる工程と、
硬化した前記導電性ペーストと前記両電極パッドとの間に第３の樹脂を封止した後硬化させる工程とを含むことを特徴とする半導体装置の実装方法。 A conductive paste including a plurality of conductive particles having a metal layer formed on a surface of a core portion made of a first resin and a second resin is applied to at least one of an electrode pad of a semiconductor element or an electrode pad of a wiring board. Supplying, and
The semiconductor element is arranged such that the electrode pad of the semiconductor element and the electrode pad of the wiring board face each other, and the conductive paste is disposed between the electrode pad of the semiconductor element and the electrode pad of the wiring board. Positioning and mounting on the wiring substrate, heating is performed in a state where the gap between the semiconductor element and the wiring substrate is controlled to be constant, and the metal around the conductive particles is melted to form a space between the conductive particles. Bonding the surfaces of
Curing the conductive paste;
A method of mounting a semiconductor device, comprising: sealing a third resin between the cured conductive paste and the electrode pads, followed by curing.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02280334A (en) * 1989-04-21 1990-11-16 Citizen Watch Co Ltd Semiconductor device and manufacture thereof
JPH05259166A (en) * 1992-03-13 1993-10-08 Hitachi Ltd Dendrite bump and its manufacturing method
JP2000323511A (en) * 1999-05-12 2000-11-24 Mitsui High Tec Inc Bonding member for surface mounting
JP2004296806A (en) * 2003-03-27 2004-10-21 Seiko Epson Corp Semiconductor device and its manufacturing process
JP2007201106A (en) * 2006-01-25 2007-08-09 Fujitsu Ltd Semiconductor element connection bump and semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02280334A (en) * 1989-04-21 1990-11-16 Citizen Watch Co Ltd Semiconductor device and manufacture thereof
JPH05259166A (en) * 1992-03-13 1993-10-08 Hitachi Ltd Dendrite bump and its manufacturing method
JP2000323511A (en) * 1999-05-12 2000-11-24 Mitsui High Tec Inc Bonding member for surface mounting
JP2004296806A (en) * 2003-03-27 2004-10-21 Seiko Epson Corp Semiconductor device and its manufacturing process
JP2007201106A (en) * 2006-01-25 2007-08-09 Fujitsu Ltd Semiconductor element connection bump and semiconductor device

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