JP2013055291A - Method for manufacturing semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor package capable of preventing the occurrence of a failure due to heat.SOLUTION: The method of the present invention for manufacturing a semiconductor package 1 comprises a step of preparing a sheet-like member 104 and a step of forming a first reinforcing member 4 by removing part of the sheet-like member 104. A conductor pattern 221 is provided with a plurality of terminals 221b. In the step of forming the first reinforcing member 4, those portions of the sheet-like member 104 which correspond to the terminals 221b are removed to form a plurality of through holes 422 penetrating the first reinforcing member 4 in the thickness direction.

Description

  The present invention relates to a method for manufacturing a semiconductor package.

  In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and further high-density mounting of electronic components have progressed. Semiconductor packages used in these electronic devices have been In addition, the size and number of pins are increasing.

  With the miniaturization of semiconductor packages, the conventional package using a lead frame has a limit on miniaturization. Therefore, recently, it is assumed that a chip is mounted on a circuit board, and BGA (Ball Grid) is used. Array) and a new area mounting type package system such as CSP (Chip Scale Package) have been proposed.

  In general, an interposer used for a new package such as BGA or CSP is formed by forming a conductor pattern or a conductor post on a substrate obtained by impregnating a fiber base material with a resin composition.

  Such an interposer has a large difference in thermal expansion coefficient from the chip. Further, since the interposer usually has a larger area than the chip, the area of the portion not in contact with the chip is large. Such a portion not in contact with the chip is extremely low in rigidity, and tends to warp with the chip side outside at room temperature due to the difference in thermal expansion between the chip and the interposer as described above.

  Meanwhile, a semiconductor package having a so-called POP (Package On Package) structure in which two packages (top package and bottom package) each having an interposer are stacked is known.

  In the conventional POP structure package, the bottom package interposer tends to warp due to the difference in thermal expansion from the chip as described above, and there is a problem in that the electrical connection reliability is lowered.

JP 2009-81261 A

  The objective of this invention is providing the manufacturing method of the semiconductor package which can prevent generation | occurrence | production of the malfunction by heat.

Such an object is achieved by the present inventions (1) to (11) below.
(1) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A semiconductor device connected to the one surface of the substrate and electrically connected to the first conductor pattern, and the semiconductor device on the surface of the substrate on the semiconductor device side. A method of manufacturing a semiconductor device comprising a reinforcing member bonded to a portion that is not made and having a smaller thermal expansion coefficient than the substrate,
Preparing a sheet-like member;
Forming the reinforcing member by removing a part of the sheet-like member,
The first conductor pattern includes a plurality of terminals,
In the step of forming the reinforcing member, a plurality of through holes penetrating in the thickness direction are formed by removing portions corresponding to the plurality of terminals of the sheet-like member. Method.

(2) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A semiconductor device connected to the one surface of the substrate and electrically connected to the first conductor pattern, and the semiconductor device on the surface of the substrate on the semiconductor device side. A first reinforcing member that is bonded to an unfinished portion and has a smaller thermal expansion coefficient than the substrate; and a second reinforcing member that is bonded to a surface of the substrate opposite to the semiconductor element and has a smaller thermal expansion coefficient than the substrate. A method of manufacturing a semiconductor package comprising a reinforcing member,
Preparing a sheet-like member;
Forming the first reinforcing member by removing a part of the sheet-like member,
The first conductor pattern includes a plurality of terminals,
In the step of forming the first reinforcing member, a plurality of through holes penetrating in the thickness direction are formed by removing portions corresponding to the plurality of terminals of the sheet-like member. Manufacturing method.

  (3) The method for manufacturing a semiconductor package according to (2), further including a step of bonding the sheet-like member to the substrate before the step of forming the first reinforcing member.

  (4) The method for manufacturing a semiconductor package according to (2), further including a step of bonding the first reinforcing member to the substrate after the step of forming the first reinforcing member.

(5) The substrate is provided with a heat conductive portion that penetrates in the thickness direction and has higher thermal conductivity than the substrate,
The above (3) or (4), wherein the heat conducting part and the sheet-like member or the first reinforcing member are connected simultaneously with or after the step of joining the sheet-like member or the first reinforcing member to the substrate. The manufacturing method of the semiconductor package of description.

  (6) The method for manufacturing a semiconductor package according to (5), wherein the heat conducting part and the sheet-like member or the first reinforcing member are connected via a connecting part.

  (7) The method for manufacturing a semiconductor package according to (6), wherein the connection portion is made of solder.

  (8) The said connection part is a manufacturing method of the semiconductor package as described in said (6) comprised with the resin composition containing an inorganic filler and a resin material.

  (9) Joining the sheet-like member or the first reinforcing member and the substrate in a state where the connecting portion is interposed between the heat conducting portion and the sheet-like member or the first reinforcing member. The semiconductor package according to any one of (6) to (8), wherein the heat conducting part and the sheet-like member or the first reinforcing member are connected via the connection part.

  (10) A hole penetrating in a thickness direction is formed in a portion corresponding to the heat conducting portion of the first reinforcing member, and the hole is formed after the sheet-like member or the first reinforcing member is joined to the substrate. The semiconductor package according to any one of (6) to (8), wherein the connection portion is formed inside.

  (11) The method for manufacturing a semiconductor package according to any one of (1) to (10), wherein the plurality of through holes are formed using laser or etching.

  According to the semiconductor package manufacturing method of the present invention, the obtained semiconductor package has the wiring board reinforced by the reinforcing member, and therefore prevents or suppresses the warpage caused by the difference in thermal expansion coefficient between the wiring board and the semiconductor element. Can do. As a result, when the obtained semiconductor package is joined as a bottom package to the wiring board of another semiconductor package (top package) via a metal bump, the connection reliability of the metal bump, the conductor pattern / conductor inside the wiring board Improving the connection reliability of the posts and the connection reliability of the metal bumps connecting the wiring board and the motherboard.

  In particular, the obtained semiconductor package has a plurality of through holes for arranging metal bumps in the reinforcing member, so that the rigidity of the reinforcing member is excellent and another semiconductor is interposed via the plurality of metal bumps. It can be connected to a wiring board of a package (top package).

1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention. It is a top view which shows the semiconductor package shown in FIG. It is a bottom view which shows the semiconductor package shown in FIG. It is a figure which shows the 1st example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows the 2nd example of the manufacturing method of the semiconductor package shown in FIG. It is sectional drawing which shows typically the semiconductor package which concerns on 2nd Embodiment of this invention. It is a top view which shows the semiconductor package which concerns on 3rd Embodiment of this invention. It is a top view which shows the semiconductor package which concerns on 4th Embodiment of this invention. It is sectional drawing which shows typically an example of the semiconductor device using the semiconductor package obtained with the manufacturing method of this invention.

  Hereinafter, preferred embodiments of a semiconductor package manufacturing method of the present invention will be described with reference to the accompanying drawings.

<First Embodiment>
(Semiconductor package)
First, a semiconductor package obtained by the manufacturing method of the present invention will be described.

  1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention, FIG. 2 is a top view showing the semiconductor package shown in FIG. 1, and FIG. 3 shows the semiconductor package shown in FIG. FIG. 4 is a bottom view, FIG. 4 is a diagram showing a first example of the method for manufacturing the semiconductor package shown in FIG. 1, and FIG. 5 is a diagram showing a second example of the method for manufacturing the semiconductor package shown in FIG. In the following description, for convenience of description, the upper side in FIG. 1 is referred to as “upper” and the lower side is referred to as “lower”. Also, in FIGS. 1 to 5, each part of the semiconductor package is exaggerated for convenience of explanation.

  As shown in FIG. 1, the semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member 4, and a second reinforcing member 5.

  This semiconductor package 1 constitutes a package (bottom package) on the side connected to the mother board of two semiconductor packages stacked on top of each other constituting a POP (Package On Package) structure as will be described in detail later. .

  According to such a semiconductor package 1, since the wiring board 2 is reinforced by the first reinforcing member 4 also in a portion other than the portion joined to the semiconductor element 3, the rigidity of the entire semiconductor package 1 is increased. In particular, since the thermal expansion coefficient of the first reinforcing member 4 is smaller than that of the wiring substrate 2 (specifically, a substrate 21 described later), the semiconductor element 3 is provided over the entire surface of the wiring substrate 2. The warpage of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 can be suppressed or prevented.

  In particular, in the semiconductor package 1, as will be described later, since the plurality of through holes 42 for arranging metal bumps are formed in the first reinforcing member 4, the rigidity of the first reinforcing member 4 is made excellent. Another semiconductor package (top package) and the wiring board 2 can be connected via a plurality of metal bumps.

Hereinafter, each part of the semiconductor package 1 will be sequentially described in detail.
[Wiring board]
The wiring board 2 is a board (first wiring board) that supports the semiconductor element 3, and is, for example, a relay board (interposer) that relays electrical connection between the mounted semiconductor element 3 and a mother board 200 as will be described later. is there. In addition, the wiring substrate 2 is usually a quadrangle such as a square or a rectangle in plan view.

  The wiring board 2 includes a substrate 21, conductor patterns 221, 222, 223, 224, conductor posts 231, 232, 233, and a plurality of heat transfer posts 24.

  In this embodiment, the conductor pattern 221 constitutes a first conductor pattern provided on one surface side of the substrate 21, and the conductor pattern 224 is provided on the other surface side of the substrate 21. A second conductor pattern electrically connected to the conductor pattern is formed.

  The substrate 21 is composed of a plurality (three layers in this embodiment) of insulating layers 211, 212, and 213. More specifically, the substrate 21 is configured by laminating an insulating layer 211, an insulating layer 212, and an insulating layer 213 in this order. In addition, the number of the insulating layers which comprise the board | substrate 21 is not limited to this, One layer or two layers may be sufficient, and four or more layers may be sufficient.

Each of the insulating layers 211, 212, and 213 is made of an insulating material.
Specifically, each insulating layer 211, 212, 213 is composed of a base material (fiber base material) and a resin composition impregnated in the base material. In addition, at least 1 layer of the insulating layers 211, 212, and 213 may be comprised only with the resin composition, without including a base material.

  The base material is used as a core material for the insulating layers 211, 212, and 213. By having such a base material, the rigidity of the substrate 21 can be increased.

  Examples of the base material include glass fiber base materials composed of glass fibers such as glass woven fabrics and glass nonwoven fabrics, polyamide resin fibers such as polyamide resin fibers, aromatic polyamide resin fibers, wholly aromatic polyamide resin fibers, and polyesters. Synthesis composed of woven or non-woven fabric mainly composed of resin fiber, aromatic polyester resin fiber, polyester resin fiber such as wholly aromatic polyester resin fiber, polyimide resin fiber, fluororesin fiber, polybenzoxazole resin fiber, etc. Examples thereof include fiber base materials, kraft paper, cotton linter paper, and paper base materials mainly composed of linter and kraft pulp mixed paper. Among these, as such a base material, a glass fiber base material is preferable. Thereby, the rigidity of the substrate 21 can be increased and the substrate 21 can be thinned. Furthermore, the thermal expansion coefficient of the substrate 21 can be reduced.

  Examples of the glass constituting such a glass fiber substrate include E glass, C glass, A glass, S glass, D glass, NE glass, T glass, H glass, and quartz glass (Q glass). . Among these, T glass is preferable. Thereby, the thermal expansion coefficient of a glass fiber base material can be made small, and, thereby, the thermal expansion coefficient of the board | substrate 21 can be made small.

  Moreover, when the insulating layers 211, 212, and 213 include a base material, the content of the base material in the insulating layers 211, 212, and 213 is preferably 30 to 70 wt%, and 40 to 60 wt%, respectively. Is more preferable. Thereby, the electric insulation and thermal expansion coefficient of each insulating layer can be made sufficiently low while reliably preventing damage such as cracks of these insulating layers.

  The resin composition impregnated in such a base material contains a resin material. As such a resin material, a thermosetting resin is preferably used.

  Examples of the thermosetting resin include an oil-modified resole modified with a novolak-type phenol resin such as a phenol novolak resin, a cresol novolak resin, a bisphenol A novolak resin, an unmodified resole phenol resin, tung oil, linseed oil, walnut oil, and the like. Phenolic resins such as phenolic resins, phenolic resins such as resol type phenolic resins, bisphenol type epoxy resins such as bisphenol A epoxy resin and bisphenol F epoxy resin, novolac type epoxy resins such as novolac epoxy resin and cresol novolac epoxy resin, biphenyl type epoxy resin, di Epoxy resins such as cyclopentadiene-type epoxy resins, naphthol-type epoxy resins, naphthylene ether-type epoxy resins, and other epoxy resins having a naphthalene skeleton, cyanate resins, lily (Urea) resins, resins having a triazine ring such as melamine resins, unsaturated polyester resins, bismaleimide resins, polyurethane resins, diallyl phthalate resins, silicone resins, resins having a benzoxazine ring.

  Among these, a cyanate resin is particularly preferable. Thereby, the thermal expansion coefficient of the board | substrate 21 can be made small enough. Furthermore, the electrical characteristics (low dielectric constant, low dielectric loss tangent, etc.) of the substrate 21 can be made excellent.

Moreover, it is preferable that the said resin composition contains a filler. That is, each of the insulating layers 211, 212, and 213 preferably contains a filler. Thereby, the thermal expansion coefficient of the insulating layers 211, 212, and 213 can be lowered.
Examples of the filler include various inorganic fillers or organic fillers.

  Examples of the inorganic filler (inorganic filler) include silica, alumina, boehmite, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, metal ferrite and other oxides, aluminum hydroxide, magnesium hydroxide and the like. Hydroxides, calcium carbonate (light, heavy), carbonates such as magnesium carbonate, dolomite, dawsonite, sulfates or sulfites such as calcium sulfate, barium sulfate, ammonium sulfate, calcium sulfite, talc, mica, clay, glass fiber Silicates such as calcium silicate, montmorillonite, bentonite, zinc borate, barium metaborate, borate such as aluminum borate, calcium borate, sodium borate, carbon black, graphite, carbon fiber, etc. Other iron powder, copper powder, aluminum powder, Namarihana, molybdenum sulfide, boron fiber, potassium titanate, and a lead zirconate titanate.

  Moreover, synthetic resin powder is mentioned as an organic filler. Examples of the synthetic resin powder include alkyd resin, epoxy resin, silicone resin, phenol resin, polyester, acrylic resin, acetal resin, polyethylene, polyether, polycarbonate, polyamide, polysulfone, polystyrene, polyvinyl chloride, fluororesin, and polypropylene. And various thermosetting resins such as ethylene-vinyl acetate copolymers or powders of thermoplastic resins, or powders of copolymers of these resins. Other examples of organic fillers include aromatic or aliphatic polyamide fibers, polypropylene fibers, polyester fibers, and aramid fibers.

  Among the fillers as described above, it is preferable to use an inorganic filler. Thereby, the thermal expansion coefficient of the insulating layers 211, 212, and 213 can be effectively lowered. In addition, the heat transfer properties of the insulating layers 211, 212, and 213 can be increased.

  In particular, among inorganic fillers, silica is preferable, and fused silica (particularly spherical fused silica) is preferable in terms of excellent low thermal expansion.

  Although the average particle diameter of an inorganic filler is not specifically limited, 0.05-2.0 micrometers is preferable and especially 0.1-1.0 micrometer is preferable. Accordingly, the inorganic filler can be more uniformly dispersed in the insulating layers 211, 212, and 213, and the physical strength and insulating properties of the insulating layers 211, 212, and 213 can be made particularly excellent. .

  In addition, the average particle diameter of the said inorganic filler can be measured with a particle size distribution meter (product made from HORIBA, LA-500), for example. Moreover, in this specification, an average particle diameter refers to the average particle diameter on a volume basis.

  The content of the inorganic filler in the insulating layers 211, 212, and 213 is not particularly limited, but is preferably 30 to 80 wt%, particularly 45 to 75 wt%, when the resin composition excluding the substrate is 100 wt%. Is preferred. When the content is within the above range, the insulating layers 211, 212, and 213 have sufficiently low thermal expansion coefficients and particularly low hygroscopicity.

  In addition to the thermosetting resin described above, the resin composition may contain a thermoplastic resin such as a phenoxy resin, a polyimide resin, a polyamideimide resin, a polyphenylene oxide resin, or a polyethersulfone resin.

  Moreover, the said resin composition may contain additives other than the said components, such as a pigment, dye, and antioxidant, as needed.

  The insulating layers 211, 212, and 213 may be made of the same material as each other or may be made of different materials.

  The average thickness of the substrate 21 composed of a plurality of layers as described above is not particularly limited, but is preferably 30 μm or more and 800 μm or less, and more preferably 30 μm or more and 400 μm or less.

  A conductor pattern 221 is provided on the upper surface of the insulating layer 211 of the substrate 21. A conductor pattern 222 is interposed between the insulating layer 211 and the insulating layer 212. A conductor pattern 223 is interposed between the insulating layer 212 and the insulating layer 213. A conductor pattern 224 is provided on the lower surface of the insulating layer 213.

  In the present embodiment, an insulating layer 251 such as a solder resist is provided on the upper surface of the insulating layer 211, and the conductor pattern 221 is interposed between the insulating layer 211 and the insulating layer 251. . In addition, an insulating layer 252 such as a solder resist is provided on the lower surface of the insulating layer 213, and the conductor pattern 224 is interposed between the insulating layer 213 and the insulating layer 252.

  Each of the conductor patterns 221, 222, 223, and 224 functions as a circuit having a plurality of wirings.

  The conductor pattern 221 has a plurality of terminals 221a that are electrically connected to the semiconductor element 3 and a plurality of terminals 221b that are electrically connected to a top package (not shown).

  The constituent material of the conductor patterns 221, 222, 223, and 224 is not particularly limited as long as it has conductivity, and examples thereof include various metals and various alloys such as copper, a copper-based alloy, aluminum, and an aluminum-based alloy. Can be mentioned. Among these, it is preferable to use copper and a copper-based alloy as the constituent material. Copper and copper-based alloys have relatively high electrical conductivity. Therefore, the electrical characteristics of the wiring board 2 can be improved. Moreover, since copper and a copper-type alloy are excellent also in heat conductivity, the heat dissipation of the wiring board 2 can also be improved.

  In addition, the average thickness of the conductor patterns 221, 222, 223, and 224 is not particularly limited, but is preferably 5 μm or more and 30 μm or less.

  The insulating layer 211 has a via hole penetrating in the thickness direction, and a conductor post (via post) 231 is provided in the via hole. The conductor post 231 passes through the insulating layer 211 in the thickness direction, and has an upper end connected to the conductor pattern 221 and a lower end connected to the conductor pattern 222. Thereby, the conductor pattern 221 and the conductor pattern 222 are electrically connected.

  The semiconductor element 3 is bonded to a plurality of terminals 221a of the conductor pattern 221 via a plurality of metal bumps 31 described later. The plurality of metal bumps 31 penetrate the insulating layer 251 in the thickness direction.

  The insulating layer 212 is provided with a conductor post (via post) 232 that penetrates in the thickness direction. The conductor post 232 has an upper end connected to the conductor pattern 222 and a lower end connected to the conductor pattern 223. Thereby, the conductor pattern 222 and the conductor pattern 223 are electrically connected.

  The insulating layer 213 is provided with a conductor post (via post) 233 penetrating in the thickness direction. The conductor post 233 has an upper end connected to the conductor pattern 223 and a lower end connected to the conductor pattern 224. Thereby, the conductor pattern 223 and the conductor pattern 224 are electrically connected.

  The insulating layer 251 is provided with a plurality of openings penetrating in the thickness direction, and part of the conductor pattern 221 (terminals 221a and 221b) is exposed from each opening. A metal bump 31 is bonded onto each exposed terminal 221 a of the conductor pattern 221, as will be described later, and the semiconductor element 3 is electrically connected via the metal bump 31.

  The insulating layer 252 is provided with a plurality of openings penetrating in the thickness direction, and a part (terminal) of the conductor pattern 224 is exposed from each opening. A metal bump 71 is bonded onto each exposed portion (terminal) of the conductor pattern 224. That is, a plurality of metal bumps 71 are bonded to the surface of the conductor pattern 224 that is the second conductor pattern on the side opposite to the substrate 21.

  The metal bump 71 is for electrically connecting the semiconductor package 1 to, for example, a mother board as will be described later.

  In the present embodiment, the metal bump 71 has a substantially spherical shape. The shape of the metal bump 71 is not limited to this.

  The constituent material of the metal bump 71 is not particularly limited. For example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, tin- Various brazing materials (solder) such as copper and tin-silver-copper can be used.

  The substrate 21 is formed with a plurality of via holes penetrating over the entire area in the thickness direction, and a heat transfer post 24 is provided in each via hole.

  Each heat transfer post 24 penetrates the entire substrate 21 in the thickness direction, and its upper end is exposed from the upper surface of the substrate 21 and its lower end is exposed from the lower surface of the substrate 21. The heat transfer post 24 has an upper end connected to the first reinforcing member 4 via the connecting portion 261 (first connecting portion) and a lower end connected to the second reinforcing member 5 via the connecting portion 262 (second connecting portion). Connected to. Thus, each heat transfer post 24 thermally connects the first reinforcing member 4 and the second reinforcing member 5.

  Each of the heat transfer posts (heat conduction portions) 24 has higher heat transfer properties than the substrate 21 (insulating layer) described above. Thereby, heat can be efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 via the heat transfer post 24. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  Further, since each heat transfer post 24 penetrates the substrate 21 in the thickness direction, it can be formed easily and with high accuracy, similarly to a known conductor post.

  Each heat transfer post 24 may be hollow or solid. Moreover, it does not specifically limit as a cross-sectional shape of each heat-transfer post | mailbox 24, For example, circular, an ellipse, a polygon etc. are mentioned. Further, the number of heat transfer posts 24 is not particularly limited and is arbitrary, but is preferably as large as possible so as not to impair the mechanical strength of the wiring board 2.

  Each heat transfer post 24 does not contribute to the transmission of an electrical signal. Thereby, heat can be more efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 through the heat transfer post 24.

  In the present embodiment, the plurality of heat transfer posts 24 are arranged side by side along the outer peripheral portion of the wiring board 2 at intervals when the wiring board 2 is viewed in plan. In particular, the plurality of heat transfer posts 24 are preferably arranged side by side at equal intervals in the circumferential direction along the outer peripheral portion of the wiring board 2 when the wiring board 2 is viewed in plan. Thereby, the temperature distribution of the wiring board 2 can be made uniform.

  The plurality of heat transfer posts 24 are provided so as not to overlap the conductor patterns 221, 222, 223, and 224 described above when the wiring board 2 is viewed in plan. Thereby, formation of the heat transfer post 24 is simplified, and a short circuit of the conductor patterns 221, 222, 223, and 224 by the heat transfer post 24 can be prevented.

  The constituent material of each heat transfer post 24 is not particularly limited as long as it has a higher heat transfer property than the substrate 21 (insulating layer) described above, but a metal material is preferably used.

  Examples of the metal material include various metals and various alloys such as copper, a copper-based alloy, aluminum, and an aluminum-based alloy. Among these, as such a metal material, it is preferable to use copper, a copper-based alloy, aluminum, or an aluminum-based alloy because of excellent heat conductivity.

  Further, the constituent material of the heat transfer post 24 may be different from the constituent material of the conductor posts 231 to 233 described above, but is preferably the same as the constituent material of the conductor posts 231 to 233. Thereby, the heat transfer post 24 can be formed together with the formation of the conductor posts 231 to 233. Therefore, the manufacturing of the semiconductor package 1 is simplified, and the semiconductor package 1 can be made inexpensive.

  The connection portion 261 is provided between the heat transfer post 24 and the first reinforcement member 4, and the connection portion 262 is provided between the heat transfer post 24 and the second reinforcement member 5. Thereby, the thermal connection between the heat transfer post 24 and the first reinforcing member 4 and the thermal connection between the heat transfer post 24 and the second reinforcing member 5 are easily and reliably performed.

  Further, as the constituent materials of the connecting portions 261 and 262, for example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, tin, respectively. -Resin composition comprised including various brazing materials (solder) such as copper-based, tin-silver-copper-based, inorganic filler, and resin material.

  When the connection portions 261 and 262 are made of a resin composition, examples of the inorganic filler (inorganic filler) used in the resin composition include metals such as Au, Ag, and Pt, silica, alumina, boehmite, and diatomaceous earth. , Oxides such as titanium oxide, iron oxide, zinc oxide, magnesium oxide and metal ferrite, nitrides such as boron nitride, silicon nitride, gallium nitride and titanium nitride, hydroxides such as aluminum hydroxide and magnesium hydroxide, carbonic acid Calcium (light, heavy), carbonates such as magnesium carbonate, dolomite, dosonite, sulfates or sulfites such as calcium sulfate, barium sulfate, ammonium sulfate, calcium sulfite, talc, mica, clay, glass fiber, calcium silicate, Silicates such as montmorillonite and bentonite, zinc borate, barium metaborate , Borates such as aluminum borate, calcium borate, sodium borate, carbon such as carbon black, graphite, carbon fiber, other iron powder, copper powder, aluminum powder, zinc white, molybdenum sulfide, boron fiber, titanic acid Examples include potassium and lead zirconate titanate. In addition, when the thing which has electroconductivity is used as an inorganic filler, an insulation process is performed as needed.

  Among them, as the inorganic filler, from the viewpoint of excellent insulation and thermal conductivity, silica, alumina, boehmite, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, metal ferrite and other oxides, nitriding Nitride such as boron, silicon nitride, gallium nitride and titanium nitride is preferable.

  Moreover, when the connection parts 261 and 262 are made of a resin composition, examples of the resin material used for the resin composition include various thermoplastic resins and various thermosetting resins.

  Examples of the thermoplastic resin used for the connecting portions 261 and 262 (resin composition) include polyolefins such as polyethylene, polypropylene, and ethylene-vinyl acetate copolymer, modified polyolefins, polyamides (eg, nylon 6, nylon 46, nylon 66). , Nylon 610, Nylon 612, Nylon 11, Nylon 12, Nylon 6-12, Nylon 6-66), liquid crystalline polymers such as thermoplastic polyimide, aromatic polyester, polyphenylene oxide, polyphenylene sulfide, polycarbonate, polymethyl methacrylate, polyether , Polyether ether ketone, polyether imide, polyacetal, styrene, polyolefin, polyvinyl chloride, polyurethane, polyester, polyamide, polybutadiene, Various thermoplastic elastomers such as Lance polyisoprene, fluororubber, chlorinated polyethylene, etc., or copolymers, blends, polymer alloys, etc. mainly composed of these are included, one or two of these The above can be mixed and used.

  Moreover, as a thermosetting resin used for the connection parts 261 and 262 (resin composition), for example, epoxy resin, phenol resin, urea resin, melamine resin, polyester (unsaturated polyester) resin, polyimide resin, silicone resin, polyurethane Resin, cyanate resin, etc. are mentioned, 1 type or 2 types or more of these can be mixed and used.

[Semiconductor element]
The semiconductor element (first semiconductor element) 3 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light emitting / receiving element.

  The semiconductor element 3 is provided on the upper surface (one surface) side of the substrate 21 of the wiring substrate 2 described above, and is electrically connected to the conductor pattern 221 that is the first conductor pattern.

  Specifically, the semiconductor element 3 is provided with a plurality of terminals (not shown) on its lower surface, and each terminal is electrically connected to the plurality of terminals 221 a of the conductor pattern 221 through the metal bumps 31. It is connected.

  The constituent material of the metal bump 31 is not particularly limited. For example, as in the case of the metal bump 71 described above, for example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin -Various brazing materials (solder) such as silver-bismuth, tin-copper, and tin-silver-copper can be used.

  Further, the semiconductor element 3 is bonded (bonded) to the upper surface of the wiring board 2 through the adhesive layer 32.

  The adhesive layer 32 is made of a material having adhesiveness and insulation, and is made of, for example, a cured product of an underfill material.

  The underfill material is not particularly limited, and a known underfill material can be used, but the same solder bonding resist as that for forming an insulating material 81 described later can also be used.

[First reinforcing member]
The first reinforcing member (stiffener) 4 is bonded to a portion of the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above where the semiconductor element 3 is not bonded.

  This 1st reinforcement member 4 and the board | substrate 21 can be joined through an adhesive agent, for example. Thereby, installation of the 1st reinforcement member 4 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used, but those having excellent thermal conductivity are preferable, and include an inorganic filler and a resin material. Resin compositions can be used. As this resin composition, it can use with the thing similar to the resin composition used for the connection parts 261,262 mentioned above.

  Such an adhesive can constitute at least a part of the insulating layer 251 described above.

  The first reinforcing member 4 has a smaller thermal expansion coefficient than the substrate 21. Thereby, the thermal expansion of the substrate 21 can be suppressed.

  Moreover, the 1st reinforcement member 4 has comprised plate shape. Thereby, the structure of the 1st reinforcement member 4 can be made simple and small.

  In the present embodiment, the surface (that is, the upper surface) opposite to the substrate 21 of the first reinforcing member 4 is positioned closer to the substrate 21 than the surface (that is, the upper surface) opposite to the substrate 21 of the semiconductor element 3. Thereby, when the semiconductor element 3 is installed after the first reinforcing member 4 is installed in manufacturing the semiconductor package 1, the installation of the semiconductor element 3 is facilitated.

  Further, the first reinforcing member 4 has a shape surrounding the periphery of the semiconductor element 3. In the present embodiment, the first reinforcing member 4 has an annular shape (more specifically, a rectangular annular shape) so as to surround the semiconductor element 3. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the effect which improves the rigidity of the wiring board 2 by the 1st reinforcement member 4 can be made excellent.

  Further, as shown in FIG. 2, the first reinforcing member 4 is formed with a plurality of through holes 42 penetrating in the thickness direction. In each through hole 42, for example, when another POP structure is obtained by stacking another semiconductor package 300 on the semiconductor package 1 as described later, metal bumps 400 are arranged (see FIG. 9).

  In the present embodiment, each through hole 42 is circular in plan view. In addition, the planar view shape of each through-hole 42 is not limited to a circle, For example, polygons, such as a quadrangle | tetragon, a pentagon, and a hexagon, may be sufficient.

  Further, the distance between the first reinforcing member 4 and the semiconductor element 3 (the distance between the inner peripheral surface 41 of the first reinforcing member 4 and the outer peripheral surface 33 of the semiconductor element 3) is on the entire circumference of the semiconductor element 3. It is formed so as to be constant throughout. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.

  The first reinforcing member 4 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the semiconductor element 3 and the 1st reinforcement member 4 can reinforce the wiring board 2 integrally, and can suppress the thermal expansion of the semiconductor package 1 whole.

  In addition, the constituent material of the first reinforcing member 4 is not particularly limited as long as it has a thermal expansion coefficient as described above. For example, a metal material, a ceramic material, or the like can be used. It is preferable to use it. When the 1st reinforcement member 4 is comprised with the metal material, the heat dissipation of the 1st reinforcement member 4 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.

  Examples of such Fe-containing alloys include Fe-Ni alloys, Fe-Co-Cr alloys, Fe-Co alloys, Fe-Pt alloys, Fe-Pd alloys, and the like. It is preferable to use a base alloy.

  Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3. Therefore, the semiconductor element 3 and the first reinforcing member 4 can integrally reinforce the wiring board 2.

  The Fe—Ni-based alloy is not particularly limited as long as it contains Fe and Ni. In addition to Fe and Ni, the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included.

  More specifically, examples of the Fe-Ni alloy include Fe-Ni alloys such as Fe-36Ni alloy (Invar), Fe-42Ni alloy (42 alloy), Fe-32Ni-5Co alloy (Super Invar), Ni-Mo-Fe such as Fe-Ni-Co alloy such as Fe-29Ni-17Co alloy (Kovar), Fe-36Ni-12Co alloy (Erin bar), Fe-Ni-Cr-Ti alloy, Ni-28Mo-2Fe alloy An alloy etc. are mentioned. In addition, Fe-Ni-Co alloys are commercially available under trade names such as KV series (manufactured by NEOMAX Materials) such as KV-2, KV-4, KV-6, KV-15, and KV-25, and Nivarox. ing. Moreover, the Fe-Ni alloy is marketed with brand names, such as NS-5 and D-1 (made by NEOMAX material company), for example. Fe-Ni-Cr-Ti alloys are commercially available under trade names such as Ni-Span C-902 (manufactured by Daido Special Metal), EL-3 (manufactured by NEOMAX Material).

  The Fe—Co—Cr alloy is not particularly limited as long as it contains Fe, Co, and Cr. For example, an Fe—Co—Cr alloy such as Fe-54Co-9.5Cr (stainless invar) is used. Is mentioned. Note that the Fe—Co—Cr-based alloy may contain one or more metals of metals such as Ni, Ti, Mo, Pd, and Pt in addition to Fe, Co, and Cr.

  Further, the Fe—Co alloy is not particularly limited as long as it contains Fe and Co, and in addition to Fe and Co, one of metals such as Ni, Ti, Mo, Cr, Pd, and Pt. It may contain seeds or two or more metals.

  Further, the Fe—Pt alloy is not particularly limited as long as it contains Fe and Pt. In addition to Fe and Pt, one of metals such as Co, Ni, Ti, Mo, Cr, and Pd is used. It may contain seeds or two or more metals.

  Further, the Fe—Pd-based alloy is not particularly limited as long as it contains Fe and Pd. In addition to Fe and Pd, one of metals such as Co, Ni, Ti, Mo, Cr, and Pt is used. It may contain seeds or two or more metals.

  In particular, the thermal expansion coefficient of the first reinforcing member 4 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the first reinforcing member 4 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  From the viewpoint of the thermal expansion coefficient as described above, when the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy, the Fe—Ni alloy has a Ni content of 30 wt% or more and 50 wt% or less. It is preferable that the Ni content is 35 wt% or more and 45 wt% or less. Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3. In this case, the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.

  Further, when the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy, the Fe—Ni alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less, The total content of Fe and Ni is more preferably 90 wt% or more and 100 wt% or less. That is, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.

  The average thickness of the first reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less. In addition, although the thickness of the 1st reinforcement member 4 is uniform in this embodiment, you may have a part from which thickness differs. For example, the thickness may decrease or increase continuously or stepwise from the inside to the outside of the first reinforcing member 4.

  A space between the first reinforcing member 4 and the semiconductor element 3 may be filled with a heat conductive material. Thereby, heat can be efficiently transmitted from the semiconductor element 3 to the first reinforcing member 4 through the thermally conductive material. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  Such a heat conductive material is not particularly limited, and examples thereof include a resin composition including an inorganic filler and a resin material. As this resin composition, the thing similar to the resin composition used for the connection part 261,262 mentioned above can be used.

  Moreover, this heat conductive material may use the thing similar to the contact bonding layer 32 (underfill material) mentioned above, and the heat conductive material and the contact bonding layer 32 can also be formed collectively.

[Second reinforcing member]
The second reinforcing member (stiffener) 5 is joined to the lower surface (the other surface) of the substrate 21 of the wiring substrate 2.

  This 2nd reinforcement member 5 and the board | substrate 21 can be joined through an adhesive agent. Thereby, installation of the 2nd reinforcement member 5 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used, but those having excellent thermal conductivity are preferable, and include an inorganic filler and a resin material. Resin compositions can be used. As this resin composition, the thing similar to the resin composition used for the connection part 261,262 mentioned above can be used.

  Such an adhesive can constitute at least a part of the insulating layer 252 described above.

  The second reinforcing member 5 has a smaller coefficient of thermal expansion than the substrate 21, similar to the first reinforcing member 4 described above.

  The second reinforcing member 5 has a plate shape. Thereby, the structure of the 2nd reinforcement member 5 can be made simple and small.

  Further, as shown in FIG. 3, the second reinforcing member 5 includes a portion (frame portion) 52 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21), and metal bumps. And a portion 53 provided between 71. By joining the portion 52 of the second reinforcing member 5 and the wiring substrate 2 (substrate 21), the second reinforcing member 5 can effectively reinforce the wiring substrate 2. Further, the rigidity of the second reinforcing member 5 is increased by joining the portion 53 of the second reinforcing member 5 and the wiring board 2.

  More specifically, the second reinforcing member 5 has a plurality of openings 51 formed so as to surround the metal bumps 71 without contacting the metal bumps 71 described above. Thereby, the ratio of the area which the 2nd reinforcement member 5 occupies for the lower surface of the wiring board 2 can be enlarged. As a result, the effect of increasing the rigidity of the wiring board 2 by the second reinforcing member 5 can be made excellent.

  In the present embodiment, each opening 51 is circular in plan view. In addition, the planar view shape of each opening part 51 is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.

  Each opening 51 is provided corresponding to each metal bump 71 (one-to-one correspondence). Thereby, the rigidity of the second reinforcing member 5 can be made uniform. Moreover, the heat dissipation of the 2nd reinforcement member 5 can also be improved.

  In addition, the distance between the second reinforcing member 5 and each metal bump 71 (distance between the wall surface of the opening 51 and the outer peripheral surface of the metal bump 71 in plan view) extends over the entire circumference of the metal bump 71. It is formed to be constant. Thereby, the integrity of the 2nd reinforcement member 5 and each metal bump 71 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.

  Similarly to the first reinforcing member 4 described above, the second reinforcing member 5 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the 2nd reinforcement member 5 can reinforce the wiring board 2 effectively, and can suppress the thermal expansion of the semiconductor package 1 whole.

  Moreover, it is preferable that the 2nd reinforcement member 5 is comprised with the metal material. Thereby, the heat dissipation of the 2nd reinforcement member 5 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  Although it does not specifically limit as this metal material, From a viewpoint of implement | achieving heat dissipation and low thermal expansion, it is preferable to use a Fe-Ni type alloy.

  As the Fe—Ni alloy, the same material as the first reinforcing member 4 described above can be used.

  In particular, the thermal expansion coefficient of the second reinforcing member 5 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the first reinforcing member 4 is preferably 2 ppm / ° C. or less, more preferably 1 ppm / ° C. or less, and 0 ppm / ° C. Is more preferable. Thereby, the thermal expansion coefficient difference of the 1st reinforcement member 4 and the 2nd reinforcement member 5 can be made small, and the curvature of the wiring board 2 resulting from these thermal expansion differences can be prevented.

  From this point of view, the constituent material of the second reinforcing member 5 is preferably the same or the same as the constituent material of the first reinforcing member 4.

  The average thickness of the second reinforcing member 5 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less.

  An insulating material 81 is provided (filled) between the second reinforcing member 5 and each metal bump 71. Thereby, the contact with the 2nd reinforcement member 5 and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the second reinforcing member 5 can be enhanced while improving the reliability of the semiconductor package 1.

  The insulating material 81 has a shape surrounding the portion (upper part) of the metal bump 71 on the substrate 21 side, and is joined to each metal bump 71. Thereby, the insulating material 81 reinforces the metal bump 71.

The insulating material 81 preferably has a higher thermal conductivity than the substrate 21 of the wiring board 2 described above. Thereby, the thermal conductivity between the metal bump 71 and the second reinforcing member 5 can be made excellent, and the heat dissipation of the semiconductor package 1 can be improved.
Such an insulating material 81 has an insulating property and includes a resin material.

  Such an insulating material 81 is not particularly limited, but is preferably formed of, for example, a solder bonding resin having thermosetting properties.

  Such a solder bonding resin (hereinafter also referred to as “curing flux”) acts as a flux at the time of solder bonding, and then is cured by heating to act as a reinforcing material for the solder bonding portion. Solder bonding resin removes harmful substances such as solder joint surfaces and oxides of solder materials during solder joining, protects the solder joint surfaces, and refines the solder materials to provide good strength and good strength. In addition, the solder bonding resin does not need to be removed by washing after solder bonding, and is heated as it is to become a three-dimensionally crosslinked resin, which acts as a reinforcing material for the solder bonding portion.

  Such a solder bonding resin can be configured to include, for example, a resin (A) having a phenolic hydroxyl group and a curing agent (B) of the resin.

  Although there is no restriction | limiting in particular as resin (A) which has a phenolic hydroxyl group, For example, a phenol novolak resin, an alkylphenol novolak resin, a polyhydric phenol novolak resin, a resole resin, a polyvinyl phenol resin etc. can be mentioned.

  In the curable flux, the content of the resin (A) having a phenolic hydroxyl group is preferably 20 to 80% by weight, and more preferably 25 to 60% by weight of the entire curable flux. If the content of the resin (A) is less than 20% by weight, the effect of removing dirt such as solder and oxides on the metal surface may be reduced, and solder jointability may be deteriorated. When content of resin (A) exceeds 80 weight%, the hardened | cured material which has sufficient physical property cannot be obtained, and there exists a possibility that joining strength and reliability may fall.

  Further, the phenolic hydroxyl group of the resin (A) having a phenolic hydroxyl group effectively removes dirt such as oxides on the solder and the metal surface by its reducing action, and therefore effectively acts as a solder joint flux.

  Moreover, as a hardening | curing agent (B) of resin (A) which has a phenolic hydroxyl group, an epoxy compound, an isocyanate compound, etc. can be mentioned, for example. Examples of the epoxy compound and isocyanate compound include phenol-based epoxy compounds such as bisphenol, phenol novolak, alkylphenol novolak, biphenol, naphthol, and resorcinol, isocyanate compounds, saturated aliphatic, cycloaliphatic, Examples thereof include an epoxy compound and an isocyanate compound modified based on a skeleton such as a saturated aliphatic group.

  The compounding amount of the curing agent (B) is such that the reactive functional group such as epoxy group and isocyanate group of the curing agent is 0.5 to 1.5 equivalent times the phenolic hydroxyl group of the resin (A). It is preferably 0.8 to 1.2 equivalent times. When the reactive functional group of the curing agent is less than 0.5 equivalents of the hydroxyl group, a cured product having sufficient physical properties cannot be obtained, and the reinforcing effect may be reduced, thereby reducing the bonding strength and reliability. There is. When the reactive functional group of the curing agent exceeds 1.5 equivalents of the hydroxyl group, the action of removing dirt such as oxides on the solder and the metal surface is lowered, and there is a possibility that the solderability is deteriorated.

  Such a solder bonding resin (curable flux) is formed because a cured product having good physical properties is formed by the reaction of the resin (A) having a phenolic hydroxyl group and the curing agent (B) of the resin. It is not necessary to remove the flux by washing after soldering, the soldered part is protected by the cured product, and electrical insulation is maintained even in a high temperature and high humidity atmosphere, and soldering with high joining strength and reliability is possible. .

  In addition to the resin (A) having a phenolic hydroxyl group and the curing agent (B) of the resin, the solder bonding resin as described above is dispersed in a microcrystalline state as a curable antioxidant (C). Compound (D) having phenolic hydroxyl group, curing agent (E), solvent (F), curing catalyst, silane coupling agent for improving adhesion and moisture resistance, and elimination for preventing voids It may contain a foaming agent or a liquid or powder flame retardant.

  According to the semiconductor package 1 configured as described above, since the wiring board 2 is reinforced by the first reinforcing member 4 even in a portion other than the portion joined to the semiconductor element 3, the rigidity of the entire semiconductor package 1 is increased. Increase. In particular, since the thermal expansion coefficient of the first reinforcing member 4 is smaller than that of the wiring substrate 2 (specifically, the substrate 21), the wiring is similar to the case where the semiconductor element 3 is provided over the entire surface of the wiring substrate 2. It is possible to suppress or prevent warping of the wiring board 2 due to a difference in thermal expansion coefficient between the substrate 2 and the semiconductor element 3.

(Semiconductor package manufacturing method)
The semiconductor package 1 as described above can be manufactured as follows, for example. In addition, the manufacturing method of the semiconductor package 1 is not limited to this.

(First example)
First, based on FIG. 4, the 1st example of the manufacturing method of the semiconductor package 1 is demonstrated easily.

[A1]
First, as shown in FIG. 4A, a substrate 21 is prepared.

[A2]
Next, as shown in FIG. 4B, a sheet-like member 104 for forming the first reinforcing member 4 is prepared, and the sheet-like member 104 is placed on the upper surface of the substrate 21 with an adhesive 106. Join.

  The sheet-like member 104 is a member that becomes the first reinforcing member 4 by processing described later, and is made of the same constituent material as the constituent material of the first reinforcing member 4 described above.

  The adhesive 106 includes a resin material and becomes the insulating layer 251. In a state where the adhesive 106 is applied to at least one of the sheet-like member 104 and the substrate 21, the sheet-like member 104 and the substrate 21 are bonded together via the adhesive 106. 21 is joined.

  At the time of this joining, metal bumps to be the connection portions 261 are formed on the joining surface of the sheet-like member 104 with the substrate 21, and the sheet-like member 104 and the substrate 21 are bonded together in this state, The metal bump penetrates the adhesive 106 and is connected to the heat transfer post 24. As a result, the metal bumps constitute the connection portion 261.

  Similar to the joining of the sheet-like member 104 as described above, a sheet-like member 105 for forming the second reinforcing member 5 is joined to the lower surface of the substrate 21 with an adhesive 107.

  The sheet-like member 105 is a member that becomes the second reinforcing member 5 by processing described later, and is made of the same constituent material as the constituent material of the second reinforcing member 5 described above.

  The adhesive 107 includes a resin material and becomes the insulating layer 252. In a state where the adhesive 107 is applied to at least one of the sheet-like member 105 and the substrate 21, the sheet-like member 105 and the substrate 21 are bonded together via the adhesive 107. 21 is joined.

  At the time of this joining, metal bumps to be the connection portions 262 are formed on the joining surface of the sheet-like member 105 with the substrate 21, and in this state, the sheet-like member 105 and the substrate 21 are bonded together, The metal bump penetrates the adhesive 107 and is connected to the heat transfer post 24. As a result, the metal bumps constitute the connection part 262.

[A3]
Next, by removing a part of the sheet-like member 104, the first reinforcing member 4 is formed as shown in FIG. Similarly, the second reinforcing member 5 is formed by removing a part of the sheet-like member 105.

  A method for removing a part of the sheet-like members 104 and 105 (that is, a method for forming the through hole 42, the opening 51, etc.) is not particularly limited, but for example, a method of removing by laser irradiation or etching. The method of removing etc. are mentioned. These methods are excellent in processing accuracy. Therefore, even when the metal bumps 71 and 400 are arranged at a narrow pitch, the contact between the metal bump 400 and the first reinforcing member 4 and the contact between the metal bump 71 and the second reinforcing member 5 can be prevented. .

As the laser, for example, a CO ₂ laser, a UV-YAG laser, or the like can be used.

  The etching may be dry etching or wet etching, but is preferably wet etching. Thereby, the 1st reinforcement member 4 and the 2nd reinforcement member 5 can be formed, preventing the damage of the board | substrate 21. FIG.

  Further, when removing part of the sheet-like members 104 and 105, it is preferable to determine the removal position based on the alignment marks provided on the sheet-like members 104 and 105 or the substrate 21.

[A4]
Next, as shown in FIG. 4 (d), after applying an underfill material to the upper surface of the wiring substrate 2, the semiconductor element 3 is bonded via the metal bumps 31 by solder reflow. In this case, a resin having flux activity similar to that of the insulating material 81 described above is used as the underfill material. Further, after mounting the semiconductor element 3 and bonding the semiconductor element 3 to the wiring board 2 by reflow using a flux or solder paste, a normal capillary underfill material is placed between the wiring board 2 and the semiconductor element 3. It can also be filled and cured.

  Further, as shown in FIG. 4D, metal bumps 71 are soldered to the lower surface of the wiring board 2 by solder reflow and an insulating material 81 is formed.

  Such solder bonding is not particularly limited, but can be performed by placing each metal bump 71 in contact with the lower surface of the wiring board 2 and heating in that state, for example, 200 to 280 ° C. for 10 to 60 seconds. .

  In addition, the insulating material 81 is formed by, for example, applying a thermosetting insulating material to the lower surface of the wiring substrate 2 and curing the insulating material by heating after soldering as described above. 81 is obtained.

The insulating material 81 thus obtained is formed so as to surround the periphery of the metal bump 71 as described above.
The semiconductor package 1 is obtained as described above.

  According to the manufacturing method of the semiconductor package 1 according to the first example as described above, each through hole 42 of the first reinforcing member 4 is formed by etching or laser, so that each through hole 42 can be formed with high accuracy. it can. Therefore, even if it is a case where the several through-hole 42 is provided by the pinching pitch, each through-hole 42 can be formed in a desired position and magnitude | size, and the outstanding reliability can be brought about.

  Similarly, since each opening 51 of the second reinforcing member 5 is formed by etching or laser, excellent reliability can be brought about in this respect as well.

  In particular, since there is a step of joining the sheet-like member 104 to the substrate 21 before the step of forming the first reinforcing member 4, the plurality of through holes 42 are formed with high accuracy without shifting from the plurality of terminals 221 b. can do.

  Further, by joining the sheet-like member 104 and the substrate 21 with the connecting portion 261 interposed between the heat-transfer post 24 and the sheet-like member 104, the heat-transfer post 24 and the sheet-like member 104 are joined together. Since it connects via the connection part 261, the heat-transfer post | mailbox 24 and the sheet-like member 104 can be connected via the connection part 261 simply and reliably. Similarly, the heat transfer post 24 and the sheet-like member 105 can be easily and reliably connected via the connection portion 262.

  As a result, in the obtained semiconductor package 1, the heat transfer post 24 and the first reinforcement member 4 are securely connected via the connection portion 261, and the heat transfer post 24 and the second reinforcement member 5 are connected to the connection portion 262. It is securely connected through the cable and has excellent reliability.

(Second example)
Next, a second example of the method for manufacturing the semiconductor package 1 will be briefly described with reference to FIG. Note that description of matters similar to those in the first example described above is omitted.

[B1]
First, as shown in FIG. 5A, a substrate 21 is prepared.

[B2]
Next, as shown in FIG. 5B, the first reinforcing member 4 and the auxiliary member 108 are joined to the upper surface of the substrate 21 with an adhesive 106.

  The auxiliary member 108 is provided on the inner side of the first reinforcing member 4, and is for improving the handleability of the first reinforcing member 4 when the first reinforcing member 4 is joined to the upper surface of the substrate 21. For example, the first reinforcing member 4 and the auxiliary member 108 are supported on the carrier film and transferred from the carrier film side to the substrate 21 side, thereby preventing the first reinforcing member 4 from being unintentionally deformed and the first reinforcing member 4 being supported. The member 4 can be stuck on the substrate 21.

  Such first reinforcing member 4 and auxiliary member 108 can be formed, for example, by punching a sheet-like member similar to the sheet-like member 104 in the first example described above before joining the substrate 21. it can.

  Further, in the second example, the first reinforcing member 4 and the first reinforcing member 4 and the substrate 21 with the adhesive 106 applied to at least one of the first reinforcing member 4 and the auxiliary member 108 and the substrate 21. By bonding the auxiliary member 108 and the substrate 21 together, the first reinforcing member 4 and the auxiliary member 108 and the substrate 21 are joined.

  Further, the first reinforcing member 4 is preferably provided with a plurality of alignment marks for positioning with respect to the substrate 21 during the joining. Thereby, for example, the plurality of through holes 42 of the first reinforcing member 4 and the plurality of terminals 221b of the conductor pattern 221 can be aligned.

  Such an alignment mark is not particularly limited, and may be constituted by a groove, a through hole, a protrusion, or the like formed in the first reinforcing member 4. A part of the plurality of through holes 42 can also be used as an alignment mark.

  Similar to the bonding of the first reinforcing member 4, the second reinforcing member 5 is bonded to the lower surface of the substrate 21 with an adhesive 107.

  Such a second reinforcing member 5 is formed, for example, by punching, laser processing or etching before joining a sheet-like member similar to the sheet-like member 105 in the first example described above to the substrate 21. can do.

  In the second example, the second reinforcing member 5 and the substrate 21 are bonded via the adhesive 107 with the adhesive 107 applied to at least one of the second reinforcing member 5 and the substrate 21. By matching, the second reinforcing member 5 and the substrate 21 are joined.

[B3]
Next, the auxiliary member 108 is removed. Thereby, as shown in FIG.5 (c), the inside of the 1st reinforcement member 4 will be in the exposed state.

  The auxiliary member 108 can be removed by using, for example, an adsorption force or an adhesive force.

[B4]
Next, as shown in FIG. 5 (d), after applying an underfill material to the upper surface of the wiring substrate 2, the semiconductor element 3 is bonded via the metal bumps 31 by solder reflow. Further, after mounting the semiconductor element 3 and bonding the semiconductor element 3 to the wiring board 2 by reflow using a flux or solder paste, a normal capillary underfill material is placed between the wiring board 2 and the semiconductor element 3. It can also be filled and cured. Next, metal bumps 71 are soldered to the lower surface of the wiring board 2 by solder reflow, and an insulating material 81 is formed.
The semiconductor package 1 can be obtained as described above.

  According to the manufacturing method of the semiconductor package 1 of the second example, since the first reinforcing member 4 is joined to the substrate 21 after the step of forming the first reinforcing member 4, the first reinforcing member Since various processing methods can be used without being affected by the substrate 21 when forming 4, the first reinforcing member 4 can be easily formed.

Further, by joining the first reinforcing member 4 and the substrate 21 with the connecting portion 261 interposed between the heat transfer post 24 and the first reinforcing member 4, the heat transfer post 24 and the first reinforcing member are joined. 4 is connected via the connecting portion 261, the heat transfer post 24 and the first reinforcing member 4 can be connected via the connecting portion 261 easily and reliably. Similarly, the heat transfer post 24 and the second reinforcing member 5 can be connected via the connection portion 262 easily and reliably.
As a result, the obtained semiconductor package 1 has excellent reliability.

Second Embodiment
Next, a second embodiment of the present invention will be described.

  FIG. 6 is a cross-sectional view schematically showing a semiconductor package according to the second embodiment of the present invention. In the following description, for convenience of description, the upper side in FIG. 6 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIG. 6, for convenience of explanation, each part of the semiconductor package is exaggerated.

  Hereinafter, the semiconductor package of the second embodiment will be described with a focus on differences from the above-described embodiments, and description of similar matters will be omitted. In FIG. 6, the same reference numerals are given to the same configurations as those in the above-described embodiment.

  The semiconductor package of the second embodiment is substantially the same as that of the first embodiment except that the configurations of the reinforcing member (first and second reinforcing members) and the heat transfer post (heat transfer part) are different.

  As shown in FIG. 6, the semiconductor package 1A includes a wiring board 2A on which the semiconductor element 3 is mounted, and a first reinforcing member 4A and a second reinforcing member 5A that reinforce the wiring board 2A.

  The wiring substrate 2A has a plurality of heat transfer posts 24A formed so as to penetrate the substrate 21 and the insulating layers 251 and 252 in the thickness direction.

  Each of the plurality of heat transfer posts 24 </ b> A has an upper end exposed from the upper surface of the insulating layer 251 and a lower end exposed from the lower surface of the insulating layer 252.

  4 A of 1st reinforcement members are provided with the hole 43 penetrated in the thickness direction in the site | part corresponding to the formation site | part of the heat transfer post 24A mentioned above. A connecting portion 261A (first connecting portion) is provided in the hole 43. The thermal connection between the first reinforcing member 4A and the heat transfer post 24A is easily and reliably made through the connection portion 261A.

  Similarly, the second reinforcing member 5A is provided with a hole 54 penetrating in the thickness direction at a portion corresponding to the formation portion of the heat transfer post 24A. A connecting portion 262A (second connecting portion) is provided in the hole 54. The thermal connection between the second reinforcing member 5A and the heat transfer post 24A is easily and reliably made through the connection portion 262A.

  As the constituent materials of the connection portions 261A and 262A, the same materials as those of the connection portions 261 and 262 of the first embodiment described above can be used, respectively.

  Further, the connecting portion 261A can be easily and reliably formed by filling the hole 43 of the first reinforcing member 4 with such a constituent material after the first reinforcing member 4 is joined to the substrate 21. Similarly, the connecting portion 262A can be formed easily and reliably by filling the hole 54 of the second reinforcing member 5 with the constituent material after the second reinforcing member 5 is joined to the substrate 21.

  Also with the semiconductor package 1A of the second embodiment as described above, it is possible to prevent the occurrence of problems due to heat.

<Third Embodiment>
Next, a third embodiment of the present invention will be described.

  FIG. 7 is a top view showing a semiconductor package according to the third embodiment of the present invention. In the following description, for convenience of explanation, the front side of the sheet in FIG. 7 is referred to as “up” and the back side of the sheet is referred to as “down”. Further, in FIG. 7, for convenience of explanation, each part of the semiconductor package is exaggerated.

  Hereinafter, the semiconductor package of the third embodiment will be described focusing on the differences from the above-described embodiment, and the description of the same matters will be omitted. In FIG. 7, the same reference numerals are given to the same configurations as those in the above-described embodiment.

  The semiconductor package of the third embodiment is substantially the same as that of the first embodiment except that the configuration of the first reinforcing member is different.

  As shown in FIG. 7, in the semiconductor package 1 </ b> B, the first reinforcing member 4 </ b> B is bonded to the upper surface of the wiring board 2.

  The first reinforcing member 4B is composed of two L-shaped members 4a. By combining the two L-shaped members 4 a as described above, the first reinforcing member 4 </ b> B has a shape surrounding the semiconductor element 3.

  Such a 1st reinforcement member 4B can adjust the position of the through-hole 42 with respect to the wiring board 2 by adjusting the distance between the two members 4a. Thereby, it is possible to cope with semiconductor packages having different sizes with one type of first reinforcing member 4B, or to finely adjust the position of the through hole 42 with respect to the wiring board 2.

  Also with the semiconductor package 1B of the third embodiment as described above, it is possible to prevent the occurrence of problems due to heat.

<Fourth embodiment>
Next, a fourth embodiment of the present invention will be described.

  FIG. 8 is a top view showing a semiconductor package according to the fourth embodiment of the present invention. In the following description, for the sake of convenience of explanation, the front side of the paper in FIG. 8 is referred to as “up” and the back side of the paper is referred to as “down”. In FIG. 8, for convenience of explanation, each part of the semiconductor package is exaggerated.

  Hereinafter, the semiconductor package of the fourth embodiment will be described focusing on differences from the above-described embodiment, and description of similar matters will be omitted. In FIG. 8, the same reference numerals are given to the same configurations as those in the above-described embodiment.

  The semiconductor package of the fourth embodiment is substantially the same as that of the first embodiment except that the configuration of the first reinforcing member is different.

  As shown in FIG. 8, in the semiconductor package 1 </ b> C, the first reinforcing member 4 </ b> C is bonded to the upper surface of the wiring board 2.

  The first reinforcing member 4C includes four I-shaped members 4b (band shape extending in one direction). By combining such four members 4b, the first reinforcing member 4C has a shape surrounding the semiconductor element 3.

  Such a first reinforcing member 4C can adjust the position of the through hole 42 with respect to the wiring board 2 by adjusting the distance between the two members 4b. Thereby, it is possible to cope with semiconductor packages having different sizes with one type of first reinforcing member 4C, or to finely adjust the position of the through hole 42 with respect to the wiring board 2.

  Also with the semiconductor package 1C of the third embodiment as described above, it is possible to prevent the occurrence of malfunction due to heat.

(Semiconductor device)
Next, a semiconductor device using the semiconductor package obtained as described above will be described.

  FIG. 9 is a cross-sectional view schematically showing an example of a semiconductor device using a semiconductor package obtained by the manufacturing method of the present invention.

  As shown in FIG. 9, the semiconductor device 100 includes a mother board (substrate) 200, a semiconductor package 1 mounted on the mother board 200, and a semiconductor package 300 mounted on the semiconductor package 1.

  Here, the semiconductor package 1 and the semiconductor package 300 have a POP (Package On Package) structure in which the semiconductor package 1 (first package) is a bottom package and the semiconductor package 300 is a top package (second package).

  The top package (second package) 300 includes a wiring substrate 301 and a semiconductor element 305, and a sealing portion 307 that covers the semiconductor element 305 is provided on the surface of the wiring substrate 301 on the semiconductor element 305 side. . Note that the configuration of the illustrated semiconductor package 300 is an example, and the present invention is not limited to this.

[Wiring board]
The wiring board 301 is a board (second wiring board) that supports the semiconductor element 305. For example, the wiring board 301 is a relay board (interposer) that relays electrical connection between the mounted semiconductor element 305 and the semiconductor package 1 described above. . In addition, the wiring board 301 has a shape in plan view generally a quadrangle such as a square or a rectangle.

  The wiring substrate 301 has a substrate 302. The substrate 302 is composed of an insulating material, and is composed of, for example, a base material (fiber base material) and a resin composition impregnated in the base material. As this base material and resin composition, the same thing as the insulating layer of the wiring board 2 of the semiconductor package 1 mentioned above can be used. In the illustrated example, the substrate 302 is formed of a single insulating layer, but may be formed of a plurality of insulating layers.

  A conductor pattern 308 is provided on the lower surface of the substrate 302. On the upper surface of the substrate 302, although not shown, a conductor pattern that is electrically connected to the conductor pattern 308 through a conductor post that penetrates the substrate 302 and electrically connected to the semiconductor element 305 is provided. It has been.

  These conductor patterns and conductor posts can be configured similarly to the conductor patterns and conductor posts of the wiring board 2 described above.

An insulating layer 304 is provided on the lower surface of the substrate 302 so as to cover the conductor pattern 308. Similarly, an insulating layer 303 is provided on the top surface of the substrate 302. The insulating layers 303 and 304 can be formed by, for example, a known solder resist.
A semiconductor element 305 is bonded on the upper surface of the wiring substrate 301.

[Semiconductor element]
The semiconductor element (second semiconductor element) 305 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light emitting / receiving element. The configuration and function of the semiconductor element 305 may be the same as or different from the configuration and function of the semiconductor element 3 described above.

  The semiconductor element 305 is electrically connected via a plurality of metal wires 306 to a conductor pattern (not shown) provided on the upper surface side of the wiring substrate 301 described above.

  Each metal wire 306 is formed by, for example, a known wire bonding technique. Note that this electrical connection may be performed by face-down bonding in the same manner as the semiconductor package 1 described above, instead of the metal wire.

  Such a semiconductor element 305 is sealed by a sealing portion 307.

  Since the sealing portion 307 is provided on the upper surface of the wiring substrate 301 so as to cover the semiconductor element 305, the rigidity of the semiconductor package 300 can be increased. Therefore, warpage of the semiconductor package 300 can be prevented or suppressed.

  Although it does not specifically limit as a constituent material of this sealing part 307, A well-known sealing resin can be used.

  The lower surface of the wiring substrate 301 of the semiconductor package 300 is not in contact with (separated from) the semiconductor element 3 of the semiconductor package 1 described above. In the present embodiment, the entire upper surface of the semiconductor element 3 is separated from the lower surface of the wiring substrate 301. Thereby, air can be ventilated through the gap S1 formed between the semiconductor element 3 and the wiring board 301, and the heat of the semiconductor element 3 can be efficiently released outward.

  Such a conductor pattern 308 of the semiconductor package 300 is bonded to the plurality of terminals 221b of the conductor pattern 221 of the semiconductor package 1 through the metal bumps 400.

  The metal bumps 400 are used for electrical connection between the semiconductor package 300 and the semiconductor package 1 (more specifically, electrical connection between the wiring board 2 and the wiring board 301). Each metal bump 400 also has a function of performing mechanical connection (fixation) between the wiring board 2 and the wiring board 301.

  The plurality of metal bumps 400 are arranged along the outer peripheral portion of the wiring board 2 at intervals.

  In the present embodiment, each metal bump 400 has a substantially spherical shape. The shape of each metal bump 400 is not limited to this. In addition, the size (diameter) of each metal bump 400 is set to such an extent that the semiconductor element 3 and the wiring board 301 are not in contact with each other as will be described later.

  Further, the constituent material of the metal bump 400 is not particularly limited. For example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, Various brazing materials (solder) such as tin-copper and tin-silver-copper can be used.

  In the present embodiment, each through hole 42 is provided in one-to-one correspondence with each metal bump 400. Each through hole 42 is formed so as to surround each metal bump 400 without contacting each metal bump 400. By arranging the metal bumps 400 in the through holes 42 in this way, the wiring board 2 and the wiring board 301 can be joined via the plurality of metal bumps 400 while the first reinforcing member 4 is seen in a plan view. The area can be increased.

  As shown in FIG. 9, an insulating material 401 is provided between the first reinforcing member 4 and each metal bump 400 (between the wall surface of the through hole 42 and the metal bump 400). Thereby, even if it is a case where the 1st reinforcement member 4 has electroconductivity, the short circuit between metal bumps 400 can be prevented. By filling the insulating material 401 between the first reinforcing member 4 and each metal bump 400, the integrity of the first reinforcing member 4 and each metal bump 400 is increased, and the first reinforcing member 4 and each metal bump 400 are increased. The thermal conductivity between 400 can be increased.

  Further, the insulating material 401 has a shape surrounding the periphery (lower part) of the metal bump 400 on the substrate 21 side, and is joined to each metal bump 400. Thereby, the insulating material 401 reinforces the metal bump 400.

  The insulating material 401 preferably has higher thermal conductivity than the substrate 21 of the wiring board 2 described above. Thereby, the thermal conductivity between the metal bump 400 and the first reinforcing member 4 is excellent, and the heat dissipation of the semiconductor package 1 can be improved.

  Such an insulating material 401 has an insulating property and includes a resin material, and is not particularly limited. However, like the insulating material 81 described above, the insulating material 401 is formed of, for example, a thermosetting solder bonding resin. Is preferred.

  Further, the distance between the first reinforcing member 4 and each metal bump 400 (the distance between the wall surface of the through hole 42 and the outer peripheral surface of the metal bump 400 in plan view) extends over the entire circumference of the metal bump 400. It is formed to be constant. Thereby, the integrity of the 1st reinforcement member 4 and each metal bump 400 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.

  In such a semiconductor device 100, the metal bumps 71 of the semiconductor package 1 are joined to the terminals 201 of the mother board 200. As a result, the semiconductor package 1 and the mother board 200 are electrically connected, and electrical signals are transmitted between them. In addition, the heat of the semiconductor package 1 can be released to the mother board 200 through this joint.

  According to the semiconductor device 100 as described above, since the semiconductor package 1 having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.

  As mentioned above, although the manufacturing method of the semiconductor package of this invention was demonstrated based on embodiment of illustration, this invention is not limited to these.

  For example, in the above-described embodiment, the first reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3. However, the present invention is not limited to this. A cut-out portion (notch) may be formed.

  Further, the second reinforcing member 5 may be omitted depending on the rigidity of the first reinforcing member 4 and the thickness of the wiring board 2.

  In the above-described embodiment, the heat transfer post 24 penetrating the substrate 21 is used as the heat conducting portion for connecting the first reinforcing member 4 and the second reinforcing member 5. Alternatively, a heat conductive member (metal member) may be used. In this case, the heat conducting member may be bonded (bonded) to the substrate 21, the first reinforcing member 4, and the second reinforcing member 5 using a heat transfer adhesive, or the substrate 21, the first reinforcing member may be bonded from the side surface side of the substrate 21. The reinforcing member 4 and the second reinforcing member 5 may be held from above and below.

  Further, the opening formed in the first reinforcing member 4 may not correspond to each metal bump 400 on a one-to-one basis. That is, an opening may be formed in the first reinforcing member 4 so that one corresponds to the plurality of metal bumps 400.

  Moreover, the opening part formed in the 2nd reinforcement member 5 does not need to respond | correspond one-to-one with each metal bump 71. FIG. That is, an opening may be formed in the second reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.

DESCRIPTION OF SYMBOLS 1 Semiconductor package 1A Semiconductor package 1B Semiconductor package 1C Semiconductor package 2 Wiring board 2A Wiring board 3 Semiconductor element 4 1st reinforcement member 4A 1st reinforcement member 4B 1st reinforcement member 4C 1st reinforcement member 4a Member 4b Member 5 2nd reinforcement member 5A Second reinforcing member 21 Substrate 24 Heat transfer post 24A Heat transfer post 31 Metal bump 32 Adhesive layer 33 Outer peripheral surface 41 Inner peripheral surface 42 Through hole 43 Hole 51 Opening 52 Part 53 Part 54 Hole 71 Metal bump 81 Insulating material 100 Semiconductor Device 104 Sheet-like member 105 Sheet-like member 106 Adhesive 107 Adhesive 108 Auxiliary member 200 Motherboard 201 Terminal 211 Insulating layer 212 Insulating layer 213 Insulating layer 221 Conductive pattern 221a Terminal 221b Terminal 222 Conductive pattern 223 Conductive pattern 224 Conductive pattern 231 Conductor Stroke 232 Conductor post 233 Conductor post 251 Insulating layer 252 Insulating layer 261 Connecting portion 261A Connecting portion 262 Connecting portion 262A Connecting portion 300 Semiconductor package 301 Wiring substrate 302 Substrate 303 Insulating layer 304 Insulating layer 305 Semiconductor element 306 Metal wire 307 Sealing portion 308 Conductor pattern 400 Metal bump 401 Insulating material S1 Gap

Claims (11)

A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. The wiring board, the semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern, and the semiconductor element on the surface of the substrate on the semiconductor element side are not bonded A method of manufacturing a semiconductor device comprising a reinforcing member bonded to a portion and having a smaller coefficient of thermal expansion than the substrate,
Preparing a sheet-like member;
Forming the reinforcing member by removing a part of the sheet-like member,
The first conductor pattern includes a plurality of terminals,
In the step of forming the reinforcing member, a plurality of through holes penetrating in the thickness direction are formed by removing portions corresponding to the plurality of terminals of the sheet-like member. Method. A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. The wiring board, the semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern, and the semiconductor element on the surface of the substrate on the semiconductor element side are not bonded A first reinforcing member bonded to a portion and having a smaller thermal expansion coefficient than the substrate; and a second reinforcing member bonded to a surface of the substrate opposite to the semiconductor element and having a smaller thermal expansion coefficient than the substrate. A method of manufacturing a semiconductor package comprising:
Preparing a sheet-like member;
Forming the first reinforcing member by removing a part of the sheet-like member,
The first conductor pattern includes a plurality of terminals,
In the step of forming the first reinforcing member, a plurality of through holes penetrating in the thickness direction are formed by removing portions corresponding to the plurality of terminals of the sheet-like member. Manufacturing method.   The manufacturing method of the semiconductor package of Claim 2 which has the process of joining the said sheet-like member to the said board | substrate before the process of forming a said 1st reinforcement member.   The method of manufacturing a semiconductor package according to claim 2, further comprising a step of bonding the first reinforcing member to the substrate after the step of forming the first reinforcing member. The substrate is provided with a heat conducting portion that penetrates in the thickness direction and has higher thermal conductivity than the substrate,
5. The method according to claim 3, wherein the thermal conductive portion and the sheet-like member or the first reinforcing member are connected simultaneously with or after the step of joining the sheet-like member or the first reinforcing member to the substrate. A method for manufacturing a semiconductor package.   The method for manufacturing a semiconductor package according to claim 5, wherein the heat conducting part and the sheet-like member or the first reinforcing member are connected via a connecting part.   The method of manufacturing a semiconductor package according to claim 6, wherein the connection portion is made of solder.   The method for manufacturing a semiconductor package according to claim 6, wherein the connection portion is made of a resin composition containing an inorganic filler and a resin material.   By joining the sheet-like member or the first reinforcing member and the substrate in a state where the connecting portion is interposed between the heat conducting portion and the sheet-like member or the first reinforcing member, The manufacturing method of the semiconductor package in any one of Claim 6 thru | or 8 which connects a heat conductive part and the said sheet-like member, or the said 1st reinforcement member via the said connection part.   A hole penetrating in the thickness direction is formed in a portion corresponding to the heat conducting portion of the first reinforcing member, and after joining the sheet-like member or the first reinforcing member to the substrate, the hole is inserted into the hole. The method of manufacturing a semiconductor package according to claim 6, wherein the connection portion is formed.   The method for manufacturing a semiconductor package according to claim 1, wherein the formation of the plurality of through holes is performed using laser or etching.

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