WO2016203927A1 - Compound semiconductor device and method for manufacturing same - Google Patents

Compound semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2016203927A1
WO2016203927A1 PCT/JP2016/065633 JP2016065633W WO2016203927A1 WO 2016203927 A1 WO2016203927 A1 WO 2016203927A1 JP 2016065633 W JP2016065633 W JP 2016065633W WO 2016203927 A1 WO2016203927 A1 WO 2016203927A1
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substrate
semiconductor
semiconductor device
opening
openings
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PCT/JP2016/065633
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French (fr)
Japanese (ja)
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渋江　人志
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ソニー株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present disclosure relates to a composite semiconductor device having a structure in which two or more semiconductor packages are stacked, and a manufacturing method thereof.
  • a composite semiconductor device includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package.
  • the first semiconductor package includes a first substrate including a wiring layer, a rigid plate including the first opening and the second opening stacked on the first substrate and penetrating in the stacking direction, A first semiconductor chip formed in a region inside the first opening on the substrate; and a solder layer formed in a region inside the second opening on the first substrate.
  • the second semiconductor package includes a second substrate including a terminal portion connected to the solder layer, and a second semiconductor chip formed on the second substrate.
  • a rigid plate including a first opening and a second opening is stacked on a first substrate. For this reason, even if the solder layer is provided at a position corresponding to the second opening on the first substrate and connected to the terminal portion of the second substrate, the warp of the first semiconductor package is reduced.
  • a method for manufacturing a composite semiconductor device includes preparing a base plate made of a rigid material, a plurality of first openings and a plurality of second at predetermined positions on the base plate. Forming a plurality of openings, and dividing a single base plate in which a plurality of first openings and a plurality of second openings are formed into a plurality of pieces, thereby forming a plurality of rigid plates Preparing a single substrate, arranging a plurality of rigid plates on the single substrate, and mounting a first semiconductor chip on the single substrate at a position corresponding to the plurality of first openings, respectively.
  • a rigid plate including a first opening and a second opening is stacked on a first substrate. Therefore, even if a solder layer is provided at a position corresponding to the second opening on the first substrate and connected to the terminal portion of the second substrate, the warp of the first semiconductor package is alleviated. Further, since the plurality of separated rigid plates are arranged on one substrate, handling becomes easy and it is advantageous for improving the yield.
  • the warp of the first semiconductor package due to the formation of the solder layer is reduced. Therefore, it is easy to maintain a good connection state between the first semiconductor package and the second semiconductor package, and a structure suitable for high integration is realized.
  • the effect of this indication is not limited to this, Any effect described below may be sufficient.
  • FIG. 3 is a cross-sectional view illustrating a step in the method for manufacturing the semiconductor device illustrated in FIGS. 1A and 1B. It is sectional drawing showing the 1 process following FIG. 2A. It is sectional drawing showing the 1 process following FIG. 2B. It is sectional drawing showing the 1 process following FIG. 2C. It is sectional drawing showing the 1 process following FIG. 2D.
  • FIG. 1 illustrates a cross-sectional configuration of a composite semiconductor device 1 (hereinafter simply referred to as a semiconductor device 1) as an embodiment of the present disclosure.
  • the semiconductor device 1 is formed by stacking a semiconductor package 10 as a lower layer structure and a semiconductor package 20 as an upper layer structure.
  • the semiconductor package 10 includes a substrate 11, a rigid plate 12 stacked on the substrate 11, a semiconductor chip 13, and a plurality of solder layers 14.
  • the substrate 11 has a base material 111 and wiring layers 112 and 113 formed on the front surface and the back surface of the base material 111, respectively.
  • the substrate 111 is made of, for example, a glass epoxy copper clad laminate.
  • the wiring layer 112 and the wiring layer 113 include a plurality of wirings L1 and wirings L2 made of a highly conductive material such as Cu (copper) or Al (aluminum). Each of the wirings L1 is connected to the solder layer 14.
  • a plurality of connection terminals C1 made of solder balls or the like are provided on the back surface of the substrate 11 so as to cover at least a part of each wiring L2.
  • the rigid plate 12 is a plate-like member made of, for example, a nonmagnetic metal such as copper, copper alloy, aluminum or aluminum alloy, other metals, ceramics or glass, which has higher rigidity than the substrate 11.
  • the rigid plate 12 is provided with an opening 15 and a plurality of openings 16 which are through-holes penetrating in the thickness direction (the stacking direction of the substrate 11 and the rigid plate 12).
  • the area of the opening 15 is larger than the area of the opening 16.
  • the plurality of openings 16 are scattered around the opening 15.
  • the openings 15 and 16 are formed using, for example, punching, cutting with a drill, etching, or laser processing.
  • the planar dimension of the opening 15 of the rigid plate 12 be slightly larger than the planar dimension of the semiconductor chip 13.
  • the semiconductor chip 13 is formed in a region inside the opening 15 on the substrate 11 by, for example, flip chip mounting. Further, the plurality of solder layers 14 are respectively formed in regions inside the plurality of openings 16 on the substrate 11. When the rigid plate 12 has conductivity, an insulating layer Z is provided between the opening 16 and the solder layer 14.
  • FIG. 1 four solder layers 14, openings 16, and wirings L ⁇ b> 1 are illustrated, but the number thereof is not limited to four.
  • the number of each of the solder layer 14, the opening 16, and the wiring L1 may be set to 3 or less, for example, or 5 or more.
  • nine connection terminals C1 and nine wirings L2 are shown, but the number thereof is also arbitrary.
  • a resin layer 17 made of a resin called an underfill agent such as an epoxy resin is filled between the semiconductor chip 13 and the substrate 11.
  • a plurality of connection terminals 13T are provided on the semiconductor chip 13 so as to penetrate the resin layer 16, and the plurality of connection terminals 13T are respectively connected to the wiring layer 112 at a plurality of connection portions 19 called bumps.
  • a protective film 18 may be provided so as to seal the entire region inside the opening 15 on the substrate 11.
  • the opening 15 of the rigid plate 12 has a function as a dam that prevents the resin layer 17 and the protective film 18 filled around the semiconductor chip 13 from flowing out during the manufacturing process.
  • the resin layer 17 is preferably in contact with the end face of the opening 15 of the rigid plate 12.
  • the semiconductor package 20 is stacked on the semiconductor package 10 and includes a substrate 21 and a semiconductor stacked chip 22 formed on the substrate 21.
  • the substrate 21 has a base material 211 and wiring layers 212 and 213 respectively formed on the front surface and the back surface of the base material 211.
  • the base material 211 consists of a glass epoxy copper clad laminated board etc., for example.
  • the wiring layer 212 and the wiring layer 213 respectively include a plurality of wirings L3 and L4 made of a highly conductive material such as Cu or Al.
  • a plurality of connection terminals 21T are provided on the surface of the substrate 21 so as to cover at least a part of each wiring L3.
  • the semiconductor multilayer chip 22 has a structure in which, for example, a semiconductor chip 221 and a semiconductor chip 222 are bonded via an adhesive layer 223.
  • Each connection terminal 221T in the semiconductor chip 221 is connected to one connection terminal 21T provided on the surface of the substrate 21 via a bonding wire W1.
  • the connection terminals 222T in the semiconductor chip 222 are connected to other connection terminals 21T provided on the surface of the substrate 21 via bonding wires W2.
  • the substrate 21 and the semiconductor multilayer chip 22 are sealed with a mold resin layer 23.
  • the rigid plate 12 having higher rigidity than the substrate 11 is provided in the semiconductor package 10. For this reason, the rigidity of the semiconductor package 10 as a whole is improved, and excellent resistance to thermal stress and mechanical stress in the manufacturing process and use environment can be exhibited.
  • the semiconductor device 1 can be manufactured as follows, for example. 2A to 2E show a part of the manufacturing method of the semiconductor device 1 in the order of steps.
  • the openings 15 and 16 are formed using, for example, punching, cutting with a drill, etching, or laser processing.
  • the insulating layer Z is formed so as to cover at least the inner surface of the opening 16.
  • the insulating layer Z can be formed by, for example, ceramic formation by spraying, electrodeposition coating of polyimide or acrylic resin, spray coating of acrylic resin, coating of fluororesin, or the like. Or after apply
  • the base plate 12Z is aluminum or an aluminum alloy, the chemically stable insulating layer Z can be easily obtained by forming an alumite coating by anodizing.
  • the single base plate 12Z in which the plurality of upper openings 15 and the plurality of openings 16 are formed is divided into a plurality of parts, for example, at positions indicated by broken lines, and a plurality of rigid plates 12 is formed (middle stage to lower stage in FIG. 2A).
  • FIG. 2A shows a case where one base plate 12Z is cut into three rigid plates 12, the number to be divided can be arbitrarily selected.
  • one substrate 11Z is prepared, and a plurality of rigid plates 12 are arranged on the one substrate 11Z.
  • the semiconductor chips 13 are each mounted on the flip chip.
  • the connection portion 19 and the connection terminal 13T of the semiconductor chip 13 are connected to each other, and the resin layer 17 is filled in the gap between the semiconductor chip 13 and the substrate 11.
  • the resin layer 17 comes into contact with the end face of the opening 15.
  • the solder layer 14 is formed by placing the solder ball on the region inside the opening 16 on the substrate 11Z and performing reflow.
  • solder ball is formed so as to cover the wiring L2, and reflow is performed to form the connection terminal C1.
  • the solder layer 14 and the connection terminal C1 may be formed at the same time.
  • the substrate 11Z is divided at positions corresponding to the outer edges of the plurality of rigid plates 12 (the positions indicated by broken lines in the upper part of FIG. 2E), thereby forming a plurality of semiconductor packages 10 (lower part of FIG. 2E). ).
  • the semiconductor package 20 is placed on the semiconductor package 10. At that time, the terminal portion C2 provided on the back surface of the substrate 21 and the solder layer 14 of the semiconductor package 10 are aligned so that they are electrically connected.
  • the semiconductor device 1 is completed.
  • the rigid plate 12 including the opening 15 and the opening 16 is laminated on the substrate 11. For this reason, even if the solder layer 14 is provided at a position corresponding to the opening 16 on the substrate 11 and soldered to the terminal portion C2 of the substrate 21, the bending (warping) generated in the semiconductor package 10 can be reduced. it can. Therefore, it becomes easy to maintain a good connection state between the semiconductor package 10 and the semiconductor package 20, and a structure suitable for high integration is realized.
  • the rigid plate 12 is formed of a metal plate such as copper, copper alloy, aluminum or aluminum alloy, excellent strength, flatness, workability, heat dissipation, and the like can be obtained.
  • the substrate 11 ⁇ / b> Z is connected to each outer edge of the plurality of rigid plates 12. Split at the corresponding position. For this reason, since the rigid plate 12 can be selectively disposed only on the non-defective product of the substrate 11Z at the stage of arrangement on the one substrate 11Z, the yield is improved. Further, since it is not necessary to match the dimensions of one base plate and one substrate, handling in the manufacturing process becomes easy.
  • the semiconductor chip 13 is mounted at a position corresponding to the opening 15. For this reason, the size of the opening 15 can be brought close to the size of the semiconductor chip 13, which is advantageous for reducing the occupied area of the semiconductor device 1.
  • the rigid plate 12 can be disposed.
  • the resin layer 17 is filled when the resin layer 17 is filled between the semiconductor chip 13 and the substrate 11. 17 spreads around the semiconductor chip 13. Since it is necessary to place the rigid plate 12 on a flat surface, a margin is given to the size of the opening 15 in that case.
  • the semiconductor chip 13 is mounted in the region inside the opening 15 of the rigid plate 12 placed in advance on the substrate 10, the spread of the resin layer 17 can be suppressed.
  • the configurations of the semiconductor packages 10 and 20 shown in the above embodiment are examples, and some components may be missing, or other components may be further provided.
  • a plurality of rigid plates 12 separated in advance are arranged on one substrate 11Z.
  • the base plate 12Z before being separated into individual pieces is arranged. After placing the substrate 11Z as it is, the substrate 11Z and the base plate 12Z may be cut together.
  • the rigid plate 12 is arranged on the substrate 10 and then the semiconductor chip 13 is mounted at a position corresponding to the opening 15. It is not limited to.
  • the rigid plate 12 may be disposed after the semiconductor chip 13 is mounted on the substrate 11Z in advance.
  • each semiconductor chip is flip-chip mounted, but the present technology is not limited to this.
  • a semiconductor chip may be mounted by wire bonding.
  • a first substrate including a wiring layer; a rigid plate including a first opening and a second opening stacked on the first substrate and penetrating in a stacking direction; and the first substrate on the first substrate.
  • a first semiconductor package having a first semiconductor chip formed in a region inside the opening, and a solder layer formed in a region inside the second opening on the first substrate;
  • a second substrate including a terminal portion stacked on the first semiconductor package and connected to the solder layer; and a second semiconductor chip formed on the second substrate.
  • a compound semiconductor device comprising a semiconductor package.
  • the rigid plate is made of a non-magnetic metal
  • the composite semiconductor device according to (1) wherein an insulating layer is provided between the second opening and the solder layer.
  • the nonmagnetic metal is copper, a copper alloy, aluminum, or an aluminum alloy.
  • the composite semiconductor device according to (1), wherein the rigid plate is made of ceramics or glass.
  • a base plate made of a rigid material Preparing a base plate made of a rigid material, and forming a plurality of first openings and a plurality of second openings at predetermined positions in the base plate; Dividing the one base plate in which the plurality of first openings and the plurality of second openings are formed into a plurality of pieces, thereby forming a plurality of rigid plates; Providing a substrate and arranging the plurality of rigid plates on the substrate; Mounting each of the first semiconductor chips on the one substrate at a position corresponding to the plurality of first openings; Forming solder layers on the one substrate at positions corresponding to the plurality of second openings, Forming the plurality of first semiconductor packages by dividing the one substrate at a position corresponding to an outer edge of each of the plurality of rigid plates; A second semiconductor package in which a second semiconductor chip is provided on a second substrate including a terminal portion is placed on the first semiconductor package, and the solder layer and the terminal portion are connected. And a method of manufacturing a composite semiconductor

Abstract

Provided is a compound semiconductor device having a structure suitable for high integration. The compound semiconductor device is provided with a first semiconductor package, and a second semiconductor package laminated on the first semiconductor package. The first semiconductor package has: a first substrate including a wiring layer; a rigid plate, which is laminated on the first substrate, and includes a first opening and a second opening, which penetrate the rigid plate in the laminating direction; a first semiconductor chip formed on the first substrate, said first semiconductor chip being in a region inside of the first opening; and a solder layer formed on the first substrate, said solder layer being in a region inside of the second opening. The second semiconductor package has: a second substrate including a terminal section connected to the solder layer; and a second semiconductor chip formed on the second substrate.

Description

複合型半導体装置およびその製造方法Composite semiconductor device and manufacturing method thereof
　本開示は、２以上の半導体パッケージが積層された構造を有する複合型半導体装置およびその製造方法に関する。 The present disclosure relates to a composite semiconductor device having a structure in which two or more semiconductor packages are stacked, and a manufacturing method thereof.
　近年のスマートフォンなどに代表される携帯型の電子機器には、複数の半導体パッケージが積層されてなるパッケージオンパッケージ（ＰＯＰ）と呼ばれる複合型半導体装置が搭載されている。このような複合型半導体装置に対しては高密度実装が求められており、これまでにもそのような課題解決のための検討がなされている（例えば特許文献１参照。） In recent years, portable electronic devices represented by smartphones and the like are equipped with a composite semiconductor device called a package-on-package (POP) in which a plurality of semiconductor packages are stacked. High density mounting is demanded for such a composite semiconductor device, and studies for solving such problems have been made (see, for example, Patent Document 1).
特開２００８－１０８８４６号公報JP 2008-10884 A
　これまでのＰＯＰ構造を有する複合型半導体装置では、下部の半導体パケージにおけるモールド樹脂により覆われた半導体チップと上部の半導体パッケージにおける半導体チップとが、スルーホールを介したはんだにより接続されていた。このため、装置全体の反りが生じることが多く、はんだ接続不良を招くおそれがあった。 In conventional composite semiconductor devices having a POP structure, the semiconductor chip covered with the mold resin in the lower semiconductor package and the semiconductor chip in the upper semiconductor package are connected by solder via a through hole. For this reason, the warpage of the entire apparatus often occurs, which may cause a solder connection failure.
　したがって、高集積化に適した構造を有する複合型半導体装置およびその製造方法を提供することが望ましい。 Therefore, it is desirable to provide a composite semiconductor device having a structure suitable for high integration and a method for manufacturing the same.
　本開示の一実施形態としての複合型半導体装置は、第１の半導体パッケージと、この第１の半導体パッケージの上に積層された第２の半導体パッケージとを備えたものである。ここで第１の半導体パッケージは、配線層を含む第１の基板と、その第１の基板に積層され、積層方向に貫く第１の開口および第２の開口を含む剛性プレートと、第１の基板上の、第１の開口の内側の領域に形成された第１の半導体チップと、第１の基板上の、第２の開口の内側の領域に形成されたはんだ層とを有する。また、第２の半導体パッケージは、はんだ層と接続された端子部を含む第２の基板と、この第２の基板上に形成された第２の半導体チップとを有する。 A composite semiconductor device according to an embodiment of the present disclosure includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. Here, the first semiconductor package includes a first substrate including a wiring layer, a rigid plate including the first opening and the second opening stacked on the first substrate and penetrating in the stacking direction, A first semiconductor chip formed in a region inside the first opening on the substrate; and a solder layer formed in a region inside the second opening on the first substrate. The second semiconductor package includes a second substrate including a terminal portion connected to the solder layer, and a second semiconductor chip formed on the second substrate.
　本開示の一実施形態としての複合型半導体装置では、第１の基板上に第１の開口および第２の開口を含む剛性プレートを積層した。このため、第１の基板上の第２の開口に対応する位置にはんだ層を設け、第２の基板の端子部と接続される構造であっても、第１の半導体パッケージの反りが緩和される。 In the composite semiconductor device as an embodiment of the present disclosure, a rigid plate including a first opening and a second opening is stacked on a first substrate. For this reason, even if the solder layer is provided at a position corresponding to the second opening on the first substrate and connected to the terminal portion of the second substrate, the warp of the first semiconductor package is reduced. The
　本開示の一実施形態としての複合型半導体装置の製造方法は、剛性材料からなる一の基材プレートを用意し、その基材プレートにおける所定の位置に複数の第１の開口および複数の第２の開口をそれぞれ形成することと、複数の第１の開口および複数の第２の開口が形成された一の基材プレートを複数に分割することにより個片化し、複数の剛性プレートを形成することと、一の基板を用意し、複数の剛性プレートを一の基板の上に配列することと、一の基板上の、複数の第１の開口と対応する位置に第１の半導体チップをそれぞれ実装することと、一の基板上の、複数の第２の開口と対応する位置にはんだ層をそれぞれ形成することと、一の基板を、複数の剛性プレートの各々の外縁と対応する位置で分割することにより、複数の第１の半導体パッケージを形成することと、第１の半導体パッケージの上に、端子部を含む第２の基板の上に第２の半導体チップを設けた第２の半導体パッケージを載置し、はんだ層と端子部とを接続することとを含む。 In one embodiment of the present disclosure, a method for manufacturing a composite semiconductor device includes preparing a base plate made of a rigid material, a plurality of first openings and a plurality of second at predetermined positions on the base plate. Forming a plurality of openings, and dividing a single base plate in which a plurality of first openings and a plurality of second openings are formed into a plurality of pieces, thereby forming a plurality of rigid plates Preparing a single substrate, arranging a plurality of rigid plates on the single substrate, and mounting a first semiconductor chip on the single substrate at a position corresponding to the plurality of first openings, respectively. Forming a solder layer at a position corresponding to the plurality of second openings on one substrate, and dividing the one substrate at a position corresponding to each outer edge of the plurality of rigid plates. A plurality of first Forming a conductor package; placing a second semiconductor package having a second semiconductor chip on a second substrate including a terminal portion on the first semiconductor package; and solder layers and terminals Connecting the parts.
　本開示の一実施形態としての複合型半導体装置の製造方法では、第１の基板上に第１の開口および第２の開口を含む剛性プレートを積層した。このため、第１の基板上の第２の開口に対応する位置にはんだ層を設け、第２の基板の端子部と接続しても、第１の半導体パッケージの反りが緩和される。また、個片化された複数の剛性プレートを一の基板の上に配列するようにしたので、ハンドリングが容易となるうえ、歩留まりの向上に有利となる。 In the method of manufacturing a composite semiconductor device as an embodiment of the present disclosure, a rigid plate including a first opening and a second opening is stacked on a first substrate. Therefore, even if a solder layer is provided at a position corresponding to the second opening on the first substrate and connected to the terminal portion of the second substrate, the warp of the first semiconductor package is alleviated. Further, since the plurality of separated rigid plates are arranged on one substrate, handling becomes easy and it is advantageous for improving the yield.
　本開示の一実施形態としての複合型半導体装置およびその製造方法によれば、はんだ層の形成に起因する第１の半導体パッケージの反りが緩和される。よって、第１の半導体パッケージと第２の半導体パッケージとの接続状態を良好に維持しやすくなり、高集積化に適した構造が実現される。なお、本開示の効果はこれに限定されるものではなく、以下に記載のいずれの効果であってもよい。 According to the composite semiconductor device and the manufacturing method thereof as one embodiment of the present disclosure, the warp of the first semiconductor package due to the formation of the solder layer is reduced. Therefore, it is easy to maintain a good connection state between the first semiconductor package and the second semiconductor package, and a structure suitable for high integration is realized. In addition, the effect of this indication is not limited to this, Any effect described below may be sufficient.
本開示の一実施の形態に係る複合型半導体装置の一構成例を表す断面図である。It is sectional drawing showing the example of 1 structure of the composite type semiconductor device which concerns on one embodiment of this indication. 図１Ａ，１Ｂに示した半導体装置の製造方法における一工程を表す断面図である。FIG. 3 is a cross-sectional view illustrating a step in the method for manufacturing the semiconductor device illustrated in FIGS. 1A and 1B. 図２Ａに続く一工程を表す断面図である。It is sectional drawing showing the 1 process following FIG. 2A. 図２Ｂに続く一工程を表す断面図である。It is sectional drawing showing the 1 process following FIG. 2B. 図２Ｃに続く一工程を表す断面図である。It is sectional drawing showing the 1 process following FIG. 2C. 図２Ｄに続く一工程を表す断面図である。It is sectional drawing showing the 1 process following FIG. 2D.
　以下、本開示の実施の形態について図面を参照して詳細に説明する。なお、説明は以下の順序で行う。
１．一実施の形態（基本構造を有する複合型半導体装置およびその製造方法）
２．変形例 Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.
1. One Embodiment (Composite Semiconductor Device Having Basic Structure and Manufacturing Method Thereof)
2. Modified example
＜実施の形態＞
［複合型半導体装置１の構成］
　図１は、本開示の一実施の形態としての複合型半導体装置１（以下、単に半導体装置１という。）の断面構成を表したものである。 <Embodiment>
[Configuration of Composite Semiconductor Device 1]
FIG. 1 illustrates a cross-sectional configuration of a composite semiconductor device 1 (hereinafter simply referred to as a semiconductor device 1) as an embodiment of the present disclosure.
　半導体装置１は、下層構造としての半導体パッケージ１０と、上層構造としての半導体パッケージ２０とが積層されたものである。 The semiconductor device 1 is formed by stacking a semiconductor package 10 as a lower layer structure and a semiconductor package 20 as an upper layer structure.
（半導体パッケージ１０）
　半導体パッケージ１０は、基板１１と、この基板１１の上に積層された剛性プレート１２と、半導体チップ１３と、複数のはんだ層１４とを有する。 (Semiconductor package 10)
The semiconductor package 10 includes a substrate 11, a rigid plate 12 stacked on the substrate 11, a semiconductor chip 13, and a plurality of solder layers 14.
　基板１１は、基材１１１と、その基材１１１の表面および裏面にそれぞれ形成された配線層１１２，１１３とを有している。基材１１１は、例えばガラスエポキシ銅張積層板などからなる。配線層１１２および配線層１１３は、例えばＣｕ（銅）やＡｌ（アルミニウム）などの高導電性材料からなる配線Ｌ１および配線Ｌ２をそれぞれ複数含んでいる。配線Ｌ１の各々は、はんだ層１４と接続されている。また、基板１１の裏面には、各配線Ｌ２の少なくとも一部をそれぞれ覆うように、はんだボールなどからなる接続端子Ｃ１が複数設けられている。 The substrate 11 has a base material 111 and wiring layers 112 and 113 formed on the front surface and the back surface of the base material 111, respectively. The substrate 111 is made of, for example, a glass epoxy copper clad laminate. The wiring layer 112 and the wiring layer 113 include a plurality of wirings L1 and wirings L2 made of a highly conductive material such as Cu (copper) or Al (aluminum). Each of the wirings L1 is connected to the solder layer 14. In addition, a plurality of connection terminals C1 made of solder balls or the like are provided on the back surface of the substrate 11 so as to cover at least a part of each wiring L2.
　剛性プレート１２は、例えば基板１１よりも高い剛性を有し、例えば銅、銅合金、アルミニウムもしくはアルミニウム合金などの非磁性金属やその他の金属、セラミックスまたはガラスからなる板状部材である。剛性プレート１２には、その厚さ方向（基板１１と剛性プレート１２との積層方向）に貫く貫通孔である開口１５および複数の開口１６が設けられている。例えば開口１５の面積は、開口１６の面積よりも大きい。複数の開口１６は、開口１５の周囲に点在している。開口１５，１６は、例えば、パンチング加工、ドリルによる切削加工、エッチング加工またはレーザ加工などを用いて形成されたものである。なお、半導体パッケージ１０の小型化を実現するため、剛性プレート１２の開口１５の平面寸法は、半導体チップ１３の平面寸法よりも僅かに大きい程度とすることが望ましい。 The rigid plate 12 is a plate-like member made of, for example, a nonmagnetic metal such as copper, copper alloy, aluminum or aluminum alloy, other metals, ceramics or glass, which has higher rigidity than the substrate 11. The rigid plate 12 is provided with an opening 15 and a plurality of openings 16 which are through-holes penetrating in the thickness direction (the stacking direction of the substrate 11 and the rigid plate 12). For example, the area of the opening 15 is larger than the area of the opening 16. The plurality of openings 16 are scattered around the opening 15. The openings 15 and 16 are formed using, for example, punching, cutting with a drill, etching, or laser processing. In order to reduce the size of the semiconductor package 10, it is desirable that the planar dimension of the opening 15 of the rigid plate 12 be slightly larger than the planar dimension of the semiconductor chip 13.
　半導体チップ１３は、基板１１上の、開口１５の内側の領域に例えばフリップチップ（Flip Chip）実装により形成されている。また、複数のはんだ層１４は、それぞれ、基板１１上の、複数の開口１６の内側の領域に形成されている。剛性プレート１２が導電性を有する場合には、開口１６とはんだ層１４との間に絶縁層Ｚが設けられている。なお、図１では、はんだ層１４、開口１６および配線Ｌ１を４つずつ記載したが、それらの数は４つに限定されるものではない。はんだ層１４、開口１６および配線Ｌ１の各々の数を例えば３以下としてもよいし、５以上としてもよい。同様に、図１では、接続端子Ｃ１および配線Ｌ２を９つずつ記載したが、それらの数も任意である。 The semiconductor chip 13 is formed in a region inside the opening 15 on the substrate 11 by, for example, flip chip mounting. Further, the plurality of solder layers 14 are respectively formed in regions inside the plurality of openings 16 on the substrate 11. When the rigid plate 12 has conductivity, an insulating layer Z is provided between the opening 16 and the solder layer 14. In FIG. 1, four solder layers 14, openings 16, and wirings L <b> 1 are illustrated, but the number thereof is not limited to four. The number of each of the solder layer 14, the opening 16, and the wiring L1 may be set to 3 or less, for example, or 5 or more. Similarly, in FIG. 1, nine connection terminals C1 and nine wirings L2 are shown, but the number thereof is also arbitrary.
　半導体チップ１３と基板１１との間には、エポキシ樹脂などのアンダーフィル剤と呼ばれる樹脂からなる樹脂層１７が充填されている。また、半導体チップ１３には、複数の接続端子１３Ｔが樹脂層１６を貫くように設けられており、複数の接続端子１３Ｔがバンプと呼ばれる複数の接続部１９においてそれぞれ配線層１１２と接続されている。さらに、基板１１上の、開口１５の内側の領域全体を封止するように、保護膜１８が設けられていてもよい。なお、剛性プレート１２の開口１５は、製造過程において半導体チップ１３の周囲に充填される樹脂層１７および保護膜１８の流出を防ぐダムとしての機能を有している。ここで、樹脂層１７は、剛性プレート１２の開口１５の端面と接することが望ましい。 A resin layer 17 made of a resin called an underfill agent such as an epoxy resin is filled between the semiconductor chip 13 and the substrate 11. In addition, a plurality of connection terminals 13T are provided on the semiconductor chip 13 so as to penetrate the resin layer 16, and the plurality of connection terminals 13T are respectively connected to the wiring layer 112 at a plurality of connection portions 19 called bumps. . Furthermore, a protective film 18 may be provided so as to seal the entire region inside the opening 15 on the substrate 11. The opening 15 of the rigid plate 12 has a function as a dam that prevents the resin layer 17 and the protective film 18 filled around the semiconductor chip 13 from flowing out during the manufacturing process. Here, the resin layer 17 is preferably in contact with the end face of the opening 15 of the rigid plate 12.
（半導体パッケージ２０）
　半導体パッケージ２０は、半導体パッケージ１０の上に積層され、基板２１と、この基板２１上に形成された半導体積層チップ２２とを有する。 (Semiconductor package 20)
The semiconductor package 20 is stacked on the semiconductor package 10 and includes a substrate 21 and a semiconductor stacked chip 22 formed on the substrate 21.
　基板２１は、基材２１１と、その基材２１１の表面および裏面にそれぞれ形成された配線層２１２，２１３とを有している。基材２１１は、例えばガラスエポキシ銅張積層板などからなる。配線層２１２および配線層２１３は、配線層１１２および配線層１１３と同様、例えばＣｕやＡｌなどの高導電性材料からなる配線Ｌ３および配線Ｌ４をそれぞれ複数含んでいる。基板２１の表面には、各配線Ｌ３の少なくとも一部をそれぞれ覆うように接続端子２１Ｔが複数設けられている。 The substrate 21 has a base material 211 and wiring layers 212 and 213 respectively formed on the front surface and the back surface of the base material 211. The base material 211 consists of a glass epoxy copper clad laminated board etc., for example. Similar to the wiring layer 112 and the wiring layer 113, the wiring layer 212 and the wiring layer 213 respectively include a plurality of wirings L3 and L4 made of a highly conductive material such as Cu or Al. A plurality of connection terminals 21T are provided on the surface of the substrate 21 so as to cover at least a part of each wiring L3.
　半導体積層チップ２２は、例えば半導体チップ２２１と半導体チップ２２２とが接着層２２３を介して接合された構造を有する。半導体チップ２２１における接続端子２２１Ｔは、それぞれボンディングワイヤＷ１を介して、基板２１の表面に設けられた一の接続端子２１Ｔと接続されている。半導体チップ２２２における接続端子２２２Ｔは、それぞれボンディングワイヤＷ２を介して、基板２１の表面に設けられた他の接続端子２１Ｔと接続されている。基板２１および半導体積層チップ２２は、モールド樹脂層２３により封止されている。 The semiconductor multilayer chip 22 has a structure in which, for example, a semiconductor chip 221 and a semiconductor chip 222 are bonded via an adhesive layer 223. Each connection terminal 221T in the semiconductor chip 221 is connected to one connection terminal 21T provided on the surface of the substrate 21 via a bonding wire W1. The connection terminals 222T in the semiconductor chip 222 are connected to other connection terminals 21T provided on the surface of the substrate 21 via bonding wires W2. The substrate 21 and the semiconductor multilayer chip 22 are sealed with a mold resin layer 23.
　このように、半導体装置１では、半導体パッケージ１０において、基板１１よりも高い剛性を有する剛性プレート１２を設けるようにした。このため、半導体パッケージ１０全体としての剛性が向上し、製造過程や使用環境下での熱応力や機械的応力に対する優れた耐性を示すことができる。 Thus, in the semiconductor device 1, the rigid plate 12 having higher rigidity than the substrate 11 is provided in the semiconductor package 10. For this reason, the rigidity of the semiconductor package 10 as a whole is improved, and excellent resistance to thermal stress and mechanical stress in the manufacturing process and use environment can be exhibited.
［半導体装置１の製造方法］
　この半導体装置１は、例えば次のようにして製造することができる。図２Ａ～図２Ｅは、半導体装置１の製造方法の一部を工程順に表したものである。 [Method of Manufacturing Semiconductor Device 1]
The semiconductor device 1 can be manufactured as follows, for example. 2A to 2E show a part of the manufacturing method of the semiconductor device 1 in the order of steps.
　まず、のちに剛性プレート１２となる、剛性材料からなる一の基材プレート１２Ｚを用意し、前記基材プレートにおける所定の位置に複数の開口１５および複数の開口１６をそれぞれ形成する（図２Ａ上段）。開口１５，１６は、例えば、パンチング加工、ドリルによる切削加工、エッチング加工またはレーザ加工などを用いて形成する。 First, one base plate 12Z made of a rigid material, which will later become the rigid plate 12, is prepared, and a plurality of openings 15 and a plurality of openings 16 are respectively formed at predetermined positions on the base plate (FIG. 2A upper stage). ). The openings 15 and 16 are formed using, for example, punching, cutting with a drill, etching, or laser processing.
　次に、図２Ａ中段に示したように、基材プレート１２Ｚが導電性を有する場合には、少なくとも開口１６の内面を覆うように絶縁層Ｚを形成する。絶縁層Ｚの形成は、例えば、溶射法によるセラミックの形成、ポリイミドやアクリル樹脂の電着塗装、アクリル樹脂のスプレー塗布、フッ素樹脂の塗布などにより行うことができる。あるいは、ソルダーレジストを塗布したのち、選択的露光、現像および加熱などの処理を行うことで開口１６の内面のみを覆うように絶縁層Ｚを形成してもよい。また、基材プレート１２Ｚがアルミニウムまたはアルミニウム合金であれば、アルマイト処理によるアルマイト被膜の形成により、化学的に安定した絶縁層Ｚを容易に得ることができる。 Next, as shown in the middle part of FIG. 2A, when the base plate 12Z has conductivity, the insulating layer Z is formed so as to cover at least the inner surface of the opening 16. The insulating layer Z can be formed by, for example, ceramic formation by spraying, electrodeposition coating of polyimide or acrylic resin, spray coating of acrylic resin, coating of fluororesin, or the like. Or after apply | coating a soldering resist, you may form the insulating layer Z so that only the inner surface of the opening 16 may be covered by performing processes, such as selective exposure, image development, and a heating. Moreover, if the base plate 12Z is aluminum or an aluminum alloy, the chemically stable insulating layer Z can be easily obtained by forming an alumite coating by anodizing.
　絶縁層Ｚの形成ののち、上段複数の開口１５および複数の開口１６が形成された一の基材プレート１２Ｚを例えば破線で示した位置で複数に分割することにより個片化し、複数の剛性プレート１２を形成する（図２Ａ中段～下段）。なお、図２Ａでは一の基材プレート１２Ｚを３つの剛性プレート１２に切り分ける場合を示しているが、分割する数は任意に選択できる。 After the formation of the insulating layer Z, the single base plate 12Z in which the plurality of upper openings 15 and the plurality of openings 16 are formed is divided into a plurality of parts, for example, at positions indicated by broken lines, and a plurality of rigid plates 12 is formed (middle stage to lower stage in FIG. 2A). Although FIG. 2A shows a case where one base plate 12Z is cut into three rigid plates 12, the number to be divided can be arbitrarily selected.
　続いて図２Ｂに示したように、一の基板１１Ｚを用意し、複数の剛性プレート１２を一の基板１１Ｚの上に配列する。 Subsequently, as shown in FIG. 2B, one substrate 11Z is prepared, and a plurality of rigid plates 12 are arranged on the one substrate 11Z.
　続いて図２Ｃに示したように、基板１１Ｚ上における開口１５の内側の領域に複数の接続部１９を形成したのち、半導体チップ１３をそれぞれフリップチップ実装する。その際、接続部１９と半導体チップ１３の接続端子１３Ｔとをそれぞれ接続すると共に、半導体チップ１３と基板１１との隙間に樹脂層１７を充填する。ここで、剛性プレート１２の開口１５の平面寸法を半導体チップ１３の平面寸法よりも僅かに大きくするようにしたので、樹脂層１７は、開口１５の端面と接することとなる。 Subsequently, as shown in FIG. 2C, after a plurality of connecting portions 19 are formed in the region inside the opening 15 on the substrate 11Z, the semiconductor chips 13 are each mounted on the flip chip. At that time, the connection portion 19 and the connection terminal 13T of the semiconductor chip 13 are connected to each other, and the resin layer 17 is filled in the gap between the semiconductor chip 13 and the substrate 11. Here, since the planar dimension of the opening 15 of the rigid plate 12 is made slightly larger than the planar dimension of the semiconductor chip 13, the resin layer 17 comes into contact with the end face of the opening 15.
　続いて図２Ｄに示したように、基板１１Ｚ上における開口１６の内側の領域にはんだボールを載置してリフローを行うことにより、はんだ層１４をそれぞれ形成する。 Subsequently, as shown in FIG. 2D, the solder layer 14 is formed by placing the solder ball on the region inside the opening 16 on the substrate 11Z and performing reflow.
　続いて図２Ｅ上段に示したように、配線Ｌ２を覆うようにはんだボールを形成してリフローを行うことにより、接続端子Ｃ１を形成する。なお、はんだ層１４の形成と接続端子Ｃ１の形成とを同時に行うようにしてもよい。そののち、基板１１Ｚを、複数の剛性プレート１２の各々の外縁と対応する位置（図２Ｅの上段に示した破線の位置）で分割することにより、複数の半導体パッケージ１０を形成する（図２Ｅ下段）。 Subsequently, as shown in the upper part of FIG. 2E, a solder ball is formed so as to cover the wiring L2, and reflow is performed to form the connection terminal C1. Note that the solder layer 14 and the connection terminal C1 may be formed at the same time. Thereafter, the substrate 11Z is divided at positions corresponding to the outer edges of the plurality of rigid plates 12 (the positions indicated by broken lines in the upper part of FIG. 2E), thereby forming a plurality of semiconductor packages 10 (lower part of FIG. 2E). ).
　最後に、半導体パッケージ１０の上に半導体パッケージ２０を載置する。その際、基板２１の裏面に設けられた端子部Ｃ２と半導体パッケージ１０のはんだ層１４との位置合わせを行い、両者を電気的に接続するようにする。 Finally, the semiconductor package 20 is placed on the semiconductor package 10. At that time, the terminal portion C2 provided on the back surface of the substrate 21 and the solder layer 14 of the semiconductor package 10 are aligned so that they are electrically connected.
　以上により、半導体装置１が完成する。 Thus, the semiconductor device 1 is completed.
［半導体装置１の作用および効果］
　本実施の形態の半導体装置１およびその製造方法では、基板１１の上に、開口１５および開口１６を含む剛性プレート１２を積層するようにした。このため、基板１１上の開口１６に対応する位置にはんだ層１４を設け、基板２１の端子部Ｃ２とはんだ接続する構造であっても、半導体パッケージ１０に生じる曲がり（反り）を緩和することができる。よって、半導体パッケージ１０と半導体パッケージ２０との接続状態を良好に維持しやすくなり、高集積化に適した構造が実現される。 [Operation and Effect of Semiconductor Device 1]
In the semiconductor device 1 and the manufacturing method thereof according to the present embodiment, the rigid plate 12 including the opening 15 and the opening 16 is laminated on the substrate 11. For this reason, even if the solder layer 14 is provided at a position corresponding to the opening 16 on the substrate 11 and soldered to the terminal portion C2 of the substrate 21, the bending (warping) generated in the semiconductor package 10 can be reduced. it can. Therefore, it becomes easy to maintain a good connection state between the semiconductor package 10 and the semiconductor package 20, and a structure suitable for high integration is realized.
　特に、銅、銅合金、アルミニウムもしくはアルミニウム合金などの金属板により剛性プレート１２を形成した場合には、優れた強度、平坦性、加工性および放熱性などを得ることができる。 In particular, when the rigid plate 12 is formed of a metal plate such as copper, copper alloy, aluminum or aluminum alloy, excellent strength, flatness, workability, heat dissipation, and the like can be obtained.
　また、本実施の形態の半導体装置１の製造方法によれば、複数の剛性プレート１２を一の基板１０のＺ上に配列したのち、その基板１１Ｚを、複数の剛性プレート１２の各々の外縁と対応する位置で分割するようにした。このため、一の基板１１Ｚの上に配列する段階で基板１１Ｚの良品にのみ選択的に剛性プレート１２を配置することができるので、歩留まりが向上する。また、一の基材プレートと一の基板との寸法を一致させなくてすむので、製造過程におけるハンドリングが容易となる。 Further, according to the method of manufacturing the semiconductor device 1 of the present embodiment, after arranging the plurality of rigid plates 12 on the Z of one substrate 10, the substrate 11 </ b> Z is connected to each outer edge of the plurality of rigid plates 12. Split at the corresponding position. For this reason, since the rigid plate 12 can be selectively disposed only on the non-defective product of the substrate 11Z at the stage of arrangement on the one substrate 11Z, the yield is improved. Further, since it is not necessary to match the dimensions of one base plate and one substrate, handling in the manufacturing process becomes easy.
　さらに、本実施の形態の半導体装置１の製造方法によれば、剛性プレート１２を基板１１Ｚの上に配列したのち、その開口１５に対応する位置に半導体チップ１３を実装するようにした。このため、開口１５の大きさを半導体チップ１３の大きさに近づけることができ、半導体装置１の占有面積をより小さくするのに有利である。例えば、基板１１Ｚの上に予め半導体チップ１３を実装したのち、剛性プレート１２を配置することもできるが、その場合、半導体チップ１３と基板１１との間に樹脂層１７を充填する際に樹脂層１７が半導体チップ１３の周辺に広がってしまう。剛性プレート１２を平坦面上に載置する必要があるので、その場合には開口１５の大きさにマージンを持たせることとなる。これに対し、本実施の形態では、基板１０の上に予め載置された剛性プレート１２の開口１５の内部の領域に半導体チップ１３を実装するので、樹脂層１７の広がりを抑えることができる。 Furthermore, according to the method of manufacturing the semiconductor device 1 of the present embodiment, after the rigid plate 12 is arranged on the substrate 11Z, the semiconductor chip 13 is mounted at a position corresponding to the opening 15. For this reason, the size of the opening 15 can be brought close to the size of the semiconductor chip 13, which is advantageous for reducing the occupied area of the semiconductor device 1. For example, after mounting the semiconductor chip 13 on the substrate 11Z in advance, the rigid plate 12 can be disposed. In this case, the resin layer 17 is filled when the resin layer 17 is filled between the semiconductor chip 13 and the substrate 11. 17 spreads around the semiconductor chip 13. Since it is necessary to place the rigid plate 12 on a flat surface, a margin is given to the size of the opening 15 in that case. On the other hand, in this embodiment, since the semiconductor chip 13 is mounted in the region inside the opening 15 of the rigid plate 12 placed in advance on the substrate 10, the spread of the resin layer 17 can be suppressed.
　以上、実施の形態を挙げて本開示を説明したが、本開示は上記実施の形態に限定されるものではなく、種々の変形が可能である。 Although the present disclosure has been described with reference to the embodiment, the present disclosure is not limited to the above-described embodiment, and various modifications can be made.
　例えば、上記実施の形態で示した半導体パッケージ１０，２０の構成は例示であり、一部の構成要素が欠けていてもよいし、他の構成要素をさらに備えていてもよい。 For example, the configurations of the semiconductor packages 10 and 20 shown in the above embodiment are examples, and some components may be missing, or other components may be further provided.
　また、上記実施の形態の半導体装置の製造方法では、予め個片化した複数の剛性プレート１２を一の基板１１Ｚの上に配列するようにしたが、個片化する前の基材プレート１２Ｚをそのまま基板１１Ｚの上に載置したのち、基板１１Ｚと基材プレート１２Ｚとをまとめて切り分けるようにしてもよい。 In the method of manufacturing a semiconductor device according to the above embodiment, a plurality of rigid plates 12 separated in advance are arranged on one substrate 11Z. However, the base plate 12Z before being separated into individual pieces is arranged. After placing the substrate 11Z as it is, the substrate 11Z and the base plate 12Z may be cut together.
　また、上記実施の形態の半導体装置の製造方法では、剛性プレート１２を基板１０の上に配列したのち、その開口１５に対応する位置に半導体チップ１３を実装するようにしたが、本開示はこれに限定されるものではない。例えば、基板１１Ｚの上に予め半導体チップ１３を実装したのち、剛性プレート１２を配置するようにしてもよい。 In the method of manufacturing a semiconductor device according to the above-described embodiment, the rigid plate 12 is arranged on the substrate 10 and then the semiconductor chip 13 is mounted at a position corresponding to the opening 15. It is not limited to. For example, the rigid plate 12 may be disposed after the semiconductor chip 13 is mounted on the substrate 11Z in advance.
　上記実施の形態では、半導体チップをそれぞれフリップチップ実装するようにしたが、本技術はこれに限定されるものではない。例えば半導体チップをワイヤボンディングにより実装するようにしてもよい。 In the above embodiment, each semiconductor chip is flip-chip mounted, but the present technology is not limited to this. For example, a semiconductor chip may be mounted by wire bonding.
　なお、本明細書中に記載された効果はあくまで例示であってその記載に限定されるものではなく、他の効果があってもよい。また、本技術は以下のような構成を取り得るものである。
（１）
　配線層を含む第１の基板と、前記第１の基板に積層され、積層方向に貫く第１の開口および第２の開口を含む剛性プレートと、前記第１の基板上の、前記第１の開口の内側の領域に形成された第１の半導体チップと、前記第１の基板上の、前記第２の開口の内側の領域に形成されたはんだ層とを有する第１の半導体パッケージと、
　前記第１の半導体パッケージの上に積層され、前記はんだ層と接続された端子部を含む第２の基板と、前記第２の基板上に形成された第２の半導体チップとを有する　第２の半導体パッケージと
　を備えた複合型半導体装置。
（２）
　前記剛性プレートは非磁性金属からなり、
　前記第２の開口と前記はんだ層との間に絶縁層を有する
　上記（１）記載の複合型半導体装置。
（３）
　前記非磁性金属は、銅、銅合金、アルミニウムもしくはアルミニウム合金である
　上記（２）記載の複合型半導体装置。
（４）
　前記剛性プレートは、セラミックスまたはガラスからなる
　上記（１）記載の複合型半導体装置。
（５）
　前記第１の半導体チップの周囲に充填された樹脂層をさらに備え、
　前記樹脂層は、前記剛性プレートと接している
　上記（１）から（４）のいずれか１つに記載の複合型半導体装置。
（６）
　前記第１の半導体チップと前記第１の基板との間に充填された樹脂層と、前記樹脂層を貫くように前記第１の半導体チップと前記配線層とを繋ぐ複数の接続端子とをさらに備え、
　前記樹脂層は、前記剛性プレートと接している
　上記（１）から（４）のいずれか１つに記載の複合型半導体装置。
（７）
　剛性材料からなる一の基材プレートを用意し、前記基材プレートにおける所定の位置に複数の第１の開口および複数の第２の開口をそれぞれ形成することと、
　前記複数の第１の開口および前記複数の第２の開口が形成された前記一の基材プレートを複数に分割することにより個片化し、複数の剛性プレートを形成することと、
　一の基板を用意し、前記複数の剛性プレートを前記一の基板の上に配列することと、
　前記一の基板上の、前記複数の第１の開口と対応する位置に第１の半導体チップをそれぞれ実装することと、
　前記一の基板上の、前記複数の第２の開口と対応する位置にはんだ層をそれぞれ形成することと、
　前記一の基板を、前記複数の剛性プレートの各々の外縁と対応する位置で分割することにより、複数の第１の半導体パッケージを形成することと、
　前記第１の半導体パッケージの上に、端子部を含む第２の基板の上に第２の半導体チップを設けた第２の半導体パッケージを載置し、前記はんだ層と前記端子部とを接続することと
　を含む複合型半導体装置の製造方法。
（８）
　前記複数の剛性プレートを前記一の基板の上に配列したのち、前記一の基板上に前記複数の第１の半導体チップをそれぞれ実装する
　上記（７）記載の複合型半導体装置の製造方法。 In addition, the effect described in this specification is an illustration to the last, and is not limited to the description, There may exist another effect. Moreover, this technique can take the following structures.
(1)
A first substrate including a wiring layer; a rigid plate including a first opening and a second opening stacked on the first substrate and penetrating in a stacking direction; and the first substrate on the first substrate. A first semiconductor package having a first semiconductor chip formed in a region inside the opening, and a solder layer formed in a region inside the second opening on the first substrate;
A second substrate including a terminal portion stacked on the first semiconductor package and connected to the solder layer; and a second semiconductor chip formed on the second substrate. A compound semiconductor device comprising a semiconductor package.
(2)
The rigid plate is made of a non-magnetic metal,
The composite semiconductor device according to (1), wherein an insulating layer is provided between the second opening and the solder layer.
(3)
The composite semiconductor device according to (2), wherein the nonmagnetic metal is copper, a copper alloy, aluminum, or an aluminum alloy.
(4)
The composite semiconductor device according to (1), wherein the rigid plate is made of ceramics or glass.
(5)
A resin layer filled around the first semiconductor chip;
The composite semiconductor device according to any one of (1) to (4), wherein the resin layer is in contact with the rigid plate.
(6)
A resin layer filled between the first semiconductor chip and the first substrate, and a plurality of connection terminals connecting the first semiconductor chip and the wiring layer so as to penetrate the resin layer Prepared,
The composite semiconductor device according to any one of (1) to (4), wherein the resin layer is in contact with the rigid plate.
(7)
Preparing a base plate made of a rigid material, and forming a plurality of first openings and a plurality of second openings at predetermined positions in the base plate;
Dividing the one base plate in which the plurality of first openings and the plurality of second openings are formed into a plurality of pieces, thereby forming a plurality of rigid plates;
Providing a substrate and arranging the plurality of rigid plates on the substrate;
Mounting each of the first semiconductor chips on the one substrate at a position corresponding to the plurality of first openings;
Forming solder layers on the one substrate at positions corresponding to the plurality of second openings,
Forming the plurality of first semiconductor packages by dividing the one substrate at a position corresponding to an outer edge of each of the plurality of rigid plates;
A second semiconductor package in which a second semiconductor chip is provided on a second substrate including a terminal portion is placed on the first semiconductor package, and the solder layer and the terminal portion are connected. And a method of manufacturing a composite semiconductor device.
(8)
The method of manufacturing a composite semiconductor device according to (7), wherein the plurality of rigid plates are arranged on the one substrate, and then the plurality of first semiconductor chips are mounted on the one substrate.
　本出願は、日本国特許庁において２０１５年６月１６日に出願された日本特許出願番号２０１５－１２１３２１号を基礎として優先権を主張するものであり、この出願のすべての内容を参照によって本出願に援用する。 This application claims priority on the basis of Japanese Patent Application No. 2015-121321 filed on June 16, 2015 at the Japan Patent Office. The entire contents of this application are hereby incorporated by reference. Incorporated into.
　当業者であれば、設計上の要件や他の要因に応じて、種々の修正、コンビネーション、サブコンビネーション、および変更を想到し得るが、それらは添付の請求の範囲やその均等物の範囲に含まれるものであることが理解される。 Those skilled in the art will envision various modifications, combinations, subcombinations, and changes, depending on design requirements and other factors, which are within the scope of the appended claims and their equivalents. It is understood that

Claims (8)

  1. 　配線層を含む第１の基板と、前記第１の基板に積層され、積層方向に貫く第１の開口および第２の開口を含む剛性プレートと、前記第１の基板上の、前記第１の開口の内側の領域に形成された第１の半導体チップと、前記第１の基板上の、前記第２の開口の内側の領域に形成されたはんだ層とを有する第１の半導体パッケージと、
    　前記第１の半導体パッケージの上に積層され、前記はんだ層と接続された端子部を含む第２の基板と、前記第２の基板上に形成された第２の半導体チップとを有する第２の半導体パッケージと
    　を備えた複合型半導体装置。     A first substrate including a wiring layer; a rigid plate including a first opening and a second opening stacked on the first substrate and penetrating in a stacking direction; and the first substrate on the first substrate. A first semiconductor package having a first semiconductor chip formed in a region inside the opening, and a solder layer formed in a region inside the second opening on the first substrate;
    A second substrate having a second substrate including a terminal portion stacked on the first semiconductor package and connected to the solder layer, and a second semiconductor chip formed on the second substrate. A compound semiconductor device comprising a semiconductor package.
  2. 　前記剛性プレートは非磁性金属からなり、
    　前記第２の開口と前記はんだ層との間に絶縁層を有する
    　請求項１記載の複合型半導体装置。     The rigid plate is made of a non-magnetic metal,
    The composite semiconductor device according to claim 1, further comprising an insulating layer between the second opening and the solder layer.
  3. 　前記非磁性金属は、銅、銅合金、アルミニウムもしくはアルミニウム合金である
    　請求項２記載の複合型半導体装置。     The composite semiconductor device according to claim 2, wherein the nonmagnetic metal is copper, a copper alloy, aluminum, or an aluminum alloy.
  4. 　前記剛性プレートは、セラミックスまたはガラスからなる
    　請求項１記載の複合型半導体装置。     The composite semiconductor device according to claim 1, wherein the rigid plate is made of ceramics or glass.
  5. 　前記第１の半導体チップの周囲に充填された樹脂層をさらに備え、
    　前記樹脂層は、前記剛性プレートと接している
    　請求項１記載の複合型半導体装置。     A resin layer filled around the first semiconductor chip;
    The composite semiconductor device according to claim 1, wherein the resin layer is in contact with the rigid plate.
  6. 　前記第１の半導体チップと前記第１の基板との間に充填された樹脂層と、前記樹脂層を貫くように前記第１の半導体チップと前記配線層とを繋ぐ複数の接続端子とをさらに備え、
    　前記樹脂層は、前記剛性プレートと接している
    　請求項１記載の複合型半導体装置。     A resin layer filled between the first semiconductor chip and the first substrate, and a plurality of connection terminals connecting the first semiconductor chip and the wiring layer so as to penetrate the resin layer Prepared,
    The composite semiconductor device according to claim 1, wherein the resin layer is in contact with the rigid plate.
  7. 　剛性材料からなる一の基材プレートを用意し、前記基材プレートにおける所定の位置に複数の第１の開口および複数の第２の開口をそれぞれ形成することと、
    　前記複数の第１の開口および前記複数の第２の開口が形成された前記一の基材プレートを複数に分割することにより個片化し、複数の剛性プレートを形成することと、
    　一の基板を用意し、前記複数の剛性プレートを前記一の基板の上に配列することと、
    　前記一の基板上の、前記複数の第１の開口と対応する位置に第１の半導体チップをそれぞれ実装することと、
    　前記一の基板上の、前記複数の第２の開口と対応する位置にはんだ層をそれぞれ形成することと、
    　前記一の基板を、前記複数の剛性プレートの各々の外縁と対応する位置で分割することにより、複数の第１の半導体パッケージを形成することと、
    　前記第１の半導体パッケージの上に、端子部を含む第２の基板の上に第２の半導体チップを設けた第２の半導体パッケージを載置し、前記はんだ層と前記端子部とを接続することと
    　を含む複合型半導体装置の製造方法。     Preparing a base plate made of a rigid material, and forming a plurality of first openings and a plurality of second openings at predetermined positions in the base plate;
    Dividing the one base plate in which the plurality of first openings and the plurality of second openings are formed into a plurality of pieces, thereby forming a plurality of rigid plates;
    Providing a substrate and arranging the plurality of rigid plates on the substrate;
    Mounting each of the first semiconductor chips on the one substrate at a position corresponding to the plurality of first openings;
    Forming solder layers on the one substrate at positions corresponding to the plurality of second openings,
    Forming the plurality of first semiconductor packages by dividing the one substrate at a position corresponding to an outer edge of each of the plurality of rigid plates;
    A second semiconductor package in which a second semiconductor chip is provided on a second substrate including a terminal portion is placed on the first semiconductor package, and the solder layer and the terminal portion are connected. And a method of manufacturing a composite semiconductor device.
  8. 　前記複数の剛性プレートを前記一の基板の上に配列したのち、前記一の基板上に前記複数の第１の半導体チップをそれぞれ実装する
    　請求項７記載の複合型半導体装置の製造方法。     The method of manufacturing a composite semiconductor device according to claim 7, wherein after arranging the plurality of rigid plates on the one substrate, the plurality of first semiconductor chips are respectively mounted on the one substrate.
PCT/JP2016/065633 2015-06-16 2016-05-26 Compound semiconductor device and method for manufacturing same WO2016203927A1 (en)

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