CN117276260A - 模块化半导体器件及包含该器件的电子器件 - Google Patents

模块化半导体器件及包含该器件的电子器件 Download PDF

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Publication number
CN117276260A
CN117276260A CN202210678569.8A CN202210678569A CN117276260A CN 117276260 A CN117276260 A CN 117276260A CN 202210678569 A CN202210678569 A CN 202210678569A CN 117276260 A CN117276260 A CN 117276260A
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Prior art keywords
interposer
layer
conductive
semiconductor
modular
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CN202210678569.8A
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Inventor
朴寿汉
金敬银
申裕珍
金惠善
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Priority to CN202210678569.8A priority Critical patent/CN117276260A/zh
Priority to KR1020230068354A priority patent/KR20230172403A/ko
Priority to US18/332,777 priority patent/US20230411263A1/en
Publication of CN117276260A publication Critical patent/CN117276260A/zh
Pending legal-status Critical Current

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    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82105—Forming a build-up interconnect by additive methods, e.g. direct writing by using a preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors

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Abstract

本申请提供了一种模块化半导体器件。模块化半导体器件包括：密封剂层，具有密封剂底面和密封剂顶面，包括元件区和层间连接区；半导体元件，设置于元件区内，包括暴露于密封剂底面的元件导电图案；层间连接阵列，设置于层间连接区内，包括一个或多个导电通孔，每个导电通孔在密封剂底面和密封剂顶面之间延伸；以及中介层，层叠于密封剂层上，并具有中介层底面及中介层顶面，其中中介层顶面与密封剂底面接触；并且其中，中介层包括中介层导电图案和中介层互连结构，中介层导电图案位于中介层底面上，中介层互连结构电耦接到元件导电图案、中介层导电图案和一个或多个导电通孔。

Description

模块化半导体器件及包含该器件的电子器件
技术领域
本申请总体上涉及半导体技术，更具体地，涉及一种模块化半导体器件及包含该模块化半导体器件的电子器件。
背景技术
半导体器件常见于现代电子产品中，它们执行广泛的功能，例如信号处理、高速计算、发送和接收电磁信号、控制电子设备以及为电视显示器创建视觉图像。集成电路可以制造于半导体裸片内。半导体裸片也可以称为芯片，其具有包括导电图案的表面，其用于将芯片与外部器件连接。
随着电子产品的不断改进，需要在单个封装件中集成越来越多的半导体裸片。然而，由于用于安装半导体裸片的基底的布局预算有限，因此需要一种改进的用于半导体器件的封装技术。
发明内容
本申请的目的在于提供一种半导体器件，其具有减少的对用于半导体器件的基底的布局的占用。
根据本申请的实施例的一个方面，提供了一种模块化半导体器件。所述模块化半导体器件包括：密封剂层，所述密封剂层具有密封剂底面和密封剂顶面，其中所述密封剂层包括元件区和层间连接区；半导体元件，所述半导体元件设置于所述元件区内，其中所述半导体元件包括暴露于所述密封剂底面的元件导电图案；层间连接阵列，所述层间连接阵列设置于所述层间连接区内，其中所述层间连接阵列包括一个或多个导电通孔，每个所述导电通孔在所述密封剂底面和所述密封剂顶面之间延伸；以及中介层，所述中介层层叠于所述密封剂层上，并具有中介层底面及中介层顶面，其中所述中介层顶面与所述密封剂底面接触；并且其中，所述中介层包括中介层导电图案和中介层互连结构，所述中介层导电图案位于所述中介层底面上，所述中介层互连结构电耦接到所述元件导电图案、所述中介层导电图案和所述一个或多个导电通孔。
根据本申请的实施例的另一个方面，提供了一种电子器件。所述电子器件包括：基底，所述基底包括基底互连结构；基础半导体元件，所述基础半导体元件安装于所述基底上并电耦接到所述基底互连结构；一个或多个基础通孔，所述一个或多个基础通孔安装于基底上并电耦接到所述基底互连结构；第一模块化半导体器件，所述第一模块化半导体器件堆叠在所述基础半导体元件和所述一个或多个基础通孔上，其中所述第一模块化半导体器件包括：密封剂层，所述密封剂层具有密封剂底面和密封剂顶面，其中所述密封剂层包括元件区和层间连接区；半导体元件，所述半导体元件设置于所述元件区内，其中所述半导体元件包括暴露于所述密封剂底面的元件导电图案；层间连接阵列，所述层间连接阵列设置于所述层间连接区内，其中所述层间连接阵列包括一个或多个导电通孔，每个所述导电通孔在所述密封剂底面和所述密封剂顶面之间延伸；以及中介层，所述中介层层叠于所述密封剂层上，并具有中介层底面及中介层顶面，其中所述中介层顶面与所述密封剂底面接触；并且其中，所述中介层包括中介层导电图案和中介层互连结构，所述中介层导电图案位于所述中介层底面上，所述中介层互连结构电耦接到所述元件导电图案、所述中介层导电图案和所述一个或多个导电通孔，并且其中所述中介层导电图案电耦接到所述一个或多个基础通孔。
根据本申请的实施例的又一个方面，提供了用于制造上述方面的模块化半导体器件和电子器件的方法。
应当理解，前面的一般描述和下面的详细描述都只是示例性和说明性的，而不是对本发明的限制。此外，并入并构成本说明书一部分的附图说明了本发明的实施例并且与说明书一起用于解释本发明的原理。
附图说明
本文引用的附图构成说明书的一部分。附图中所示的特征仅图示了本申请的一些实施例，而不是本申请的所有实施例，除非详细描述另有明确说明，并且说明书的读者不应做出相反的暗示。
图1A和图1B是根据本申请一个实施例的具有模块化半导体器件的电子器件。
图2和图3示出了根据本申请一些实施例的具有若干模块化半导体器件的电子器件。
图4示出了根据本申请另一实施例的具有模块化半导体器件的电子器件。
图5示出了根据本申请另一实施例的具有模块化半导体器件的电子器件。
图6A至图6I示出了根据本申请一个实施例的用于制造具有模块化半导体器件的电子器件的方法。
图7A至7F示出了根据本申请一个实施例的用于制造模块化半导体器件的方法。
图8A至图8G示出了根据本申请一个实施例的用于制造模块化半导体器件的方法。
在整个附图中将使用相同的附图标记来表示相同或相似的部分。
具体实施方式
本申请示例性实施例的以下详细描述参考了形成描述的一部分的附图。附图示出了其中可以实践本申请的具体示例性实施例。包括附图在内的详细描述足够详细地描述了这些实施例，以使本领域技术人员能够实践本申请。本领域技术人员可以进一步利用本申请的其他实施例，并在不脱离本申请的精神或范围的情况下进行逻辑、机械等变化。因此，以下详细描述的读者不应以限制性的方式解释该描述，并且仅以所附权利要求限定本申请的实施例的范围。
在本申请中，除非另有明确说明，否则使用单数包括了复数。在本申请中，除非另有说明，否则使用“或”是指“和/或”。此外，使用术语“包括”以及诸如“包含”和“含有”的其他形式的不是限制性的。此外，除非另有明确说明，诸如“元件”或“部件”之类的术语覆盖了包括一个单元的元件和部件，以及包括多于一个子单元的元件和部件。此外，本文使用的章节标题仅用于组织目的，不应解释为限制所描述的主题。
如本文所用，空间上相对的术语，例如“下方”、“下面”、“上方”、“上面”、“上”、“上侧”、“下侧”、“左侧”、“右侧”、“水平”、“竖直”、“侧”等等，可以在本文中使用，以便于描述如附图中所示的一个元件或特征与另一个或多个元件或特征的关系。除了图中描绘的方向之外，空间相对术语旨在涵盖设备在使用或操作中的不同方向。该器件可以以其他方式定向(旋转90度或在其他方向)，并且本文使用的空间相关描述符同样可以相应地解释。应该理解，当一个元件被称为“连接到”或“耦接到”另一个元件时，它可以直接连接到或耦接到另一个元件，或者可以存在中间元件。
图1A和1B示出了根据本申请一个实施例的具有模块化半导体器件120的电子器件100。图1A显示电子器件100的俯视图，而图1B显示电子器件100沿图1A的剖面线AA的截面图。
如图1A和1B所示，电子器件100包括基底102，一个或多个元件安装于基底102上。基底102可以包括一个或多个绝缘或钝化层以及形成在该绝缘或钝化层中的一个或多个基底互连结构(未示出)。每个基底互连结构可以包括穿过绝缘或钝化层形成的一个或多个导电通孔，以及形成在基底102的顶面和/或底面上的一个或多个导电层。基底102可以包括一个或多个层叠的具有酚醛棉纸、环氧树脂、树脂、编织玻璃、磨砂玻璃、聚酯和其他增强纤维或织物的组合的预浸渍聚四氟乙烯、FR-4、FR-1、CEM-1或CEM-3。基底102也可以是多层柔性层叠板、陶瓷、覆铜层叠板或玻璃。在一些实施例中，基底102内的基底互连结构或再分布层(RDL)可以使用溅射、电解电镀、化学镀或其他合适的沉积过程形成。该导电通孔和导电层可以是一层或多层Al、Cu、Sn、Ni、Au、Ag、钛(Ti)、钨(W)或其他合适的导电材料。
基础半导体元件104与各种其他分立元件106一起安装于基底102上，该分立元件106例如电容器、电阻器或类似电子元件或板对板连接器。在一些实施例中，基础半导体元件104可以包括半导体裸片或半导体封装件以实现模拟或数字电路。例如，半导体裸片可以以倒装芯片方式形成并且可以安装到基底102的顶面上，使得半导体裸片的导电图案可以焊接到基底102中的基底互连结构上。在一些其他的实施例中，半导体裸片可以包括可以通过引线接合连接到基底互连结构的接合焊盘。通过基底互连结构，基础半导体元件104可以电耦接到外部电子设备或电子器件100的分立元件106，下文对其详述。
尽管图1B中未示出，但基底互连结构的一部分可以嵌入基底102内且位于基础半导体元件104下方。此外，基底互连结构的另一部分可以横向沿着基底102延伸并且可以位于一些其他元件106或电子器件100的结构下方。如图1B所示，一个或多个基础通孔108安装于基底102上并且电耦接到基底互连结构。在一些实施例中，基础通孔108可以接合或焊接到基底互连结构以确保它们之间的电连接。在图1B所示的实施例中，基础通孔108形成为突起e-bar结构，其是具有多层导电桩的块或板。突起e-bar结构的块或板可以由二氧化硅(SiO2)、氮化硅(Si3N4)、氧氮化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、阻焊剂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)和其他具有类似绝缘和结构特性的材料的一层或多层制成。突起e-bar结构的块或板也可以是多层柔性层叠板、陶瓷、覆铜层叠板、玻璃、环氧树脂模塑料或半导体晶圆。在另一个实施例中，突起e-bar结构的块或板也可以是任何合适的层叠中介层、PCB、晶圆形式、条状中介层、引线框或其它类型的基底。块或板可以包括一个或多个层叠的具有酚醛棉纸、环氧树脂、树脂、编织玻璃、磨砂玻璃、聚酯和其他增强纤维或织物的组合的预浸渍(prepreg)聚四氟乙烯(PTFE)、FR-4、FR-1、CEM-1或CEM-3。基础通孔108或特别是导电桩可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料，并且可以使用PVD、CVD、电解电镀、化学镀过程，或其他合适的金属沉积过程形成。在一些实施例中，可以将突起e-bar结构预形成为单件，从而可以容易地安装到基底102上。
如图1B所示，基础通孔108(包括其接合焊盘或导电凸块166)的厚度大体上等于基础半导体元件104的厚度。如此以来，附加的半导体元件或器件，即本实施例中的模块化半导体器件120，可堆叠于基础半导体元件104及基础通孔108之上。模块化半导体器件120被预形成为单件，因此容易将其放置在基础半导体元件104之上，而无需诸如互连沉积之类的复杂过程。此外，出于保护目的，可以形成全局密封剂层150以覆盖基底102上的各种元件和器件。例如，可以通过在将模块化半导体器件120放置在基础半导体元件104上方之后沉积密封剂材料来形成密封剂层150。
具体地，模块化半导体器件120包括密封剂层122，其密封其他子元件并保护它们免受外部损坏。此外，密封剂层122可以将模块化半导体器件120的子元件组装在一起，使得它们可以在以后的操作中一起移动和处理。如图1B所示，密封剂层122具有密封剂底面124以及与密封剂底面124相对的密封剂顶面126。此外，密封剂层122可以包括元件区128和相邻于元件区128的层间连接区130。当与基础半导体元件104和基础通孔108连接时，元件区128与基础半导体元件104大体对齐，层间连接区130与基础通孔108大体对齐。
半导体元件132设置于元件区128内，其用于实现数字或模拟电路。在一些实施例中，半导体元件132可以是半导体裸片或半导体封装件。半导体元件132与其下方的基础半导体元件104需要电耦接，以实现电子器件100的紧凑结构，并减少对基底102的过多布局(layout)的占用。为了将两者连接起来，半导体元件132包括从密封剂底面124暴露的元件导电图案148，其用作半导体元件132与其他外部元件或器件之间的接口。
模块化半导体器件120还包括在层间连接区130内设置的层间连接阵列134。层间连接阵列134包括一个或多个导电通孔136，每个导电通孔在密封剂底面124和密封剂顶面126之间延伸。也即，导电通孔136同时暴露于密封剂底面124和密封剂顶面126，并实现穿过层间连接区130的垂直信号路径。在图1B所示的实施例中，层间连接阵列134形成为具有导电通孔的突起e-bar结构，该导电通孔由一层或多层Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料制成，其可以类似于基础通孔108，因此在此不再详述。类似地，形成为突起e-bar结构的层间连接阵列134可以预形成为单件，从而可以容易地安装到其他元件或结构。
在一些实施例中，密封剂层122可以具有与半导体元件132的厚度相等的厚度，以减小模块化半导体器件120的总厚度。然而，在一些其他实施例中，密封剂层122的厚度可以大于半导体元件132的厚度，以保护半导体元件132的顶面。
中介层138层叠在密封剂层122上。中介层138具有中介层底面140和与中介层底面140相对的中介层顶面142。中介层顶面142接触密封剂底面124。当模块化半导体器件120与基础半导体元件104和底部通孔108附接时，中介层顶面140与它们各自的顶面直接或通过互连焊球(例如，焊球166)相连。具体地，中介层138包括中介互连结构144，其电耦接到元件导电图案148和一个或多个导电通孔136。此外，中介层138还包括中介层底面140上的中介层导电图案146，其也电耦接到中介层互连结构144。这样，中介层导电图案146在模块化半导体器件120底侧作为其接口，以实现与其下方的基础半导体元件104的信号交互。在模块化半导体器件120的另一侧，即密封剂层122的顶面，导电通孔136的暴露顶面用作模块化半导体器件120的另一个接口，以实现与安装在模块化半导体器件120上方的其他半导体元件(未示出)的信号交互。
在图1A和1B所示的实施例中，半导体元件/器件的堆叠布置为不对称布局。也就是说，模块化半导体器件120布置在整体电子器件100的一侧，而不是占据电子器件100的整个布局。由于模块化半导体器件120不与基础半导体元件104的全部顶面重叠，基础半导体元件104散发的热量不直接影响模块化半导体器件120的整体，反之亦然。这种非对称布局可以帮助改善整体器件的翘曲控制。此外，基础半导体元件104可能不与模块化半导体器件120的半导体元件132完全重叠。例如，半导体元件132可以具有小于基础半导体元件104的尺寸。
尽管在图1B示出了仅一个模块化半导体器件120堆叠在基础半导体元件104上方并通过互连的基础通孔108和互连焊球(例如，焊球166)电耦接到基础半导体元件104，但是在一些其他实施例中，一个或多个附加模块化半导体器件可以类似地进一步堆叠在模块化半导体器件120之上，如图2和3所示。
在图2所示的实施例中，三个模块化半导体器件220堆叠在基础半导体元件204上，并且包含在电子器件中的所有半导体元件可以通过导电通孔“中枢”电耦接在一起，该“中枢”包括基础通孔208，多个模块化半导体器件220的第一组导电通孔236a、第二组导电通孔236b和第三组导电通孔236c。所有模块化半导体器件220都具有暴露于其顶面和底面的导电结构，因此它们可以电耦接到它们上方和/或下方的相应器件。此外，在图3所示的实施例中，五个模块化半导体器件以相对于导电通孔的垂直“中枢”交替的布置方式堆叠在基础半导体元件上方。由于模块化半导体器件的有源半导体元件332a至332e彼此不是很接近，这种布置的热管理得以改进。可以理解的是，相邻的模块化半导体器件的暴露的导电结构可以通过焊接材料接合在一起以实现电连接。
尽管在图1A和图1B中示出的基础通孔108和层间连接阵列134形成为突起e-bar结构，它们可以形成为任何其他合适的互连结构。图4和5示出了根据本申请的一些实施例的具有不同互连结构的两个模块化半导体器件。
如图4所示，电子器件400包括基底402。基础半导体元件404安装到基底402上并电耦接到形成在基底402内部的基底互连结构(未示出)。一个或多个基础通孔408也形成于基底402上，以将基底互连结构连接到上部模块化半导体器件420。基础通孔408由通过密封剂层450a彼此隔开的导电柱制成。基础通孔408的导电柱可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料，并且可以使用PVD、CVD、电解电镀、化学镀过程，或其他合适的金属沉积过程形成。在一些实施例中，可以在将基础半导体元件404安装于基底402上之后形成导电柱408。然后，可以在导电柱408和基础半导体元件404上沉积密封剂材料以形成密封剂层450a。在将模块化半导体器件420安装于密封剂层450a上之前，密封剂层450a可以被平坦化，并被蚀刻(例如，通过激光束)以暴露导电柱408的顶面。焊球466可以被放置在导电柱408的顶面上方。以这种方式，模块化半导体器件420可以放置在导电柱408上方并且电耦接到导电柱408，并且因此电耦接到基底半导体元件402。
仍然参考图4，除了层间连接阵列434形成为一组导电柱436，模块化半导体器件420具有与图1A和图1B所示的模块化半导体器件120相似的结构。层间连接阵列434的导电柱通过密封剂层422彼此分离。具体地，导电柱436形成在在密封剂层422的层间连接区430内，且在密封剂层422的元件区428中的半导体元件432旁边。导电柱436在密封剂顶面426和密封剂底面424之间延伸。在密封剂底面424上，导电柱436电耦接到层叠在密封剂层422下方的中介层438内的中介层互连结构444。此外，中介层438还包括中介层导电图案446，其电耦接到中介层互连结构444。这样，中介层导电图案446在模块化半导体器件420底侧用作其接口，以实现与其下方的基础半导体元件404的信号交互。模块化半导体器件420可以由另一个密封剂层450b密封。在一些实施例中，密封剂层450b和密封剂层450a可以在单个过程中形成，而不是在两个过程中分别形成，例如，在模块化半导体器件420被放置在基础半导体元件404上方之后。
如图5所示，另一个模块化半导体器件500包括安装在基底502上的基础半导体元件504和安装在基础半导体元件504上方的模块化半导体器件520。与图4所示的实施例不同，基部通孔508和层间连接阵列534的导电通孔536形成为焊球。焊球可以具有不同的尺寸或厚度，这取决于与它们设置在相同的层中的各个半导体元件。
如前所述，图1A至1B和图2至5中所示的每个模块化半导体器件是可预形成为单件。这样以来，更容易将这种模块化半导体器件堆叠到安装了有一个或多个基础半导体元件的基底上。在一些实施例中，多个半导体元件可以被放置在载体上，并且然后可以将它们与多个导电通孔一起封装，它们随后在同一批次中被分割成独立的模块化半导体器件。这种“板级”封装过程可以显著提高模块化半导体器件的生产率。此外，可以在封装过程之前对半导体元件进行预测试，这也可以通过在封装过程之前丢弃不合格的半导体元件来提高所得模块化半导体器件的良率。
图6A至图6I示出了根据本申请的一个实施例的用于制造图1A至图1B所示电子器件的方法。
如图6A所示，可以提供诸如玻璃载体或金属载体的载体660，其顶面由诸如粘性胶带的临时接合层662覆盖。例如，粘性胶带可以是聚酰亚胺薄膜。临时接合层662可以在制造过程中保护载体660并且将其他层和元件临时附接到载体660。
如图6B所示，一个或多个半导体元件632和一个或多个层间连接阵列634可以放置于临时接合层662上。层间连接阵列634可以放置于半导体元件632旁边。具体地，半导体元件632包括朝向向上远离载体660的元件导电图案648。层间连接阵列634具有一个或多个导电通孔636。层间连接阵列634的高度等于半导体元件632的高度，以使得导电通孔636的顶面和元件导电图案648大体上处于同一水平面。在该实施例中，层间连接阵列634形成为突起e-bar结构，其可以预先形成。
接下来，如图6C所示，可以在载体660上，或者具体地在临时接合层662上沉积密封剂材料，以形成密封剂层622。密封剂层622可以密封半导体元件632和层间连接阵列634。在一些实施例中，可以使用模塑过程来沉积密封剂层622。
之后，如图6D所示，可减薄密封剂层622，例如使用背磨过程，以去除半导体元件632和层间连接阵列634上方的过量的密封剂材料。以这种方式，半导体元件632和层间连接阵列634以及它们各自顶面上的各自导电结构可以被暴露以供进一步处理。
如图6E所示，中介层638可以层叠在密封剂层622上。中介层638包括在中介层638的暴露表面上的至少一个中介层导电图案646，以及至少一个中介层互连结构644。至少一个中介层互连结构644电耦接到中介层导电图案646、元件导电图案648和层间连接阵列634的一个或多个导电通孔636。在一些实施例中，中介层互连结构644可以包括中介层基底内部的导电层或再分布层(RDL)，并且可以使用溅射、电解电镀、化学镀或其他合适的沉积过程形成。导电层可以是一层或多层Al、Cu、Sn、Ni、Au、Ag、钛(Ti)、钨(W)或其他合适的导电材料。在图6E所示的实施例中，焊球666被接合到相应的中介层导电图案646，以便于随后的附接过程。
如图6F所示，可以将层叠在一起的密封剂层622和中介层638分割成单独的模块化半导体器件。每个模块化半导体器件可以包括半导体元件和层间连接阵列。之后，可以从载体上移除单独的模块化半导体器件。
模块化半导体器件可以与其他半导体元件一起封装以形成堆叠结构。如图6G所示，提供了具有基础半导体元件604和各种其他分立元件606的基底602。基底602还具有形成在其上的一个或多个基础通孔608。在该实施例中，基础通孔608形成为突起e-bar结构，类似于模块化半导体器件的层间连接阵列。接下来，如图6H所示，模块化半导体器件可以堆叠在基础半导体元件604和基础通孔608之上，并且模块化半导体器件的半导体元件632可以通过基部通孔608和焊球666电连接到基础半导体元件604。
之后，如图6I所示，可以在基底602上沉积另一种密封剂材料以形成保护所有元件免受外部环境影响的密封剂层650。可以理解，更多的模块化半导体器件可以堆叠在基底602上，它们可以全部被密封剂材料封装。
图7A至7F示出了根据本申请一个实施例的用于制造图4所示的模块化半导体器件的方法。
如图7A所示，可以提供诸如玻璃载体或金属载体的载体760，其顶面被诸如粘性胶带的临时接合层762覆盖。例如，粘性胶带可以是聚酰亚胺薄膜。临时接合层762可以在制造过程中保护载体760并且将其他层和元件临时附接到载体760。在一些实施例中，可以省略临时接合层762。
如图7B所示，可在基底760上形成临时基底层770。可在该临时基底层770内形成一个或多个导电层(未示出)，其用作一个或多个层间连接阵列734的锚定点。在该实施例中，每个层间连接阵列734可以包括一个或多个导电柱736，其从临时基底层770向上延伸。
如图7C所示，一个或多个半导体元件732可以放置在临时基底层770上。半导体元件732可以放置在各自的层间连接阵列734旁边。具体地，半导体元件732包括朝向向上远离载体760的元件导电图案748。层间连接阵列734具有与半导体元件732相同的高度，使得导电柱736的顶面和元件导电图案748大体处于同一水平。
接下来，如图7D所示，可以在载体760上，或者具体地在临时基底层770上沉积密封剂材料，以形成密封剂层722。密封剂层722可以密封半导体元件732和层间连接阵列734。密封剂层722可以被减薄，例如，使用背磨过程，以去除半导体元件732和层间连接阵列734上方的过量密封剂材料。
如图7E所示，可以在密封剂层722上层叠中介层738。中介层738包括在中介层722的暴露表面上的至少一个中介层导电图案746，以及至少一个中介层互连结构744。该至少一个中介层互连结构744电耦接到中介层导电图案746、元件导电图案748和层间连接阵列734的一个或多个导电柱736。此外，焊球766被接合到相应的中介层导电图案746，以促进随后的附接过程。
如图7F所示，可以将层叠在一起的密封剂层722和中介层738分割成单独的模块化半导体器件。每个模块化半导体器件可以包括半导体元件和层间连接阵列。之后，可以从载体上去除单独的模块化半导体器件，并且也可以从分割出的单个模块化半导体器件去除临时基底层。
图8A至8G示出了根据本申请一个实施例的用于制造图5所示的模块化半导体器件的方法。
如图8A所示，可以提供诸如玻璃载体或金属载体的载体860，其顶面被诸如粘性胶带的临时接合层862覆盖。例如，粘性胶带可以是聚酰亚胺薄膜。临时接合层862可以在制造过程中保护载体860并且将其他层和元件临时附接到载体860。在一些实施例中，可以省略临时接合层862。
如图8B所示，可在基底860上形成临时基底层870。可在临时基底层870内形成一个或多个导电层872，其用作其上形成的一个或多个层间连接阵列的种子图案。在该实施例中，导电层872沿垂直方向延伸并且从临时基底层870的顶面暴露。
如图8C所示，一个或多个层间连接阵列834形成在基底860上，或者具体地在临时基底层870上。在该实施例中，每个层间连接阵列834包括一组焊料球836，其贴附在临时基底层870内的导电层872上。
如图8D所示，一个或多个半导体元件832可以放置在临时基底层870上。半导体元件832可以放置在各自的层间连接阵列834旁边。具体地，半导体元件832包括朝向向上远离载体860的元件导电图案848。层间连接阵列834的高度等于半导体元件832的高度，使得焊球836的顶面和元件导电图案848大体上处于同一水平。
接下来，如图8E所示，可以在载体860上，或者具体地在临时基底层870上沉积密封剂材料，以形成密封剂层822。密封剂层822可以密封半导体元件832和层间连接阵列834。密封剂层822可以被减薄，例如，使用背磨过程，以去除半导体元件832和层间连接阵列834上方过量的密封剂材料。
如图8F所示，可以在密封剂层822上层叠中介层838。中介层838包括在中介层822的暴露表面上的至少一个中介层导电图案846，以及至少一个中介层互连结构844。该至少一个中介层互连结构844电耦接到中介层导电图案846、元件导电图案848和层间连接阵列834的一个或多个焊球836。此外，附加的焊球866接合到相应的中介层导电图案846，以促进随后的附接过程。
如图8G所示，可以将层叠在一起的密封剂层822和中介层838分割成单独的模块化半导体器件。每个模块化半导体器件可以包括半导体元件和层间连接阵列。之后，可以从载体上去除单独的模块化半导体器件，并且也可以从分割出的模块化半导体器件去除临时基底层。
可以理解，使用图7A至7F和图8A至8G所示的方法制成的模块化半导体器件可以与类似于图6G至图6I所示的步骤的基础半导体元件的基底组装，在此不再赘述。
本文的讨论包括许多说明性附图，这些说明性附图显示了半导体器件的各个部分及其制造方法。为了说明清楚起见，这些图并未显示每个示例组件的所有方面。本文提供的任何示例组件和/或方法可以与本文提供的任何或所有其他组件和/或方法共享任何或所有特征。
本文已经参照附图描述了各种实施例。然而，显然可以对其进行各种修改和改变，并且可以实施另外的实施例，而不背离如所附权利要求中阐述的本发明的更广泛范围。此外，通过考虑说明书和本文公开的本发明的一个或多个实施例的实践，其他实施例对于本领域技术人员将是明显的。因此，本申请和本文中的实施例旨在仅被认为是示例性的，本发明的真实范围和精神由所附示例性权利要求的列表指示。

Claims (19)

1.一种模块化半导体器件，其特征在于，所述模块化半导体器件包括：
密封剂层，所述密封剂层具有密封剂底面和密封剂顶面，其中所述密封剂层包括元件区和层间连接区；
半导体元件，所述半导体元件设置于所述元件区内，其中所述半导体元件包括暴露于所述密封剂底面的元件导电图案；
层间连接阵列，所述层间连接阵列设置于所述层间连接区内，其中所述层间连接阵列包括一个或多个导电通孔，每个所述导电通孔在所述密封剂底面和所述密封剂顶面之间延伸；以及
中介层，所述中介层层叠于所述密封剂层上，并具有中介层底面及中介层顶面，其中所述中介层顶面与所述密封剂底面接触；并且其中，所述中介层包括中介层导电图案和中介层互连结构，所述中介层导电图案位于所述中介层底面上，所述中介层互连结构电耦接到所述元件导电图案、所述中介层导电图案和所述一个或多个导电通孔。
2.根据权利要求1所述的模块化半导体器件，其特征在于，所述半导体元件包括半导体裸片或半导体封装件。
3.根据权利要求1所述的模块化半导体器件，其特征在于，所述导电通孔包括导电桩、导电柱或焊球。
4.根据权利要求1所述的模块化半导体器件，其特征在于，所述密封剂层的厚度等于所述半导体元件的厚度。
5.如权利要求1所述的模块化半导体器件，其特征在于，所述模块化半导体器件形成为单件形式。
6.一种电子器件，其特征在于，所述电子器件包括：
基底，所述基底包括基底互连结构；
基础半导体元件，所述基础半导体元件安装于所述基底上并电耦接到所述基底互连结构；
一个或多个基础通孔，所述一个或多个基础通孔安装于基底上并电耦接到所述基底互连结构；
第一模块化半导体器件，所述第一模块化半导体器件堆叠在所述基础半导体元件和所述一个或多个基础通孔上，其中所述第一模块化半导体器件包括：
密封剂层，所述密封剂层具有密封剂底面和密封剂顶面，其中所述密封剂层包括元件区和层间连接区；
半导体元件，所述半导体元件设置于所述元件区内，其中所述半导体元件包括暴露于所述密封剂底面的元件导电图案；
层间连接阵列，所述层间连接阵列设置于所述层间连接区内，其中所述层间连接阵列包括一个或多个导电通孔，每个所述导电通孔在所述密封剂底面和所述密封剂顶面之间延伸；以及
中介层，所述中介层层叠于所述密封剂层上，并具有中介层底面及中介层顶面，其中所述中介层顶面与所述密封剂底面接触；并且其中，所述中介层包括中介层导电图案和中介层互连结构，所述中介层导电图案位于所述中介层底面上，所述中介层互连结构电耦接到所述元件导电图案、所述中介层导电图案和所述一个或多个导电通孔，并且
其中所述中介层导电图案电耦接到所述一个或多个基础通孔。
7.根据权利要求6所述的电子器件，其特征在于，所述电子器件进一步包括一个或多个附加模块化半导体器件，所述一个或多个附加模块化半导体器件堆叠在所述第一模块化半导体器件上，其中所述一个或多个附加模块化半导体器件具有与所述第一模块化半导体器件的结构基本相同的结构，并且其中所述第一模块化半导体器件和所述一个或多个附加模块化半导体器件通过它们各自的导电通孔和中介层电耦接在一起。
8.根据权利要求6所述的电子器件，其特征在于，所述基础半导体元件不与所述第一模块化半导体器件完全重叠。
9.根据权利要求6所述的电子器件，其特征在于，所述一个或多个基础通孔的厚度等于所述基础半导体元件的厚度。
10.根据权利要求6所述的电子器件，其特征在于，其中所述第一模块化半导体器件的半导体元件包括半导体裸片或半导体封装件。
11.根据权利要求6所述的电子器件，其特征在于，所述导电通孔包括导电桩、导电柱或焊球。
12.根据权利要求6所述的电子器件，其特征在于，所述密封剂层的厚度等于所述半导体元件的厚度。
13.根据权利要求6所述的电子器件，其特征在于，所述模块化半导体器件形成为单件形式。
14.一种用于制造模块化半导体器件的方法，其特征在于，所述方法包括：
在载体上放置至少一个半导体元件和至少一个层间连接阵列，每个半导体元件位于至少一个半导体元件中一个半导体元件的旁边，其中所述至少一个半导体元件的每一个半导体元件包括朝向向上远离所述载体的元件导电图案，且所述层间连接阵列包括一个或多个导电通孔，其高度等于所述至少一个半导体元件的高度；
在所述载体上沉积密封剂材料以形成密封剂层，所述密封剂层密封所述至少一个半导体元件和所述至少一个层间连接阵列；
减薄所述密封剂层以暴露所述元件导电图案和所述至少一个层间连接阵列；
在所述密封剂层上层叠中介层，所述中介层包括至少一个中介层导电图案和至少一个中介层互连结构，所述至少一个中介层导电图案位于所述中介层的一个暴露的表面上，所述至少一个中介层互连结构电耦接到所述中介层导电图案、所述至少一个半导体元件的元件导电图案、以及所述层间连接阵列的一个或多个导电通孔。
15.根据权利要求14所述的方法，其特征在于，所述方法进一步包括：
将所述密封剂层和所述中介层分割成单独的模块化半导体器件，其中所述单独的模块化半导体器件的每个模块化半导体器件包括半导体元件和层间连接阵列。
16.根据权利要求14所述的方法，其特征在于，所述至少一个层间连接阵列形成为预制件。
17.根据权利要求14所述的方法，其特征在于，所述在载体上放置至少一个半导体元件和至少一个层间连接阵列的步骤包括：
在所述载体上附接胶带；
将所述至少一个半导体元件和所述至少一个层间连接阵列附接到所述胶带上。
18.根据权利要求17所述的方法，其特征在于，所述胶带是粘性胶带。
19.根据权利要求14所述的方法，其特征在于，所述在载体上放置至少一个半导体元件和至少一个层间连接阵列的步骤包括：
在所述载体上形成临时基底层；
在所述临时基底层上形成所述至少一个层间连接阵列；以及
将所述至少一个半导体元件附接到所述临时基底层上。
CN202210678569.8A 2022-06-15 2022-06-15 模块化半导体器件及包含该器件的电子器件 Pending CN117276260A (zh)

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