CN106672888B - 封装集成电路管芯的方法和器件 - Google Patents
封装集成电路管芯的方法和器件 Download PDFInfo
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Abstract
本发明涉及封装集成电路管芯的方法和器件。一种具有开口和穿衬底互连结构的封装衬底附接至临时载体(诸如粘附膜)。将IC管芯的有源表面与开口之内的载体衬底接触地放置,以暂时将该管芯附接至载体衬底。将另一管芯附接至离该载体衬底最远的第一管芯的一侧。根据实施例,使用环氧树脂使两个管芯彼此附接,使得它们各自的非有源表面彼此面对。在第二管芯的有源表面处的互连和封装衬底之间连接键合引线。然后封装该引线。在移除该载体衬底之后,形成累积互连结构,该累积互连结构包括封装衬底的外部互连(例如球栅阵列封装的焊球)。
Description
技术领域
本公开的实施例通常涉及电子器件,更具体地,涉及封装的电子器件以及制造封装的电子器件的方法。
背景技术
将多个微电子器件(诸如承载集成电路(IC)的半导体管芯、微电子机械系统(MEMS)、光学器件、无源电子部件等)组合到紧凑且结构坚固的单个封装中经常是有用的。常规上已经利用其中两个或更多微电子器件以并排或横向相邻的空间关系定位并且互连的所谓的二维(2D)或非堆叠的方案实施了微电子器件的封装。更具体地,对于IC形成于半导体管芯(IC管芯)上的情况,封装通常已需要将多IC管芯安装至封装衬底并且通过引线键合或倒装芯片(FC)连接形成所期望的电连接。之后通过将封装衬底安装至印刷电路板(PCB)或包括在电子系统内的其它部件,可以将该2D微电子封装并入到更大的电子系统中。
作为上述类型的2D封装技术的替代方案,最近已开发了三维(3D)封装技术,其中微电子器件以堆叠布置设置并且垂直地互连以得到堆叠的3D微电子封装。这种3D封装技术产生高度紧凑的很适合用在移动电话、数字照相机、数字音乐播放器以及其它小型电子设备内的微电子封装。此外,这种3D封装技术通过减小封装的微电子器件之间的互连长度并因此减小信号延迟而增强了器件性能。
扇出晶片级封装(FOWLP)封装使用用于封装互连的累积(build-up)处理。例如,标准的RCP流将IC管芯附接至晶片级衬底以使累积互连层可以形成在IC管芯的有源侧以提供外部互连。对于需要引线键合的3D结构(例如G单元(G-cell)器件)的情况,FOWLP不容易适应其它类型的互连结构(例如引线键合结构)的形成。
附图说明
图1例示了根据本公开的具体实施例的封装衬底的俯视图;
图2例示了在图1中标示的位置处的封装衬底的剖面图;
图3例示了根据本公开的具体实施例的附接至载体的图2的工件;
图4例示了根据本公开的具体实施例的具有附接至载体的管芯的图3的工件的俯视图;
图5例示了图4的工件的剖面图;
图6例示了根据本公开的具体实施例的具有第二管芯的图5的工件的剖面图;
图7例示了根据本公开的具体实施例的具有键合引线的图6的工件的剖面图;
图8例示了根据本公开的具体实施例的具有被覆盖的键合引线的图7的工件的剖面图;
图9例示了根据本公开的具体实施例的移除了载体之后的图8的工件的剖面图;
图10例示了根据本公开的具体实施例的具有覆盖主表面的图案化的介电层的图9的工件的剖面图;
图11例示了根据本公开的具体实施例的具有覆盖主表面的图案化的介电层的图9的工件的剖面图;
图12例示了根据本公开的具体实施例的具有导电通孔的图11的工件的剖面图;
图13例示了根据本公开的具体实施例的具有导电焊盘的图12的工件的剖面图;
图14例示了根据本公开的具体实施例的具有外部互连的图13的工件的剖面图;
图15例示了根据本公开的具体实施例的封装衬底的剖面图;
图16例示了根据本公开的具体实施例的封装衬底的俯视图;
图17例示了根据具有同一级处的多个管芯的本公开的具体实施例的工件剖面图;
图18例示了根据包括同一级处的多个管芯的本公开的具体实施例的工件剖面图;
图19例示了根据包括堆叠管芯的本公开的具体实施例的工件剖面图;以及
图20例示了具有多个根据本公开的具体实施例的封装衬底的板。
具体实施方式
根据本公开的实施例,具有开口和穿衬底互连结构的衬底附接至临时载体(诸如粘附膜)。与开口内的载体衬底接触地放置IC管芯的有源表面,以将IC管芯暂时附接至该载体衬底。此IC管芯可以称作该封装的背侧管芯。将另一IC管芯附接至背侧管芯的离该载体衬底最远的一侧。因为该IC管芯将会比该背侧管芯离完成的封装的外部互连更远,因此该IC管芯可以称作顶侧管芯。根据实施例,使用环氧树脂将两个IC管芯相互附接使得它们各自的非有源表面相互面对。在第二IC管芯的有源表面和该封装衬底之间形成键合引线。然后将该键合引线包封。在移除了载体衬底之后,在包括封装衬底的外部互连的封装衬底和管芯的背侧处形成累积互连堆叠(诸如球栅阵列封装的焊球)。参照附图将会更好地理解本公开的各个实施例。请注意,各图的不能从图的具体视图直接可见的特征件以虚线例示,除非另有说明。
图1例示了衬底10的第一主表面的俯视图。图2例示了在图1中标示的位置处的衬底10的剖面图。衬底10包括作为电绝缘物的基体材料12和多个导电互连20。衬底10的上主表面和下主表面由该基体材料12界定并暴露该导电互连的部分(被称作衬底的外部互连)。请注意,除非另有说明,关于具体特征件的术语“上”和“下”指的是该具体特征件第一次被例示的附图所例示的该特征件的方向。由衬底10的内部区域所界定的开口13穿过该衬底10地延伸。衬底10可以是基于有机或陶瓷衬底(例如印刷电路板(PCB)等)的叠层或累积层,。
多个导电互连20包括具体的互连14和15。多个互连20的每个导电互连包括界定在上主表面处的上外部互连的部分、界定在下主表面处的下外部互连的部分以及连接该上外部互连部分和下外部互连部分的穿衬底互连部分。例如在图2处,例示了互连14和互连15的每一个包括上外部互连16、穿衬底互连18以及下外部互连17。穿衬底互连被例示为穿孔通孔(Through-Hole-Vias)(THV)。然而,正如将下文更详细地说明的,应理解,穿衬底互连还可以是穿过衬底的一个或多个路由层(routing layer)的路由的互连。
如本文所使用的,关于具体结构所使用的术语“外部互连”意指涉及该具体结构的提供导电接口的部分,通过该导电接口信号可以在该具体结构和其它结构之间传输。例如,互连14的外部互连16是互连14的随后提供的导电结构将与其接触的部分。通过示例的方式,上外部互连16被假定为键合焊盘,经由随后附接的键合引线,信号可以通过该键合焊盘传送至该衬底10以及从该衬底10传出。
在图3处例示了工件,其中图3例示了在衬底10的下主表面处附接至载体衬底30之后的衬底10。随后将移除该载体衬底30,因此该载体衬底30是临时衬底。该载体衬底30可以是粘合带、在刚性载体之上的双面粘合带等。在实施例中,载体衬底30完全覆盖开口13和整个衬底。在其它实施例中,该载体衬底可以仅覆盖开口13的一部分。
图4和图5分别是工件400的俯视图和剖面图。工件400包括已放置在开口13之内的具有上主表面和下主表面的IC管芯40。如本文所使用的,关于物体相对于开口的位置所使用的术语“在......之内”意指从俯视图来看该物体不延伸到该开口的边界之外。IC管芯40的下主表面包括多个外部互连41,该多个外部互连41包括被称作管芯焊盘的外部互连45和46,其本身可以是键合焊盘。IC管芯40的下主表面已附接至在开口13之内的暴露位置处的载体衬底30。该下主表面是IC管芯40的有源表面,其中术语“有源表面”意指IC管芯的已形成电子部件49的一侧。电子部件49可以是诸如晶体管或二极管的有源半导体部件;或者诸如电阻器或电容器的无源器件。在例示的实施例中,该IC管芯40具有一个有源表面(即其下主表面),并且没有穿衬底互连,虽然这不是必要的。
图6是工件600的剖面图,该工件600包括具有上主表面和下主表面的IC管芯60。在例示的实施例中,IC管芯60的上主表面是有源表面并且包括可以连接至电子部件(未示出)的外部互连62和63,而下主表面是无源表面。通过附接结构53,该IC管芯60已附接至IC管芯40使得管芯40的无源表面面对管芯60的无源表面。该附接结构53可以是环氧树脂、管芯附接膜等。在例示的实施例中,将IC管芯40的上主表面和次表面(minor surface)包封在填充材料中,该填充材料的一部分作为附接结构53。例如,封装填充材料包括IC管芯40左侧的部分52、IC管芯40右侧的填充部分51以及在IC管芯40之上的填充部分53,该填充部分53也称作附接结构53。该填充材料可以是在同一沉积处理期间沉积的环氧树脂;其中,通过将IC管芯60的下主表面与该环氧树脂接触地放置,IC管芯60附接至IC管芯40。在另一实施例中,附接结构53可以是被放置为与IC管芯60的下主表面接触的管芯附接膜;并且然后通过在IC管芯40的上主表面之上放置管芯附接膜,将该IC管芯60/管芯附接膜组合附接至IC管芯40。应理解,在替代方案中,该管芯附接膜可以首先与IC管芯40接触地放置。
图7是在通过引线键合处理已将键合引线(wirebond)65连接至衬底10的互连14的外部互连16和IC管芯60的外部互连63,并且也已将键合引线64连接至衬底10的互连15的外部互连16和IC管芯60的外部互连62之后的工件700的剖面图。
图8是包括键合引线63和65的衬底10的上主表面已被覆盖之后的工件800的剖面图。可以通过模塑料(molding compound)包封该表面以产生界定封装器件的外部的结构71,或者可被附接的具有空隙的盖。该覆盖物可以覆盖该器件的次表面,或者不覆盖该器件的次表面。该模塑料可以包括诸如硅石填料、树脂等的材料。
图9是在工件800已被翻转并且载体衬底30已被移除以暴露IC管芯40的有源表面之后的工件900的剖面图。注意到,在下面的讨论中保持原来提及的各表面的方向。
图10至14例示了为了形成包括完成的封装的外部互连的互连的累积处理的具体实施例。图10是在之前的工件表面处形成层81之后的工件1000的剖面图。层81是位于衬底10的下表面和IC管芯40之上的具体层级处的绝缘层。因而,层81覆盖于衬底10的两个外部互连17以及IC管芯40的外部互连45和46之上。可以通过用环氧树脂、聚酰亚胺、苯并环丁烯(BCB)旋涂,用干膜材料的层压处理等形成层81。
图11是已使用常规技术或专有技术(诸如光刻、激光烧蚀等)图案化层81以形成暴露衬底10和IC管芯40处的外部互连的开口83之后的工件1100的剖面图。
图12是在每个开口83中形成导电触点93之后工件1200的剖面图,该导电触点93还称作通孔。该触点93可以使用常规技术或专有技术形成,并且可以包括金属和位于该金属和其它特征件之间的阻挡层等。
图13是形成导电结构94(例如RDL(再分配层))之后的工件1300的剖面图,随后将会在导电结构94处形成封装的外部互连。根据实施例,导电结构94可以包括金属、导电环氧树脂材料等;并且可以通过电镀、印刷、处置(disposing)处理等形成。根据所使用的具体处理可以包括阻挡层。RDL处理可以包括溅射的阻挡层、光刻、电镀和蚀刻处理。RDL金属可以是Cu、Cu合金、Ti或其它材料。阻挡层可以是Ti、TiW或其它金属材料。如果需要,可以通过重复的绝缘层和RDL处理来包括额外的RDL。应理解,还可以在同一处理(诸如电镀处理)期间形成导电层间触点93以及导电结构94。
图14是在导电结构94处形成外部互连114-117之后的工件1400的剖面图。外部互连114-117可以是导电球,该导电球通过使用焊接处理穿过图案化的绝缘层82中的开口附接导电结构94、通过在该开口处沉积一个或多个导电层等形成。
在之前的附图中,已参照本发明的实施例的具体示例说明了各种实施例。然而,清晰的是,在不脱离如在所附权利要求中所记载的本发明更广泛的精神和范围的情况下,可以对其作出各种变型和改变。下面的附图例示了各种额外的实施例。
在之前的附图中的该穿衬底互连20已经被例示为从主表面至主表面的垂直互连的TSV。图15例示了具有穿衬底互连1514(TSV)和穿衬底互连1515的衬底1500的替换实施例,由于在穿过衬底1500的层1592处的绝缘层处具有水平路由,该穿衬底互连1515被称作“路由的穿衬底互连”并分别通过穿过层1591和1593处的绝缘物的分开的通孔连接至外部互连1516和1517。层1591-1593的每一个可以称作通孔层,层1591-1593是通孔主要穿透的绝缘层。层1592可以称作路由层,层1592是绝缘层,穿过该绝缘层形成垂直于通孔的导电路径。因而,导电路径形成在外部互连1516和1517之间。尽管衬底1500被示出为具有单个路由层,在其它实施例中,可以使用多路由层。
衬底的具体实施例可以仅具有穿衬底互连,例如前面已例示的。在替换实施例中,该衬底还可以包括在衬底同一主表面处的两个外部互连之间提供导电路径的衬底互连。例如,参照作为衬底1600的俯视图的图16,互连1610在衬底的上表面处具有由代表外部互连的实线所标示的两个外部互连1611和1612、由互连1611和1612内的虚线圆所代表的两个通孔以及由虚线1613所代表的水平互连。图16还例示了衬底1600的互连1620,该互连1620具有在衬底的下表面处的由代表外部互连的实线所标示的两个外部互连1621和1622、由互连1621和1622的虚线圆所代表的两个通孔以及由虚线1623所代表的水平互连。
出于例示离封装的外部互连1715最近的管芯级处的多IC管芯的使用的目的,图17例示了仅包括封装器件的相关部分1700的简化图。因而,代替如图5所说明的单个IC管芯与载体接触地放置的情况,多个IC管芯1740和1770与载体接触地放置。随后附接IC管芯1760,形成键合引线1764,并形成包括外部互连1715的累积层。还例示了类似于图6的填充材料52的填充材料1752。
出于例示离封装的外部互连1815最远的管芯级处的多IC管芯的使用的目的,图18例示了仅包括封装器件的相关部分1800的简化图。因而,代替如图6所说明的单个IC管芯附接至IC管芯1840的情况,多个IC管芯1860和1870附接至IC管芯1840。形成键合引线1864,并形成包括外部互连1815的累积层。还例示了类似于图6的填充材料52的填充材料1852。
图19例示了具体实施例1900,其中提供堆叠管芯模块(诸如可以检测加速度的G单元)并将堆叠管芯模块附接至与(图5的)载体接触的IC管芯1940。具体的堆叠IC管芯模块1970包括基部IC管芯1960、覆盖的IC管芯1972以及覆盖IC管芯1972的部分之上的盖1973。在例示的实施例中,IC管芯1960和IC管芯1972二者的上主表面都是具有引线键合至衬底1912并与其各自的IC管芯的电子部件(未示出)电连接的外部互连的有源表面。
在一个实施例中,管芯模块1970是被放置在开口中之前通过晶片级处理形成的管芯堆叠。例如,在晶片级处理期间,盖1973可以例如在从晶片切单管芯1972之前附接至管芯1972,并且可以密封地或者以其它方式附接。在切单之后,可以包括诸如MEMS(微电子机械系统)器件(例如可以用于检测加速度)的有盖的管芯1972/1973可以附接至专用的管芯1960,当专用的管芯1960与有盖的管芯1972/1973电接合时实现支持特定的一组特征件(诸如加速计)的以MEMS为基础的器件。
应理解,当提供管芯堆叠以放置到本封装中时,在管芯1960和管芯1972之间的物理连接通常会与管芯1940和1960之间的物理连接的类型不同。根据实施例,通过晶片级处理所处理的管芯模块可以具有厚度范围在2-10微米的介于管芯盖1973和管芯1972之间的键合接口以及介于管芯1972和1960之间的键合接口,而介于管芯1940和管芯1960之间的键合接口的厚度则会厚很多。例如,介于1940和1960之间的键合接口的厚度可以在10至25微米的范围中。因而,两个厚度的比例可以在2∶1至10∶1的范围中。此外,可以使用不同的材料以及可以使用导致不同物理特性的不同处理来分别附接两个管芯组。在替换实施例中,可以与专用的管芯1960分开地提供有盖的管芯1972/1973并反而将有盖的管芯1972/1973作为所公开的封装处理的一部分附接至管芯1960。因而在将管芯堆叠1960附接至管芯1940之后,将管芯堆叠1972/1973附接至管芯1960。可替换地,有盖的管芯1972/1973可以附接至管芯1940(例如不使用管芯1960),以电连接至具有其专用的管芯的MEMS单元,因而使用本技术制造封装的G单元器件。
在可替换实施例中,在将管芯附接至衬底1912的键合处理期间,可以在管芯1972和管芯1960的有源表面之间连接键合引线。
在前面的说明书中,已参照本发明实施例的具体实例描述了本发明。然而,清晰的是,在不脱离如在所附权利要求中所记载的本发明更广泛的精神和范围的情况下,可以对其作出各种变型和改变,并且权利要求不限于所说明的具体实例。
可以使用各种不同电路部件来实现可应用的一些上述实施例。例如,给出的图中的示例性布局和对其的说明仅仅是为了提供在讨论本发明的各个方面时的有用的参照。当然,出于讨论的目的已简化了对该布局的说明,并且所说明的布局只是根据本发明可以使用的很多不同类型的合适的布局中的一个。因此,例如,应理解本文例示的各种管芯可以具有不同厚度。
例如,代替单独处理衬底的情况,可以按板级制造封装,如图20所例示的。图20是示出了多个封装在彼此被切单之前在板的衬底位置2011-2014处组装的剖面图。应理解,图20类似于与参照图7所说明的处理位置相同的处理位置。在完成处理之后,衬底位置2011-2014将会沿着虚线2001-2003彼此切单以形成单个封装。由于切单处理,此处理留下沿着最终封装的次表面暴露的衬底2000的一部分。
本领域技术人员应理解,为了简洁和清晰地例示图中的元件并且不必按比例绘制图中的元件。例如,所选元件仅用于帮助提高对本发明的各个实施例中的这些元件的功能和布置的理解。还有,为了使本发明的这些各种实施例不那么抽象,在商业可行的实施例中有用的或必需的通用且熟知的元件大部分未被描述。还应理解,所说明的方法中的某些动作和/或步骤可以按照特定的发生顺序说明或描述,而本领域技术人员应理解,这种有关顺序的特定性实际上是不必要的。还应理解,除了本文另有说明的具体含义之外,本说明书中所使用的术语和表达具有与这种术语和表达式在它们相应的各自领域的调查和研究中的含义一致的通常含义。
Claims (8)
1.一种形成集成电路封装的方法,包括:
将衬底的第一主表面附接至载体,该衬底具有第一主表面、第二主表面、介于该第一主表面和该第二主表面之间的介电层、界定第一开口的第一区域、以及第一互连,其中该第一互连具有该第一主表面处的第一外部部分、该第二主表面处的第二外部部分以及将该第一外部部分电连接至该第二外部部分的穿过该介电层的部分,其中该载体的暴露部分暴露在该第一开口之内;
将第一IC管芯的第一主表面附接至该载体的暴露部分,该第一IC管芯具有第一主表面、第二主表面以及包括该第一主表面处的外部部分和连接至该第一IC管芯的电子部件的内部部分的互连;以及其中第一IC管芯的第一主表面与衬底的第一主表面共面;
将第二IC管芯固定至该第一IC管芯,其中该第一IC管芯的第二主表面面对该第二IC管芯的第二主表面,该第二IC管芯具有第一主表面、第二主表面和包括电连接至该第二IC管芯的电子部件的第一主表面处的外部部分的互连,以及其中第二IC管芯的第一主表面和衬底的第二主表面不共面;
将第一引线连接至该第二IC管芯的互连的外部部分并且连接至该衬底的第一互连的第二外部部分;
用模塑料包封该引线、第二IC管芯的第一主表面、以及衬底的第二主表面;
从该衬底的第一主表面移除该载体,其中在移除该载体时该第一IC管芯的第一主表面与该衬底的第一主表面共面;
在该衬底的该第一主表面处形成第二介电层;
穿过该第二介电层形成第一互连,该第一互连电连接至该衬底的第一互连的第一外部部分;
形成电连接至穿过该第二介电层的该第一互连的IC封装的第一外部互连;
穿过第二介电层形成第二互连,该第二互连电连接至该第一IC管芯的互连的外部部分;以及
形成电连接至穿过该第二介电层的该第二互连的IC封装的第二外部互连。
2.如权利要求1所述的方法,还包括:
将第三IC管芯的第一主表面附接至该载体的暴露部分,该第三IC管芯具有第一主表面、第二主表面和包括该第一主表面处的外部部分和连接至该第三IC管芯的电子部件的内部部分的互连。
3.一种封装,包括:
多个外部互连,位于该封装的第一主表面处;
第一衬底,具有第一主表面、第二主表面,该第一主表面具有第一外部互连,该第二主表面具有通过穿过该第一衬底的绝缘层的第一导电路径电连接至该第一外部互连的第二外部互连,第一衬底的区域界定穿过该衬底的开口;
第一管芯,位于开口之内,具有与该第一衬底的第一主表面共面的第一主表面,所述第一管芯包括在其第一主表面的外部互连、电连接至该外部互连的内部电路系统;
累积互连堆叠,包括穿过路由层并穿过介电层/通孔层的第一导电路径和第二导电路径,该第一导电路径电连接至该第一管芯的外部互连并且电连接至该封装的第一外部互连,该第二导电路径电连接至该衬底的第一外部互连并且电连接至该封装的第二外部互连;
第二管芯,具有第一主表面、第二主表面和接近于第一主表面的半导体部件,该第二主表面面对该第一管芯的第二主表面,该第一主表面具有电连接至该第二管芯的半导体部件的外部互连;其中第二管芯的第一主表面和衬底的第二主表面不共面;
第一引线,连接至该第二管芯的外部互连,并且连接至该衬底的第二外部互连;以及
模塑料,覆盖第一引线、第二管芯的第一主表面、以及第一衬底的第二主表面。
4.如权利要求3所述的封装,还包括:
第三有盖的管芯,具有第一主表面、第二主表面和接近于该第一主表面的有源半导体部件,该第二主表面面对该第二管芯的第一主表面,该第一主表面具有电连接至该有源半导体部件的外部互连;
该第一衬底的第一主表面还包括第三外部互连;该第一衬底的第二主表面还包括通过穿过该第一衬底的绝缘层的第二导电路径电连接至该第三外部互连的第四外部互连;
该累积互连堆叠还包括穿过该路由层和介电层/通孔层的第三导电路径,该第三导电路径电连接至该第一衬底的第三外部互连并且电连接至该封装的第三外部互连;以及
第二引线,连接至该第三有盖的管芯的外部互连,并且连接至该衬底的第四外部互连。
5.如权利要求3所述的封装,还包括:
第三管芯,具有与该第一衬底的第一主表面共面的第一主表面,所述第三管芯包括外部互连和接近于该第一主表面并且电连接至该外部互连的有源半导体部件;并且
该累积互连堆叠还包括穿过该路由层和介电层/通孔层的第三导电路径,该第三导电路径电连接至该第三管芯的外部互连并且电连接至该封装的第三外部互连。
6.如权利要求3所述的封装,还包括:
第三管芯,具有与该第二管芯的第一主表面共面的第一主表面、第二主表面以及接近于第一主表面的有源半导体部件,该第二主表面面对该第一管芯的第二主表面,该第一主表面具有电连接至该有源半导体部件的外部互连;
该第一衬底的第一主表面还包括第三外部互连,该第一衬底的第二主表面还包括通过穿过该第一衬底的绝缘层的第二导电路径电连接至该第三外部互连的第四外部互连;
该累积互连堆叠还包括穿过该路由层和电介质/通孔层的第三导电路径,该第三导电路径电连接至该第三管芯的外部互连并且电连接至该封装的第三外部互连;以及
第二引线,连接至该第三管芯的外部互连,并且连接至该衬底的第四外部互连。
7.如权利要求3所述的封装,其中该衬底的第一主表面的所有外部互连都通过通孔电连接至该衬底的第二主表面的外部互连。
8.如权利要求3所述的封装,其中该衬底的第一主表面的外部互连中的至少一些通过第一层级的路由层和两个通孔电连接至第二主表面的外部互连。
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