CN104600040A - 包括设置有集成电路芯片的堆叠的电子器件的电子系统 - Google Patents

包括设置有集成电路芯片的堆叠的电子器件的电子系统 Download PDF

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CN104600040A
CN104600040A CN201410547304.XA CN201410547304A CN104600040A CN 104600040 A CN104600040 A CN 104600040A CN 201410547304 A CN201410547304 A CN 201410547304A CN 104600040 A CN104600040 A CN 104600040A
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electronic device
metallic plate
chip
integrated circuit
electric contact
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CN104600040B (zh
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J-M·里维埃
N·马丁
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STMicroelectronics International NV
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STMicroelectronics Grenoble 2 SAS
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Abstract

本公开涉及包括设置有集成电路芯片的堆叠的电子器件的电子系统,该电子系统包括第一电子器件(具有第一集成电路芯片)和第二电子器件(具有第二集成电路芯片)。第二电子器件在与第一集成电路芯片相同侧上被堆叠在第一电子器件上方。位于第一集成电路芯片周围的电连接元件将第二电子器件电连接到第一电子器件。被配置用于热量捕获和转移的金属板在第一电子器件和第二电子器件之间延伸。金属板包括经对准以允许电连接元件以一定距离通过的通道。

Description

包括设置有集成电路芯片的堆叠的电子器件的电子系统
优先权要求
本申请要求于2013年10月30日提交的第1360584号法国专利申请的优先权,其公开内容通过引用并入本文。
技术领域
本发明涉及微电子领域。
背景技术
构造包括彼此堆叠并且彼此电连接的电子器件的电子系统是众所周知的,每个电子器件包括至少一个集成电路芯片。
电子器件的堆叠尤其具有改进电连接的性能以及减小尺寸的优点。然而在一些情况下,出现了一些集成电路芯片产生热量,而且产生的热量会加热其它集成电路芯片并且随后退化其它集成电路芯片的性能的问题。这尤其是当第一电子器件包括产生热量的处理器芯片并且堆叠在第一电子器件上的第二电子器件包括存储器芯片的情况,该存储器芯片的功能尤其在其温度升高时退化。
以上描述的情形构成了提高电子系统的性能(尤其是程序执行速率)的障碍。然而,目前存在于在电子系统的期望性能和其尺寸之间采取折中的情况并不令人满意,尤其在诸如移动电话之类的便携式设备的领域。
发明内容
一个实施例提供了一种电子系统,该电子系统包括:第一电子器件,该第一电子器件包括至少一个第一集成电路芯片;以及第二电子器件,该第二电子器件包括至少一个第二集成电路芯片,在与第一芯片相同侧上被堆叠在第一电子器件上方,并且通过位于第一芯片周围的电连接元件连接到第一电子器件。
提出了第一电子器件应当配备有用于热量捕获和转移的金属板,金属板在第一芯片上方在第一电子器件和第二电子器件之间延伸,并且具有被布置用于电连接元件以一定距离通过的通道。
该金属板可以距第二电子器件一定距离延伸。
该金属板可以在第一电子器件上方与其接触。
导热胶层可以被插入在金属板和第一电子器件之间。
导热胶层可以被插入在金属板和第一芯片之间。
第一电子器件可以通过电连接元件被安装在印刷电路板上,并且金属板可以具有在该印刷电路板上方与其接触的外侧部分。
盖可以包围第二电子器件并且可以具有在金属板的外侧部分上方的边缘。
该外侧部分可以包括外围条带。
该外侧部分可以包括突出部。
该盖可以具有通风孔。
散热器可以被安装在金属盖上方。
附图说明
根据本发明的具体实施例的电子系统将通过由附图图示出的非限制性示例来描述,其中:
图1呈现了电子器件的截面;
图2A和2B呈现了图1的电子器件的金属板的顶视图;
图3呈现了另一电子器件的截面;
图4呈现了另一电子器件的截面;
图5A、图5B和图5C呈现了图4的电子器件的金属板的顶视图;
图6呈现了另一电子器件的截面;以及
图7呈现了另一电子器件的截面。
具体实施方式
如图1所示,电子系统1包括彼此堆叠并且彼此相距一定距离的第一电子器件2和第二电子器件3。
电子器件2包括设置有集成电连接网距络5的衬底晶片4,集成电连接网络5包括:在一个面4a上被布置在其中心部分上的电连接焊盘6a和被布置在其外围部分上的电连接焊盘6b,以及在其相对的面4b上的电连接焊盘7。
电子器件2包括在衬底晶片4的面4a上通过电连接元件9安装在衬底晶片4上的至少一个集成电路芯片8,电连接元件9被插入在芯片8的电连接焊盘与电连接网络5的电连接焊盘6a之间。
电子器件3包括设置有集成电连接网络11的衬底晶片10,集成电连接网络11包括:在一个面10a上被布置在其外围部分上的电连接焊盘12,以及在其相对的面10b上被布置在其外围部分上的电连接焊盘13。
电子器件3包括至少一个集成电路芯片14,至少一个集成电路芯片14通过粘接层15被安装在其面10a上方并且通过电连接线16电连接到电连接网络11的焊盘12,芯片14和电连接线被嵌入到绝缘材料层17中。根据备选实施例,芯片14可以通过电连接元件被安装在衬底晶片10上。
电子器件3通过电连接元件18(诸如金属珠)被安装在电子器件2上,电连接元件18被插入在电子器件2的电连接网络5的电连接焊盘6b和电子器件3的电连接网络11的电连接焊盘13之间。
因此,衬底晶片10的面10b面向芯片8和衬底晶片4的面4a并且与它们相距一定距离,电连接元件18位于芯片8周围,并且衬底晶片10在芯片8和芯片14之间延伸。
电子系统1可以通过电连接元件20(诸如金属珠)被安装在印刷电路板19上,电连接元件20被插入在衬底晶片4的电连接网络5的电连接焊盘7和印刷电路板19的电连接焊盘19a之间。
根据一个实施例,芯片8可以是处理器芯片,处理器芯片的操作会引起产生热量,芯片14可以是存储器芯片,如果其温度变得太高,则其操作容易退化。
电子器件2配备有用于捕获和转移热量的金属板21,例如由铜或铝制成,金属板21在第一电子器件2和第二电子器件3之间延伸,优选地不与第二电子器件接触,以便至少部分地把由芯片8产生的热量转移到衬底晶片4和/或印刷电路板19。
金属板21包括中心部分22,中心部分22在第一电子器件2的芯片8和第二电子器件3的衬底晶片10之间平坦延伸。
金属板21还包括外围部分23,外围部分23至少部分包围中心部分22,并且外围部分23在第一电子器件2的位于芯片8周围的部分上方平坦延伸并且具有通道24,连接第一电子器件2和第二电子器件3的电连接元件18穿过通道24但不与其接触或相距一定距离。
根据图1所示的实施例,金属板21为盘形,芯片8位于其中。其中心部分22通过导热胶层25被安装在芯片8的与衬底晶片4和电连接元件9不同侧的面8a上。其外围部分23通过导热胶层26被安装在衬底晶片4的面4a上,该外围部分23的外围边沿大致沿着衬底晶片4的外围边缘延伸。
因此,由芯片8产生的热量优先扩散进入衬底晶片4和其电连接网络5,对于面向衬底晶片4的面,热量直接扩散,而对于背对衬底晶片4的面,热量通过金属板21间接扩散,金属板21构成了第一电子器件2和第二电子器件3之间的热屏障,以及热量从芯片8的面8a转移到衬底晶片4的优先手段。
具体地并且优选地,衬底晶片4的热量随即通过电连接元件20转移到印刷电路板19。
结果是第二电子器件3的芯片14被保护以免其温度的任何过度上升。
根据如图2A所示的备选实施例,通道24具有大开口24a,每个开口24a用于使多个电连接元件18通过。
根据如图2B所示的另一备选实施例,通道24具有个体开口24b,每个个体开口24b用于使单个电连接元件18通过。
根据图3,其图示了另一电子系统1A,其中第一电子器件2还包括封装材料,该封装材料形成了被布置在芯片8周围且在衬底晶片4的面10b上的模块27。用于电连接元件18的路径和布置的开口28被布置在封装模块27中。
根据该示例,金属板21被平坦的金属传热板29替代,金属传热板2在芯片8和封装模块27上方延伸并且通过导热胶层30被安装在其上,金属板29具有像金属板21一样的通道31以用于位于开口28上方的电连接元件18通过。
根据图4,其图示了另一导电系统1B,其中尤其如图1所示的第一电子器件2配备有金属传热板32,金属传热板32包括图1的金属板21和并且包括外侧部分33,外侧部分33延伸了金属板21的外围部分23并且具有在印刷电路板19上方变平坦的端部部分34,在第二电子器件2周围并且与其相距一定距离。
外侧部分33可以通过加固部件35和/或通过导热胶层36平坦安装在印刷电路板19上方。
因此,来自芯片8并且被金属板32捕获的热量可以至少部分地通过其外侧部分33直接被转移到印刷电路板19。
如图5A所示,金属板32的外侧部分33可以包括包围外围部分23的外围条带33a。
如图5B所示,金属板32的外侧部分33可以包括多个突出部33b,多个突出部33b被间隔开、延伸了外围部分23并且被设置为例如从外围部分23的角部开始。
如图5C所示,金属板32可以只包括金属板21的中心部分22和突出部33c,突出部33c被间隔开、延伸了中心部分22的角部、并且从电子器件2和3的角部上方通过并且距其一定距离。在这种情况下,用于电连接元件18通过的通道可以由分别被布置在间隔的突出部33c之间的凹陷部37构成。
根据备选实施例,金属板可以包括如图3所示的金属板29来代替如图1所示的金属板21。
根据图6,图示了另一电子系统1C,其中图4所示的电子系统1B被进一步配备有金属盖38,金属盖38包围第二电子器件3,至少和芯片14相距一定距离,并且金属盖38具有到达金属板32的被安装在印刷电路板19上的外侧部分34上方的端部边缘39。边缘39可以通过加固部件35和/或粘接层40来进行固定。
另外,金属盖38具有通风孔41并且可以设置有外部散热器42,外部散热器42被固定其位于芯片14上方并且与其相距一定距离的部分上。
根据图7,图示了另一电子系统1D,其中图3所示的电子系统1A被进一步被配备有金属盖43,金属盖43以一定距离包围第二电子器件3,金属盖43具有到达金属板29的突出的外围部分45上方的端部边缘44。端部边缘44和该突出的外围部分45可以通过加固部件和/或粘接层来固定。
金属盖43也具有通风孔46,并且可以设置有外部散热器47,外部散热器47被固定其位于芯片14上方并且与其相距一定距离的部分上。
因此,金属盖38和43以及散热器41和47可以帮助将由芯片8产生的热量消散到环境空气中,为了保护芯片14免受温度过度上升。
本发明不限于上面描述的示例。特别地,用于热量捕获和转移的金属板可以有非常不同的形状。在不背离本发明的范围的情况下,多个其它备选实施例也是可能的。

Claims (20)

1.一种电子系统,包括:
第一电子器件,包括至少一个第一集成电路芯片,
第二电子器件,包括至少一个第二集成电路芯片,
其中所述第二电子器件在与所述第一芯片相同侧上被堆叠在所述第一电子器件上方,并且通过位于所述第一芯片周围的电连接元件被连接到所述第一电子器件,
其中所述第一电子器件还包括被配置用于热量捕获和转移的金属板,所述金属板在所述第一芯片上方的位置处在所述第一电子器件和所述第二电子器件之间延伸,所述金属板具有被布置用于允许所述电连接元件以一定距离通过所述金属板的通道。
2.根据权利要求1所述的系统,其中所述金属板与所述第二电子器件分离地延伸。
3.根据权利要求1所述的系统,其中所述金属板在所述第一电子器件上方与其接触。
4.根据权利要求1所述的系统,其中导热胶层被插入在所述金属板和所述第一电子器件之间。
5.根据权利要求1所述的系统,其中导热胶层被插入在所述金属板和所述第一集成电路芯片之间。
6.根据权利要求1所述的系统,其中所述第一电子器件被配置为通过电连接元件被安装在印刷电路板上,以及其中所述金属板具有外侧部分,所述外侧部分被配置为与所述印刷电路板发生接触。
7.根据权利要求1所述的系统,还包括盖,所述盖被配置为包围所述第二电子器件并且具有位于所述金属板的外侧部分上方的边缘。
8.根据权利要求7所述的系统,其中所述外侧部分包括外围条带。
9.根据权利要求7所述的系统,其中所述外侧部分包括突出部。
10.根据权利要求7所述的系统,其中所述盖具有通风孔。
11.根据权利要求7所述的系统,还包括被安装在所述金属盖上方的散热器。
12.一种电子系统,包括:
第一电子器件,包括:
第一集成电路芯片,具有包括第一电触点的正面;
第一衬底,具有包括第二电触点和第三电触点的正面;
其中所述第一集成电路芯片的正面面对所述第一衬底的正面,并且所述第一电触点被电连接到所述第二电触点;
被配置用于热量捕获和转移的金属板,所述金属板包括与所述第一集成电路芯片的背面接触的中心区域以及包括与所述第一衬底的所述第三电触点对准的开口的外围区域;
第二电子器件,包括第二衬底,所述第二衬底具有包括第四电触点的背面;以及
电连接件,其延伸穿过所述金属板中的所述开口并且将所述第四电触点电连接到所述第三电触点。
13.根据权利要求12所述的系统,其中所述第二电子器件包括第二集成电路芯片,所述第二集成电路芯片被安装至所述第二衬底的正面并且与所述第四电触点电连接。
14.根据权利要求12所述的系统,其中所述第一衬底的背面被配置为被安装至接线板,并且其中所述金属板的所述外围区域延伸越过第一衬底的周界并且被配置用于附接至所述接线板的正面。
15.根据权利要求12所述的系统,其中所述金属板的所述外围区域中的所述开口包括多个开口,所述多个开口中的每个开口对应于所述第三电触点中的单个第三电触点。
16.根据权利要求12所述的系统,其中所述金属板的所述外围区域中的所述开口包括多个开口,所述多个开口中的每个开口对应于多个所述第三电触点。
17.根据权利要求12所述的系统,还包括包围至少所述第二电子器件的盖。
18.根据权利要求17所述的系统,其中所述盖被安装到所述金属板的所述外围部分。
19.根据权利要求17所述的系统,其中所述盖包括通风孔。
20.根据权利要求17所述的系统,还包括被安装到所述盖的散热结构。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106672888A (zh) * 2015-11-11 2017-05-17 飞思卡尔半导体公司 封装集成电路管芯的方法和器件
CN110364518A (zh) * 2018-04-11 2019-10-22 意法半导体(格勒诺布尔2)公司 包括电子芯片的电子设备

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9673175B1 (en) * 2015-08-25 2017-06-06 Freescale Semiconductor,Inc. Heat spreader for package-on-package (PoP) type packages
US10297541B2 (en) 2016-11-18 2019-05-21 Intel Corporation Multiple-component substrate for a microelectronic device
US10497687B2 (en) * 2016-12-31 2019-12-03 Intel Corporation Configurable semiconductor package
FR3061600B1 (fr) * 2017-01-03 2020-06-26 Stmicroelectronics (Grenoble 2) Sas Dispositif electronique comprenant une puce rainuree
US20190206839A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Electronic device package
US20210066155A1 (en) * 2019-08-30 2021-03-04 Intel Corporation Microelectronics package comprising a package-on-package (pop) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone
JP7280208B2 (ja) 2020-01-22 2023-05-23 日立Astemo株式会社 電子制御装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6212074B1 (en) * 2000-01-31 2001-04-03 Sun Microsystems, Inc. Apparatus for dissipating heat from a circuit board having a multilevel surface
US20030128523A1 (en) * 1998-06-30 2003-07-10 Moden Walter L. Heat sink with alignment and retaining features
US7781883B2 (en) * 2008-08-19 2010-08-24 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
CN102610594A (zh) * 2010-11-22 2012-07-25 钰桥半导体股份有限公司 具有散热座及增层电路的堆栈式半导体组体
WO2013089780A1 (en) * 2011-12-16 2013-06-20 Intel Corporation Package for a microelectronic die, microelectronic assembly containing same, microelectronic system, and method of reducing die stress in a microelectronic package

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW479339B (en) * 2001-03-01 2002-03-11 Advanced Semiconductor Eng Package structure of dual die stack
JP4454181B2 (ja) * 2001-05-15 2010-04-21 富士通マイクロエレクトロニクス株式会社 半導体装置
US7863732B2 (en) * 2008-03-18 2011-01-04 Stats Chippac Ltd. Ball grid array package system
JP2012033875A (ja) * 2010-06-30 2012-02-16 Canon Inc 積層型半導体装置
KR101719636B1 (ko) * 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8710640B2 (en) * 2011-12-14 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with heat slug and method of manufacture thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030128523A1 (en) * 1998-06-30 2003-07-10 Moden Walter L. Heat sink with alignment and retaining features
US6212074B1 (en) * 2000-01-31 2001-04-03 Sun Microsystems, Inc. Apparatus for dissipating heat from a circuit board having a multilevel surface
US7781883B2 (en) * 2008-08-19 2010-08-24 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
CN102610594A (zh) * 2010-11-22 2012-07-25 钰桥半导体股份有限公司 具有散热座及增层电路的堆栈式半导体组体
WO2013089780A1 (en) * 2011-12-16 2013-06-20 Intel Corporation Package for a microelectronic die, microelectronic assembly containing same, microelectronic system, and method of reducing die stress in a microelectronic package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106672888A (zh) * 2015-11-11 2017-05-17 飞思卡尔半导体公司 封装集成电路管芯的方法和器件
CN106672888B (zh) * 2015-11-11 2022-03-11 恩智浦美国有限公司 封装集成电路管芯的方法和器件
CN110364518A (zh) * 2018-04-11 2019-10-22 意法半导体(格勒诺布尔2)公司 包括电子芯片的电子设备

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