CN204361076U - 电子系统 - Google Patents

电子系统 Download PDF

Info

Publication number
CN204361076U
CN204361076U CN201420597359.7U CN201420597359U CN204361076U CN 204361076 U CN204361076 U CN 204361076U CN 201420597359 U CN201420597359 U CN 201420597359U CN 204361076 U CN204361076 U CN 204361076U
Authority
CN
China
Prior art keywords
electronic device
metallic plate
chip
electronic
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201420597359.7U
Other languages
English (en)
Inventor
J-M·里维埃
N·马丁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics International NV
Original Assignee
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Grenoble 2 SAS filed Critical STMicroelectronics Grenoble 2 SAS
Application granted granted Critical
Publication of CN204361076U publication Critical patent/CN204361076U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4037Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
    • H01L2023/4056Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink heatsink to additional heatsink
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4037Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
    • H01L2023/4062Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink heatsink to or through board or cabinet
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094Thermal management, e.g. cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3675Cooling facilitated by shape of device characterised by the shape of the housing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15173Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本公开涉及一种电子系统,该电子系统包括第一电子器件(具有第一集成电路芯片)和第二电子器件(具有第二集成电路芯片)。第二电子器件在与第一集成电路芯片相同侧上被堆叠在第一电子器件上方。位于第一集成电路芯片周围的电连接元件将第二电子器件电连接到第一电子器件。被配置用于热量捕获和转移的金属板在第一电子器件和第二电子器件之间延伸。金属板包括经对准以允许电连接元件以一定距离通过的通道。

Description

电子系统
技术领域
本实用新型涉及微电子领域。
背景技术
构造包括彼此堆叠并且彼此电连接的电子器件的电子系统是众所周知的,每个电子器件包括至少一个集成电路芯片。
电子器件的堆叠尤其具有改进电连接的性能以及减小尺寸的优点。然而在一些情况下,出现了一些集成电路芯片产生热量,而且产生的热量会加热其它集成电路芯片并且随后退化其它集成电路芯片的性能的问题。这尤其是当第一电子器件包括产生热量的处理器芯片并且堆叠在第一电子器件上的第二电子器件包括存储器芯片的情况,该存储器芯片的功能尤其在其温度升高时退化。
以上描述的情形构成了提高电子系统的性能(尤其是程序执行速率)的障碍。然而,目前存在于在电子系统的期望性能和其尺寸之间采取折中的情况并不令人满意,尤其在诸如移动电话之类的便携式设备的领域。
实用新型内容
本公开的实施方式旨在解决目前存在于在电子系统的期望性能和其尺寸之间采取折中的情况并不令人满意的问题。
根据本公开的一个方面,提供了一种电子系统,包括:
第一电子器件,包括至少一个第一集成电路芯片,
第二电子器件,包括至少一个第二集成电路芯片,
其中所述第二电子器件在与所述第一集成电路芯片相同侧上被堆叠在所述第一电子器件上方,并且通过位于所述第一集成电路芯片周围的电连接元 件被连接到所述第一电子器件,
其中所述第一电子器件还包括被配置用于热量捕获和转移的金属板,所述金属板在所述第一集成电路芯片上方的位置处在所述第一电子器件和所述第二电子器件之间延伸,所述金属板具有被布置用于允许所述电连接元件以一定距离通过所述金属板的通道。
优选地,所述金属板与所述第二电子器件分离地延伸。
优选地,所述金属板在所述第一电子器件上方与其接触。
优选地,导热胶层被插入在所述金属板和所述第一电子器件之间。
优选地,导热胶层被插入在所述金属板和所述第一集成电路芯片之间。
优选地,所述第一电子器件被配置为通过电连接元件被安装在印刷电路板上,以及其中所述金属板具有外侧部分,所述外侧部分被配置为与所述印刷电路板发生接触。
优选地,所述电子系统还包括盖,所述盖被配置为包围所述第二电子器件并且具有位于所述金属板的外侧部分上方的边缘。
优选地,所述外侧部分包括外围条带。
优选地,所述外侧部分包括突出部。
优选地,所述盖具有通风孔。
优选地,所述电子系统还包括被安装在所述金属盖上方的散热器。
根据本公开的另一方面,提供了一种电子系统,包括:
第一电子器件,包括:
第一集成电路芯片,具有包括第一电触点的正面;
第一衬底,具有包括第二电触点和第三电触点的正面;
其中所述第一集成电路芯片的正面面对所述第一衬底的正面,并且所述第一电触点被电连接到所述第二电触点;
被配置用于热量捕获和转移的金属板,所述金属板包括与所述第一集成电路芯片的背面接触的中心区域以及包括与所述第一衬底 的所述第三电触点对准的开口的外围区域;
第二电子器件,包括第二衬底,所述第二衬底具有包括第四电触点的背面;以及
电连接件,其延伸穿过所述金属板中的所述开口并且将所述第四电触点电连接到所述第三电触点。
优选地,所述第二电子器件包括第二集成电路芯片,所述第二集成电路芯片被安装至所述第二衬底的正面并且与所述第四电触点电连接。
优选地,所述第一衬底的背面被配置为被安装至接线板,并且其中所述金属板的所述外围区域延伸越过第一衬底的周界并且被配置用于附接至所述接线板的正面。
优选地,所述金属板的所述外围区域中的所述开口包括多个开口,所述多个开口中的每个开口对应于所述第三电触点中的单个第三电触点。
优选地,所述金属板的所述外围区域中的所述开口包括多个开口,所述多个开口中的每个开口对应于多个所述第三电触点。
优选地,所述电子系统还包括包围至少所述第二电子器件的盖。
优选地,所述盖被安装到所述金属板的所述外围部分。
优选地,所述盖包括通风孔。
优选地,所述电子系统还包括被安装到所述盖的散热结构。
在本公开的各个实施方式中,由芯片产生的热量优先扩散进入衬底晶片和其电连接网络,对于面向衬底晶片的面,热量直接扩散,而对于背对衬底晶片的面,热量通过金属板间接扩散,金属板构成了第一电子器件和第二电子器件之间的热屏障,以及热量从芯片的面8a转移到衬底晶片的优先手段。
附图说明
根据本实用新型的具体实施例的电子系统将通过由附图图示出的非限制性示例来描述,其中:
图1呈现了电子器件的截面;
图2A和2B呈现了图1的电子器件的金属板的顶视图;
图3呈现了另一电子器件的截面;
图4呈现了另一电子器件的截面;
图5A、图5B和图5C呈现了图4的电子器件的金属板的顶视图;
图6呈现了另一电子器件的截面;以及
图7呈现了另一电子器件的截面。
具体实施方式
如图1所示,电子系统1包括彼此堆叠并且彼此相距一定距离的第一电子器件2和第二电子器件3。
电子器件2包括设置有集成电连接网距络5的衬底晶片4,集成电连接网络5包括:在一个面4a上被布置在其中心部分上的电连接焊盘6a和被布置在其外围部分上的电连接焊盘6b,以及在其相对的面4b上的电连接焊盘7。
电子器件2包括在衬底晶片4的面4a上通过电连接元件9安装在衬底晶片4上的至少一个集成电路芯片8,电连接元件9被插入在芯片8的电连接焊盘与电连接网络5的电连接焊盘6a之间。
电子器件3包括设置有集成电连接网络11的衬底晶片10,集成电连接网络11包括:在一个面10a上被布置在其外围部分上的电连接焊盘12,以及在其相对的面10b上被布置在其外围部分上的电连接焊盘13。
电子器件3包括至少一个集成电路芯片14,至少一个集成电路芯片14通过粘接层15被安装在其面10a上方并且通过电连接线16电连接到电连接网络11的焊盘12,芯片14和电连接线被嵌入到绝缘材料层17中。根据备选实施例,芯片14可以通过电连接元件被安装在衬底晶片10上。
电子器件3通过电连接元件18(诸如金属珠)被安装在电子器件2上,电连接元件18被插入在电子器件2的电连接网络5的电连 接焊盘6b和电子器件3的电连接网络11的电连接焊盘13之间。
因此,衬底晶片10的面10b面向芯片8和衬底晶片4的面4a并且与它们相距一定距离,电连接元件18位于芯片8周围,并且衬底晶片10在芯片8和芯片14之间延伸。 
电子系统1可以通过电连接元件20(诸如金属珠)被安装在印刷电路板19上,电连接元件20被插入在衬底晶片4的电连接网络5的电连接焊盘7和印刷电路板19的电连接焊盘19a之间。
根据一个实施例,芯片8可以是处理器芯片,处理器芯片的操作会引起产生热量,芯片14可以是存储器芯片,如果其温度变得太高,则其操作容易退化。
电子器件2配备有用于捕获和转移热量的金属板21,例如由铜或铝制成,金属板21在第一电子器件2和第二电子器件3之间延伸,优选地不与第二电子器件接触,以便至少部分地把由芯片8产生的热量转移到衬底晶片4和/或印刷电路板19。
金属板21包括中心部分22,中心部分22在第一电子器件2的芯片8和第二电子器件3的衬底晶片10之间平坦延伸。
金属板21还包括外围部分23,外围部分23至少部分包围中心部分22,并且外围部分23在第一电子器件2的位于芯片8周围的部分上方平坦延伸并且具有通道24,连接第一电子器件2和第二电子器件3的电连接元件18穿过通道24但不与其接触或相距一定距离。
根据图1所示的实施例,金属板21为盘形,芯片8位于其中。其中心部分22通过导热胶层25被安装在芯片8的与衬底晶片4和电连接元件9不同侧的面8a上。其外围部分23通过导热胶层26被安装在衬底晶片4的面4a上,该外围部分23的外围边沿大致沿着衬底晶片4的外围边缘延伸。
因此,由芯片8产生的热量优先扩散进入衬底晶片4和其电连接网络5,对于面向衬底晶片4的面,热量直接扩散,而对于背对衬底晶片4的面,热量通过金属板21间接扩散,金属板21构成了第一电子器件2和第二电子器件3之间的热屏障,以及热量从芯片8 的面8a转移到衬底晶片4的优先手段。
具体地并且优选地,衬底晶片4的热量随即通过电连接元件20转移到印刷电路板19。
结果是第二电子器件3的芯片14被保护以免其温度的任何过度上升。
根据如图2A所示的备选实施例,通道24具有大开口24a,每个开口24a用于使多个电连接元件18通过。
根据如图2B所示的另一备选实施例,通道24具有个体开口24b,每个个体开口24b用于使单个电连接元件18通过。
根据图3,其图示了另一电子系统1A,其中第一电子器件2还包括封装材料,该封装材料形成了被布置在芯片8周围且在衬底晶片4的面10b上的模块27。用于电连接元件18的路径和布置的开口28被布置在封装模块27中。
根据该示例,金属板21被平坦的金属传热板29替代,金属传热板2在芯片8和封装模块27上方延伸并且通过导热胶层30被安装在其上,金属板29具有像金属板21一样的通道31以用于位于开口28上方的电连接元件18通过。
根据图4,其图示了另一导电系统1B,其中尤其如图1所示的第一电子器件2配备有金属传热板32,金属传热板32包括图1的金属板21和并且包括外侧部分33,外侧部分33延伸了金属板21的外围部分23并且具有在印刷电路板19上方变平坦的端部部分34,在第二电子器件2周围并且与其相距一定距离。
外侧部分33可以通过加固部件35和/或通过导热胶层36平坦安装在印刷电路板19上方。
因此,来自芯片8并且被金属板32捕获的热量可以至少部分地通过其外侧部分33直接被转移到印刷电路板19。
如图5A所示,金属板32的外侧部分33可以包括包围外围部分23的外围条带33a。
如图5B所示,金属板32的外侧部分33可以包括多个突出部 33b,多个突出部33b被间隔开、延伸了外围部分23并且被设置为例如从外围部分23的角部开始。
如图5C所示,金属板32可以只包括金属板21的中心部分22和突出部33c,突出部33c被间隔开、延伸了中心部分22的角部、并且从电子器件2和3的角部上方通过并且距其一定距离。在这种情况下,用于电连接元件18通过的通道可以由分别被布置在间隔的突出部33c之间的凹陷部37构成。
根据备选实施例,金属板可以包括如图3所示的金属板29来代替如图1所示的金属板21。
根据图6,图示了另一电子系统1C,其中图4所示的电子系统1B被进一步配备有金属盖38,金属盖38包围第二电子器件3,至少和芯片14相距一定距离,并且金属盖38具有到达金属板32的被安装在印刷电路板19上的外侧部分34上方的端部边缘39。边缘39可以通过加固部件35和/或粘接层40来进行固定。
另外,金属盖38具有通风孔41并且可以设置有外部散热器42,外部散热器42被固定其位于芯片14上方并且与其相距一定距离的部分上。
根据图7,图示了另一电子系统1D,其中图3所示的电子系统1A被进一步被配备有金属盖43,金属盖43以一定距离包围第二电子器件3,金属盖43具有到达金属板29的突出的外围部分45上方的端部边缘44。端部边缘44和该突出的外围部分45可以通过加固部件和/或粘接层来固定。
金属盖43也具有通风孔46,并且可以设置有外部散热器47,外部散热器47被固定其位于芯片14上方并且与其相距一定距离的部分上。
因此,金属盖38和43以及散热器41和47可以帮助将由芯片8产生的热量消散到环境空气中,为了保护芯片14免受温度过度上升。
本实用新型不限于上面描述的示例。特别地,用于热量捕获和转移的金属板可以有非常不同的形状。在不背离本实用新型的范围 的情况下,多个其它备选实施例也是可能的。

Claims (20)

1.一种电子系统,其特征在于,包括:
第一电子器件,包括至少一个第一集成电路芯片,
第二电子器件,包括至少一个第二集成电路芯片,
其中所述第二电子器件在与所述第一集成电路芯片相同侧上被堆叠在所述第一电子器件上方,并且通过位于所述第一集成电路芯片周围的电连接元件被连接到所述第一电子器件,
其中所述第一电子器件还包括被配置用于热量捕获和转移的金属板,所述金属板在所述第一集成电路芯片上方的位置处在所述第一电子器件和所述第二电子器件之间延伸,所述金属板具有被布置用于允许所述电连接元件以一定距离通过所述金属板的通道。
2.根据权利要求1所述的电子系统,其特征在于,所述金属板与所述第二电子器件分离地延伸。
3.根据权利要求1所述的电子系统,其特征在于,所述金属板在所述第一电子器件上方与其接触。
4.根据权利要求1所述的电子系统,其特征在于,导热胶层被插入在所述金属板和所述第一电子器件之间。
5.根据权利要求1所述的电子系统,其特征在于,导热胶层被插入在所述金属板和所述第一集成电路芯片之间。
6.根据权利要求1所述的电子系统,其特征在于,所述第一电子器件被配置为通过电连接元件被安装在印刷电路板上,以及其中所述金属板具有外侧部分,所述外侧部分被配置为与所述印刷电路板发生接触。
7.根据权利要求1所述的电子系统,其特征在于,还包括盖,所述盖被配置为包围所述第二电子器件并且具有位于所述金属板的外侧部分上方的边缘。
8.根据权利要求7所述的电子系统,其特征在于,所述外侧部分包括外围条带。
9.根据权利要求7所述的电子系统,其特征在于,所述外侧部分包括突出部。
10.根据权利要求7所述的电子系统,其特征在于,所述盖具有通风孔。
11.根据权利要求7所述的电子系统,其特征在于,还包括被安装在所述金属盖上方的散热器。
12.一种电子系统,其特征在于,包括:
第一电子器件,包括:
第一集成电路芯片,具有包括第一电触点的正面;
第一衬底,具有包括第二电触点和第三电触点的正面;
其中所述第一集成电路芯片的正面面对所述第一衬底的正面,并且所述第一电触点被电连接到所述第二电触点;
被配置用于热量捕获和转移的金属板,所述金属板包括与所述第一集成电路芯片的背面接触的中心区域以及包括与所述第一衬底的所述第三电触点对准的开口的外围区域;
第二电子器件,包括第二衬底,所述第二衬底具有包括第四电触点的背面;以及
电连接件,其延伸穿过所述金属板中的所述开口并且将所述第四电触点电连接到所述第三电触点。
13.根据权利要求12所述的电子系统,其特征在于,所述第二电子器件包括第二集成电路芯片,所述第二集成电路芯片被安装至所述第二衬底的正面并且与所述第四电触点电连接。
14.根据权利要求12所述的电子系统,其特征在于,所述第一衬底的背面被配置为被安装至接线板,并且其中所述金属板的所述外围区域延伸越过第一衬底的周界并且被配置用于附接至所述接线板的正面。
15.根据权利要求12所述的电子系统,其特征在于,所述金属板的所述外围区域中的所述开口包括多个开口,所述多个开口中的每个开口对应于所述第三电触点中的单个第三电触点。
16.根据权利要求12所述的电子系统,其特征在于,所述金属板的所述外围区域中的所述开口包括多个开口,所述多个开口中的每个开口对应于多个所述第三电触点。
17.根据权利要求12所述的电子系统,其特征在于,还包括包围至少所述第二电子器件的盖。
18.根据权利要求17所述的电子系统,其特征在于,所述盖被安装到所述金属板的所述外围部分。
19.根据权利要求17所述的电子系统,其特征在于,所述盖包括通风孔。
20.根据权利要求17所述的电子系统,其特征在于,还包括被安装到所述盖的散热结构。
CN201420597359.7U 2013-10-30 2014-10-15 电子系统 Active CN204361076U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1360584 2013-10-30
FR1360584A FR3012670A1 (fr) 2013-10-30 2013-10-30 Systeme electronique comprenant des dispositifs electroniques empiles munis de puces de circuits integres

Publications (1)

Publication Number Publication Date
CN204361076U true CN204361076U (zh) 2015-05-27

Family

ID=50289786

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201420597359.7U Active CN204361076U (zh) 2013-10-30 2014-10-15 电子系统
CN201410547304.XA Active CN104600040B (zh) 2013-10-30 2014-10-15 包括设置有集成电路芯片的堆叠的电子器件的电子系统

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201410547304.XA Active CN104600040B (zh) 2013-10-30 2014-10-15 包括设置有集成电路芯片的堆叠的电子器件的电子系统

Country Status (3)

Country Link
US (1) US9275977B2 (zh)
CN (2) CN204361076U (zh)
FR (1) FR3012670A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9673175B1 (en) * 2015-08-25 2017-06-06 Freescale Semiconductor,Inc. Heat spreader for package-on-package (PoP) type packages
CN106672888B (zh) * 2015-11-11 2022-03-11 恩智浦美国有限公司 封装集成电路管芯的方法和器件
US10297541B2 (en) 2016-11-18 2019-05-21 Intel Corporation Multiple-component substrate for a microelectronic device
US10497687B2 (en) 2016-12-31 2019-12-03 Intel Corporation Configurable semiconductor package
FR3061600B1 (fr) * 2017-01-03 2020-06-26 Stmicroelectronics (Grenoble 2) Sas Dispositif electronique comprenant une puce rainuree
US20190206839A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Electronic device package
FR3080218B1 (fr) 2018-04-11 2022-02-11 St Microelectronics Grenoble 2 Dispositif electronique comprenant des puces electroniques
US20210066155A1 (en) * 2019-08-30 2021-03-04 Intel Corporation Microelectronics package comprising a package-on-package (pop) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone
JP7280208B2 (ja) * 2020-01-22 2023-05-23 日立Astemo株式会社 電子制御装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297960B1 (en) * 1998-06-30 2001-10-02 Micron Technology, Inc. Heat sink with alignment and retaining features
US6212074B1 (en) * 2000-01-31 2001-04-03 Sun Microsystems, Inc. Apparatus for dissipating heat from a circuit board having a multilevel surface
TW479339B (en) * 2001-03-01 2002-03-11 Advanced Semiconductor Eng Package structure of dual die stack
JP4454181B2 (ja) * 2001-05-15 2010-04-21 富士通マイクロエレクトロニクス株式会社 半導体装置
US7863732B2 (en) * 2008-03-18 2011-01-04 Stats Chippac Ltd. Ball grid array package system
US7781883B2 (en) * 2008-08-19 2010-08-24 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
JP2012033875A (ja) * 2010-06-30 2012-02-16 Canon Inc 積層型半導体装置
US20120126399A1 (en) * 2010-11-22 2012-05-24 Bridge Semiconductor Corporation Thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
KR101719636B1 (ko) * 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8710640B2 (en) * 2011-12-14 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with heat slug and method of manufacture thereof
IN2014CN03370A (zh) * 2011-12-16 2015-07-03 Intel Corp

Also Published As

Publication number Publication date
US20150115424A1 (en) 2015-04-30
US9275977B2 (en) 2016-03-01
CN104600040B (zh) 2019-05-07
CN104600040A (zh) 2015-05-06
FR3012670A1 (fr) 2015-05-01

Similar Documents

Publication Publication Date Title
CN204361076U (zh) 电子系统
KR101798571B1 (ko) 반도체 패키지
US7928590B2 (en) Integrated circuit package with a heat dissipation device
US9076749B2 (en) Electronic system comprising stacked electronic devices comprising integrated-circuit chips
CN103426839B (zh) 半导体封装
US9554453B2 (en) Printed circuit board structure with heat dissipation function
KR102001880B1 (ko) 적층 패키지 및 제조 방법
CN103703549A (zh) 用于直接表面安装的裸露芯片封装
US20080258294A1 (en) Heat-dissipating semiconductor package structure and method for manufacturing the same
KR20150130660A (ko) 반도체 패키지 및 그의 제조 방법
US20130147027A1 (en) Semiconductor package
CN103426869B (zh) 层叠封装件及其制造方法
US8928148B2 (en) Semiconductor component and device provided with heat dissipation means
CN101419957B (zh) 半导体器件及其制造方法
US7629682B2 (en) Wafer level package configured to compensate size difference in different types of packages
CN109801900A (zh) 一种电力用逆变电路装置
US9402331B2 (en) Integrated circuit chip comprising electronic device and electronic system
US9142529B2 (en) Chip package with improved heat dissipation and manufacturing method thereof
CN103050454A (zh) 堆迭封装构造
US20160260651A1 (en) Semiconductor device
JP5120087B2 (ja) 半導体装置及びその製造方法
CN216311757U (zh) 立体埋嵌封装结构
US20140345117A1 (en) Semiconductor device with thermal dissipation lead frame
US20160106002A1 (en) Internal heat-dissipation terminal
CN205666231U (zh) 一种多芯片无引脚封装结构

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20230519

Address after: Geneva, Switzerland

Patentee after: STMicroelectronics International N.V.

Address before: Grenoble

Patentee before: STMicroelectronics (Grenoble 2) S.A.S.

TR01 Transfer of patent right