CN101419957B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN101419957B
CN101419957B CN2008101729206A CN200810172920A CN101419957B CN 101419957 B CN101419957 B CN 101419957B CN 2008101729206 A CN2008101729206 A CN 2008101729206A CN 200810172920 A CN200810172920 A CN 200810172920A CN 101419957 B CN101419957 B CN 101419957B
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flexible substrate
semiconductor chip
conductive layer
semiconductor device
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CN101419957A (zh
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岩田靖昭
佐佐木千寻
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Renesas Electronics Corp
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Abstract

本发明涉及一种半导体器件及其制造方法。通过仅由布线连接到常规半导体芯片的热量排放，在新近的半导体器件中可能不能获得足够的热量排放性能。根据本发明的一方面的半导体器件包括：柔性衬底，包括第一主表面和第二主表面；半导体芯片；第一导热层，形成柔性衬底的第一主表面上并电连接到半导体芯片；和第二导热层，形成在柔性衬底的第二主表面上并与半导体芯片电绝缘。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件，更具体地，涉及一种将半导体芯片安装到柔性衬底上的半导体器件。
背景技术
例如，被称为载带封装(TCP)和薄膜覆晶封装(COF)的公知技术作为用于将半导体器件安装在液晶显示装置中的技术。随着高度集成或高功能IC的发展，JP06-314724A和JP11-102937A公开了一种技术，其包括经由通路孔在柔性衬底的背面侧上形成布线的技术，以改善TCP或COF的引线布置中的柔性。
另一方面，随着半导体器件操作速度的增加，从半导体芯片辐射的热量也逐渐变大。为此，近年来，甚至在包括布置在柔性衬底上的半导体芯片的诸如TCP的半导体器件中，也需要具有极好的热排放功能的半导体器件。
通常，在包括布置在柔性衬底上的半导体芯片的半导体器件中，从半导体芯片辐射的热通过利用连接到半导体芯片的布线层排出。但是，通过仅由连接到半导体芯片的布线的热量排放，可能不能在新近的半导体器件中获得充足的热排放性能。
如上所述，通过仅由连接到常规半导体芯片的布线的热量排放，可能不能获得充足的热排放性能。
发明内容
一种根据本发明的一方面的半导体器件包括：柔性衬底，包括第一主表面和第二主表面；半导体芯片；第一导热层，形成在柔性衬底的第一主表面上并电连接到半导体芯片；以及第二导热层，形成在柔性衬底的第二主表面上并与半导体芯片电绝缘。
此外，一种根据本发明的另一方面的半导体器件包括：柔性衬底，包括第一主表面和第二主表面；多个半导体芯片，以行布置在柔性衬底上；第一导热层，形成在柔性衬底的第一主表面上并电连接到所述多个半导体芯片；以及第二导热层，形成在柔性衬底的第二主表面上并与所述多个半导体芯片电绝缘，其中第二导热层包括在与所述多个半导体芯片的行方向交叉的方向上的长侧部。
更进一步，一种根据本发明的又一方面的制造半导体器件的方法：在柔性衬底的第一主表面上形成第一导热层，以电连接到半导体芯片；在柔性衬底的第二主表面上形成第二导热层，以与半导体芯片电绝缘；将半导体芯片布置在第一导热层上；以及用树脂密封第一导热层和半导体芯片的至少一部分。
根据本发明，能够改善半导体封装的热量排放性能。
附图说明
附图中：
图1示出根据本发明第一实施例的半导体器件的横截面图；
图2A和2B示出根据本发明第一实施例的半导体器件；
图3A、3B、3C、3D、3E、3F和3G示出根据本发明的第一实施例的半导体器件的制造过程；
图4A和4B示出根据本发明第二实施例的半导体器件；以及
图5A和5B示出根据本发明第二实施例的半导体器件的背面与膜馈送方向之间的关系。
具体实施方式
第一实施例
以下，将参考附图描述本发明的实施例。图1是根据本发明第一实施例的半导体器件(以下称为TCP)100的横截面图。如图1所示，该实施例的TCP100包括柔性衬底(以下还简单地称为衬底)1、第一导热层(以下称为第一传导图案)2、第二导热层(以下称为第二传导图案)3、阻焊剂4、半导体芯片5以及电极6。
柔性衬底1具有绝缘特性和柔性。例如，由聚酰亚胺树脂形成的带状膜用作柔性衬底。
第一传导图案2形成在衬底1的第一主表面(以下称为正面)上。第一传导图案2由诸如铜箔的电导体形成。第一传导图案2包括连接到半导体芯片5的电极的内引线部分、连接到外部元件上的外引线部分以及使内引线部分与外引线部分连接的布线部分。作为第一导热层，可以准备在其表面上镀有传导材料以防止布线氧化的任何层。
第二传导图案3形成在衬底1的第二主表面(以下称为背面)上。该实施例中，第二传导图案3由诸如铜箔的电导体形成。此外，第二传导图案3没有形成在半导体芯片安装在正面侧和衬底暴露的区域上。第二导热层3与安装到正面上的半导体芯片电绝缘。
阻焊剂4形成在除安装半导体芯片的区域以外的第一传导图案2和第二传导图案3上。阻焊剂4是具有绝缘特性的涂层膜并具有下述密封树脂的防漏功能。另外，阻焊剂4还具有防变形效果，因为加强了柔性衬底或传导图案部分的包围。
半导体芯片5具有形成在其中的集成电路。其内电路和第一传导图案2经由在半导体芯片5上形成的电极6彼此连接。
图2A和2B是示出上述衬底1的正面和背面的视图。多个TCP100形成为以行或以矩阵布置在膜上，并划分以获得单独的半导体器件。因此，向每个TCP的两侧提供输送孔9。提供输送孔9是为了在连续进行器件装配情况下的膜馈送的目的。
如上所述，第一传导图案2和第二传导图案3形成在衬底1的两侧上。第一传导图案2电连接到半导体芯片上，而第二传导图案3与半导体芯片电绝缘。与背面侧不提供任何东西并且热从聚酰亚胺树脂表面排出到空气的情况相比较，以这种方式在TCP的背面侧上提供作为导热层的传导图案允许减小热阻。结果，改善TCP的热量排放性能，由此还能减小安装芯片造成热击穿等的可能性。
此外，除与安装半导体芯片5的区域相对应的部分以外，形成第二传导图案3。在半导体芯片安装在具有上述结构的膜上的情况下，接合工具可与膜直接接触。通常，当安装半导体芯片时，接合工具在被加热的状态下使用。在第二传导图案3形成在整个背面上的状态中进行焊接的情况下，接合工具的热经由第二传导图案3而部分地排出。因此，去除安装半导体芯片的区域的传导图案，从而防止焊接的热量排放。因此，能够有效地安装半导体芯片。
图3A至3G是示出制造如上构造的TCP的方法的视图。以下，参考图3A至3G描述制造该实施例的TCP的方法。首先，将传导层形成在成为衬底的膜上。传导层通过已知的光刻工艺或蚀刻工艺图案化为预定的形状(见图3A和3B)。在图3A至3G中，膜的正面和背面同时形成有传导层。例如，在正面上形成传导层之后，对于背面可重复相同的工艺，以形成背面侧的传导层。
为了将诸如铜箔的上述电导体附着到基膜1，例如，使用粘合剂(未示出)。例如，将具有极好的粘性和热阻的热固性环氧粘合剂用作粘合剂。
之后，阻焊剂4形成在除安装半导体芯片5的区域以外的第一和第二传导图案上(见图3C)。然后，将半导体芯片5安装到TCP100上。
具体而言，半导体芯片5的电极6与TCP的第一传导图案的内引线彼此连接。在该情况下，内引线例如经由凸点电极连接到安装到半导体封装的半导体芯片上。将TCP的传导部分连接到半导体芯片的连接部分的过程例如可通过内引线焊接实现。在该情况下，例如，在设置于焊接台7上的半导体元件的连接部分与TCP的传导部分对准之后，接合工具8在加热条件下压在TCP上，以在短时间内进行多个部分处的连接(见图3D)。
然后，作为最后的过程，半导体芯片和内引线由树脂密封以致被包围，以便保护半导体芯片和内引线免受周围环境的湿度、污染等影响。例如，将环氧树脂用作密封树脂(见图3F)。以这种方式，完成半导体器件100(见图3G)。
如上所述，在该实施例中，形成电连接到半导体芯片5上的第一传导图案2和与半导体芯片5电绝缘的第二传导图案3。与背面侧不提供任何东西并且热从聚酰亚胺树脂的表面排出到空气的情况相比较，提供传导图案作为TCP背面侧上的导热层允许热阻减小。结果，改善TCP的热量排放性能，由此还能减小安装芯片造成热击穿等的可能性。
此外，在该实施例所示的半导体器件100中，第二传导图案3是用于热量排放目的而形成的导热层。因此，第一传导图案2和第二传导图案3不需要经由通孔彼此电连接，并因此衬底1不需要形成有通孔。第二传导图案3在不进行形成通孔的过程的情况下可以正好与第一传导图案2相同的方式形成。因此，使半导体器件100的制造过程比JP06-314724A或JP11-102937A所公开的TCP的制造过程简单，其在TCP的背面上形成有作为布线图案的导体。
第二实施例
图1是示出类似于第一实施例的本实施例的半导体器件200的横截面视图。图4A和4B分别示出半导体芯片5安装到其上的正面和与半导体芯片5安装到其上的正面相对的背面。注意，在图4A和4B中，与图2A和2B相同的构造由相同的附图标记标示，并省略其详细描述。在图4A和4B中，图2B所示的半导体器件100中的TCP的第二传导图案3形成为条带形状。条带形状沿包括长侧部和短侧部的多个传导图案沿半导体芯片5的长侧部方向布置的方向形成。
这样的条带形状可通过在衬底1的背面上形成的铜箔上执行蚀刻而形成。此外，除与安装在衬底1的正面上形成的半导体芯片5的区域相对应的部分以外，在TCP的背面上形成的条带形状被形成。
图5A和5B是示出条带形状相对于膜馈送方向的取向的视图。在图5A所示的TCP中，条带形状沿垂直于膜馈送方向的方向延伸。在图5B所示的TCP中，条带形状沿与膜馈送方向相同的方向延伸。
如上所述，在第二传导图案3形成为条带形状的情况下，能改善作为柔性衬底1的柔性。在只考虑柔性的情况下，可选择条带形状相对于膜馈送方向的任何取向。但是，在考虑膜倒回方向的情况下，在TCP的背面上形成的条带形状优选地沿垂直于膜馈送方向的方向延伸。此外，当待安装的半导体芯片包括长侧部和短侧部时，条带形状沿长侧部方向提供，从而在能保持半导体芯片的长侧部方向的强度的同时能改善柔性。
如上所述，在本实施例中，在TCP的背面上形成的第二传导图案3形成为条带形状。第二传导图案3形成为条带形状，由此能改善TCP的柔性。此外，增加第二传导图案3的表面积，由此更加改善热量排放性能。另外，除与安装半导体芯片5的区域相对应的部分以外，形成第二传导图案3。在半导体芯片5安装到具有这种结构的膜上的情况，接合工具能与膜直接接触。因此，由于焊接的热在去除安装半导体芯片5的区域的传导图案时不会排出，所以能高效地安装半导体芯片。
以上，已描述了本发明的实施例，其中只要修改不偏离本发明的主旨就能够做出各种变型。在本发明的实施例中，热量排放表面形成在具有传导图案的柔性衬底的背面上，热量排放表面排出半导体芯片中产生的热。但是，如果目的是热量排放，则将热转化成要排出的红外线的特殊陶瓷图案可形成在柔性衬底的背面上。此外，在第二实施例中，将第二传导图案3做成条带形状。但是，如果增加第二传导图案3的表面积可有助于改善热量排放性能，则不一定提供条带形状，并且可采用各种形状。

Claims (7)

1.一种半导体器件，其包括：
柔性衬底，包括第一主表面和第二主表面；
半导体芯片；
第一导热层，形成在所述柔性衬底的所述第一主表面上并与所述半导体芯片电连接；以及
第二导热层，形成在所述柔性衬底的所述第二主表面上并与所述半导体芯片电绝缘，其中，
所述第二导热层是形成在所述柔性衬底的除去下述部分的所述第二主表面上，其中，所述部分是指：从所述半导体器件的平面视角来看，在所述柔性衬底的所述第一主表面上的所述半导体芯片所被安装的区域的正下方的部分。
2.如权利要求1所述的半导体器件，其中，所述第二导热层包括多个分开的传导图案。
3.如权利要求2所述的半导体器件，其中，所述多个分开的传导图案中的每个形成为具有长侧部和短侧部的条带形状。
4.如权利要求2所述的半导体器件，其中，所述多个分开的传导图案中的每个的长侧部以与所述半导体芯片的长侧部方向相同的方向形成。
5.如权利要求1所述的半导体器件，其中，在与在所述柔性衬底的所述第一主表面上安装所述半导体芯片的区域相对应的部分处，在所述柔性衬底的所述第二主表面上暴露所述柔性衬底。
6.一种半导体器件，其包括：
柔性衬底，包括第一主表面和第二主表面；
多个半导体芯片，以行的方式布置在所述柔性衬底上；
第一导热层，形成在所述柔性衬底的所述第一主表面上并与所述多个半导体芯片电连接；以及
第二导热层，形成在所述柔性衬底的所述第二主表面上并与所述多个半导体芯片电绝缘，
其中，所述第二导热层包括在与所述多个半导体芯片的行方向交叉的方向上的长侧部，
其中，
所述第二导热层是形成在所述柔性衬底的除去下述部分的所述第二主表面上，其中，所述部分是指：从所述半导体器件的平面视角来看，在所述柔性衬底的所述第一主表面上的所述半导体芯片所被安装的区域的正下方的部分。
7.一种制造半导体器件的方法，其包括：
在柔性衬底的第一主表面上形成第一导热层，以与半导体芯片电连接；
在所述柔性衬底的第二主表面上形成第二导热层，以与所述半导体芯片电绝缘；
将所述半导体芯片布置在所述第一导热层上；以及
用树脂密封所述第一导热层和所述半导体芯片的至少一部分，
其中，
所述第二导热层是形成在所述柔性衬底的除去下述部分的所述第二主表面上，其中，所述部分是指：从所述半导体器件的平面视角来看，在所述柔性衬底的所述第一主表面上的所述半导体芯片所被安装的区域的正下方的部分。
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US9490226B2 (en) 2014-08-18 2016-11-08 Qualcomm Incorporated Integrated device comprising a heat-dissipation layer providing an electrical path for a ground signal
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US6650009B2 (en) * 2000-07-18 2003-11-18 Siliconware Precision Industries Co., Ltd. Structure of a multi chip module having stacked chips
US6835897B2 (en) * 2002-10-08 2004-12-28 Siliconware Precision Industries Co., Ltd. Warpage preventing substrate

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06314724A (ja) * 1993-04-28 1994-11-08 Hitachi Cable Ltd 半導体素子搭載用両面配線基板，及びそれを用いた半導 体装置
JPH0758239A (ja) * 1993-06-30 1995-03-03 Matsushita Electric Works Ltd チップキャリア
JPH11102937A (ja) * 1997-09-26 1999-04-13 Hitachi Cable Ltd 両面配線ｔａｂ用テープ
US6002169A (en) * 1998-06-15 1999-12-14 Lsi Logic Corporation Thermally enhanced tape ball grid array package
JP2003068804A (ja) * 2001-08-22 2003-03-07 Mitsui Mining & Smelting Co Ltd 電子部品実装用基板
JP4972306B2 (ja) * 2004-12-21 2012-07-11 オンセミコンダクター・トレーディング・リミテッド 半導体装置及び回路装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US6650009B2 (en) * 2000-07-18 2003-11-18 Siliconware Precision Industries Co., Ltd. Structure of a multi chip module having stacked chips
US6835897B2 (en) * 2002-10-08 2004-12-28 Siliconware Precision Industries Co., Ltd. Warpage preventing substrate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开平6-314724A 1994.11.08

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