CN103703549A - 用于直接表面安装的裸露芯片封装 - Google Patents

用于直接表面安装的裸露芯片封装 Download PDF

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CN103703549A
CN103703549A CN201280027904.2A CN201280027904A CN103703549A CN 103703549 A CN103703549 A CN 103703549A CN 201280027904 A CN201280027904 A CN 201280027904A CN 103703549 A CN103703549 A CN 103703549A
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metal layer
encapsulation
semiconductor chip
leads
moulding material
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F·于
L·莱特
C-T·芬
S·霍尔顿
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

封装的半导体器件（100）包括包含衬底（112）的半导体芯片（110），其包括具有包含有源电路（114）的顶部（113）和底部（116）的衬底，在所述衬底的所述底部上直接连接至少一个背部金属层（118）。包括具有封装在成型材料内的芯片焊盘（125）和多条引线（127）的成型材料（132）的封装（130），其中引线包括包含接合部分（127（a）（1））的暴露部分（127（a））。半导体芯片的顶部连接至芯片焊盘，而且封装包括将背部金属层沿着封装的底面暴露的间隙。接线将半导体芯片的顶部上的焊盘耦合至引线。接合部分、沿着封装底面的成型材料和背部金属层相对于彼此全部基本位于一个平面。

Description

用于直接表面安装的裸露芯片封装
技术领域
所公开的实施例涉及包括具有裸露衬底（例如，硅）的芯片的封装的半导体器件以及包括这种封装的半导体器件的电子组件。
背景技术
对于包括至少一个半导体芯片在其中的半导体封装，尤其是对于功率集成电路（IC），散热问题是很重要的问题。具有较差散热性能的半导体封装不仅会产生错误，而且会降低产品可靠性并极大地增加制造成本。
其中一种公知的功率封装包括增强型冷却，它是含有散热板（例如，铜板）的裸露散热板封装，该散热板裸露在封装的底部。使用热传导芯片附着材料将芯片面向（有源顶部）散热板的顶部接合。另一种公知功率封装是裸露硅封装，其中倒装芯片将半导体芯片安装在芯片焊盘上，并暴露半导体芯片的底部。然后通过使用导热硅脂将散热板热耦合至半导体芯片。
这两种功率封装都具有大量的热阻力，降低了冷却性能，由于冷却路径中的多个界面，增加了封装的热阻力。例如，裸露的散热板封装包括半导体衬底（例如，硅）、芯片附着材料、散热板和冷却路径中从半导体顶部到下面的工件如印制电路板的焊料。类似地，裸露的硅封装包括衬底、导热硅脂和冷却路径中从半导体芯片顶部到大气中的散热片。
发明内容
所公开的实施例认识到常规封装的半导体器件，尤其是高功率半导体器件，在工作时由于较高的热阻力能够达到较高的结温度，其中较高的热阻力是由多个界面两端的大热电阻降造成的，在工作时，这些多个界面干扰封装器件到其散热片的散热。通过具有彼此基本是平面的引线的接合部分、封装的底面以及半导体芯片的背部，允许封装的半导体器件直接焊接到工件如印制电路板（PCB）上。最终由于热冷却路径到工件的界面的减少提高了工件（例如，PCB）的散热。
一个公开的实施例包括封装的半导体器件，其包括半导体芯片，半导体芯片包含衬底和至少一个与衬底的底部直接相连的背部金属层，衬底包括顶部和底部，顶部包括有源电路。包括具有芯片焊盘和多条引线的成型材料的封装被封在成型材料内，其中所述引线包括包含接合部分的裸露部分。半导体芯片的顶部连在芯片的焊盘上，而且封装包括将背部金属层沿着封装的底面暴露的间隙。接线将半导体芯片顶部上的焊盘耦合到引线上。接合部分、封装的底面和背部金属层相对于彼此全部基本位于一个平面。
另一个公开的实施例包括电子组件，该组件包括所公开的封装的半导体器件和包括多个表面焊盘的PCB。提供了从背部金属层和引线的接合部分到PCB上的表面焊盘的直接焊接连接。与传统组件相比，所公开的封装的半导体器件提供的直接可焊接性降低了组件成本，例如，通过消除导热硅脂和散热器的需要，以及连接散热器所增加的处理。此外，直接焊接减小了PCB组件的板空间，而且通过使用表面贴片器件（SMD）规则简化了PCB布局。
附图说明
图1A是根据示例性实施例的包括引线封装的示例性封装的半导体器件的截面图，其中用于直接表面安装的半导体芯片的背部金属沿着封装的底面暴露。
图1B是根据示例性实施例的包括无引线封装的示例性封装的半导体器件的截面图，其中半导体芯片的背部金属沿着封装表面的底面暴露。
图2是根据示例性实施例的包含图1A所示的封装的半导体器件的示例性电子组件的截面图，该半导体器件的通过使用直接焊接连接表面安装到多层PCB。
具体实施方式
图1A根据示例性实施例图示了包括引线封装的示例性封装的半导体器件100，其中，半导体芯片110的背部金属沿着封装的底面暴露以用于直接表面安装。半导体芯片110包括衬底（例如，硅或硅/锗）112和位于衬底112的底部116上的至少一个背部金属层118，衬底包括顶部113和底部116，顶部113包括有源电路114。半导体芯片110的顶部表面113上的有源电路114被配置为提供IC电路功能。背部金属层118直接连接到半导体芯片110的底部116。
能够使用各种背部金属层118。在一个实施例中，背部金属层118是单金属层，例如，铜层。铜层的厚度通常为3μm到6μm，但是能比这个范围更薄或更厚。其中一个示例性过程包括在形成铜层之前形成薄的籽晶层。在另一个实施例中，背部金属层包括半导体芯片110的背部116上的第一金属层和包括与在第一金属层上的第一金属层不同的至少一个第二金属层的多层金属栈。例如，第一金属层能够包括钛。公知钛为硅和其他半导体提供良好的粘附性，因此建立有效的“粘着层”。其他实施例可以包括钽、钯、钒或钼作为与半导体芯片110的背部116连接的第一层。与钛一样，这些金属为硅提供良好的粘附性，因为它们能够在相对较低的温度下与硅形成中间金属硅化物。具体多层背部金属栈（stack）的若干实例包括钛上覆铜，钛上覆银,钛上覆铜，栈包括第一、第二和第三金属层，例如钛上覆镍再覆金，和钛上覆镍再覆银。镍层能够为下面的金属层提供保护以免受到机械刻划和腐蚀。
在其他示例性实施例中，第一金属层或第二金属层能够包括镍。例如，镍上覆铬再覆银或金上覆镍再覆钯。铬能够充当阻挡层的作用以阻止金属扩散到衬底中，提供应力缓冲层，而且由于其较高的断裂强度还用于阻止金属栈内的断裂。多层金属栈的典型厚度能够包括第一金属层为1到2千埃
Figure BDA0000430361290000031
第二金属层为2到4千埃
Figure BDA0000430361290000032
第三金属层为10到20千埃
Figure BDA0000430361290000033
当金用于第三金属层时，金的厚度能够明显厚于20千埃
Figure BDA0000430361290000034
具体的金属层厚度能够比这些范围更薄或更厚。
背部金属层118的区域与半导体芯片110的底部116的区域匹配。此处所用的“直接相连”是指不包括任何中间层的连接。与半导体芯片110的底部116的区域匹配的背部金属层118由在单片化之前的半导体芯片110的背部116上的背部金属层118提供（例如，当半导体芯片110是晶圆形式时，背部金属层118被放置在衬底112的底部116），以使单片化过程将晶圆切割成多个半导体芯片，使得每个半导体芯片具有的区域在通过背部金属118和衬底112切割过程中是恒定的。
图1A的封装130显示为引线封装，其包括成型材料132，例如具有芯片焊盘125和多个引线127的标准环氧树脂封装材料，其中引线包括装入成型材料132内的部分和暴露部分127（a），暴露部分上的引线显示为弯曲的，其包括接合部分127（a）(1)，显示为引脚127（a）(1)。
半导体芯片110的顶部113由芯片连接材料126如环氧树脂连接至芯片焊盘125。背部金属层118由成型材料132中的间隙沿着封装130的底面130（a）部分来暴露。该封装能够由成型材料中的间隙成型，以暴露背部金属层118。背部金属层118允许封装的半导体器件100直接焊接在封装衬底如PCB上。
直接将封装的半导体器件100的背部金属层118焊接到封装的衬底（例如，PCB）上提供了从半导体芯片110到封装衬底的良好的热传递。在这个直接焊接的配置中，散热路径具有最小数量的界面，包括从半导体芯片110的顶部113上的有源器件114通过衬底112的厚度和背部金属118的微小贡献，从而封装的半导体器件100到下面的工件的散热通常由半导体芯片110的衬底112的热传导性设定，或对于硅衬底，约为140W/m-K。在一个实施例中，半导体芯片110是变薄的芯片，例如，40到100μm的厚度，以进一步增强从封装的半导体器件到工件的热传递。
此外，与传统的组件相比，由封装的半导体器件100提供的直接可焊接性降低了组件成本，例如，通过消除导热硅脂和散热器的需要，以及连接散热器所增加的处理。此外，直接焊接减小了PCB组件的板空间，而且通过使用表面贴片器件（SMD）规则简化了PCB布局。
接线136显示为用于将半导体芯片110的顶部113上的接合焊盘119耦合至多个引线127。引脚127（a）（1）、封装130的底面130（a）和背部金属层118相对于彼此全部基本位于一个平面（或是基本平的）。此处所用的“基本位于一个平面（或是基本平的）”是指用于接合到工件（例如，PCB）的引线的接合部分如图1A所示的引脚127（a）（1）的下边缘、封装130的底面130（a）和背部金属层118之间的最大范围（range）全部在+/-0.25mm范围内（即，最大0.5mm的偏差）。此处所公开的“基本平的（或基本位于一个平面）”配置有利于直接表面安装，例如，诸如在焊接过程包括工件如PCB上具有0.3mm到0.5mm的厚度屏蔽网（掩膜）上的焊膏的情形。此外，如图1A所示，沿着封装130的底面130（a）的整个长度上的成型材料132还能够全部是基本平的（即没有凹陷区域）。
图1B根据示例性实施例图示了包括无引线封装180的示例性封装半导体器件150，其中半导体芯片110的背部金属118沿着用于直接表面安装的封装的底面180（a）暴露。封装180包括芯片焊盘125和显示为外围终端引线181（有时也称为外围引线）的多个暴露部分，其中暴露部分不会延伸超过成型材料132。外围终端引线181与无引线封装180的底面180（a）和背部金属118基本位于一个平面。无引线封装180能够包括各种扁平无引线封装，例如QFN（Quad Flat No leads，四方扁平无引线）和DFN（双扁平无引线）。封装的半导体器件150提供直接可焊接性、较高热等级、降低的组件成本、降低的PCB组件板空间和由上述封装的半导体器件100提供的板布局的简化。
图2图示了示例性电子组件200，该组件包括图1A所示的封装的半导体器件100，其中器件100通过使用直接焊接连接表面安装至包括至少一种内部金属（例如铜）面211和多个表面焊盘215的多层PCB210。直接焊接连接216显示为用于将背部金属层118和封装的半导体器件100的引脚127（a）（1）耦合至PCB210上的表面焊盘215的其中一些，例如铜表面焊盘。
另一个公开的实施例是形成电子器件的方法。所公开的封装半导体器件，例如所述封装的半导体器件100或150，是直接焊接到工件如包括多个表面焊盘的PCB上。背部金属层和多条引线的接合部分直接焊接到PCB的衬底焊盘。
形成在半导体晶圆上的有源电路和来自半导体晶圆的半导体芯片包括电路元件，这些电路元件通常可以包括晶体管、二极管、电容器和电阻器，以及信号线和其他互连各种电路元件的电导体，从而提供IC电路功能。此处所用的“提供IC电路功能”是指IC的电路功能，例如，可以包括专用集成电路（ASIC）、数字信号处理器、射频芯片、存储器、微控制器和片上系统或它们的组合。
所公开的实施例能够集成在各种组装流水线中以形成各种不同的IC器件及其相关产品。IC组件能够包括单半导体芯片和多芯片，例如，包括多个栈半导体芯片的PoP配置。可以使用各种封装衬底。半导体芯片可以在其中包括多种元件和/或在其上包括多层，包括阻断层、介电层、器件结构、有源元件和包括源区和漏区的无源元件、位线、基极、发射极、集电极、导线、导电孔等。另外，半导体芯片能够从各种过程形成，包括双极晶体管、CMOS、BiCMOS和MEMS。
本发明涉及到的本领域的技术人员将认识到在所要求保护的本发明的范围内所述实施例的修改和许多其他实施例是可能的。

Claims (15)

1.一种封装的半导体器件，其包括：
半导体芯片，其包括具有包含有源电路的顶部和底部的衬底和在所述衬底的所述底部上的至少一个背部金属层，其中所述背部金属层直接附着到所述半导体芯片的所述底部，并且所述背部金属层的区域与所述半导体芯片的所述底部的区域匹配；
封装，其包括具有芯片焊盘和多条引线的成型材料，所述芯片焊盘和多条引线被封装入所述成型材料内，其中所述多条引线包括含有接合部分的暴露部分；
其中所述半导体芯片的所述顶部连接到所述芯片焊盘，并且其中所述封装包括将所述背部金属层沿着所述封装的底部暴露的间隙；和
接线，其将所述半导体芯片的所述顶部上的焊盘耦合至所述多条引线；
其中，所述接合部分、沿着所述封装的所述底部的所述成型材料和所述背部金属层相对于彼此全部基本位于一个平面。
2.根据权利要求1所述的器件，其中所述暴露部分横向延伸超过所述成型材料并弯曲超过所述成型材料；并且其中所述接合部分包括远端引脚。
3.根据权利要求1所述的器件，其中所述多条引线包括没有延伸到所述成型材料之外的多条外围终端引线；并且其中所述多条外围终端引线提供所述接合部分。
4.根据权利要求1所述的封装的半导体器件，其中所述背部金属层包括铜。
5.根据权利要求1所述的封装的半导体器件，其中所述背部金属层包括在所述半导体芯片的所述底部上的第一金属层和在所述第一金属层上的与所述第一金属层不同的至少一层第二金属层。
6.根据权利要求5所述的封装的半导体器件，其中所述第一金属层包括钛。
7.根据权利要求5所述的封装的半导体器件，其中所述第一金属层或所述第二金属层包括镍。
8.根据权利要求5所述的封装的半导体器件，其中所述第一金属层包括钛，所述第二金属层包括镍，并且还包括在所述第二金属层上的包括金或银的第三金属层。
9.根据权利要求1所述的封装的半导体器件，其中沿所述封装的所述底面的所述成型材料整体是平的。
10.一种电子组件，其包括：
封装的半导体器件，其包括：
半导体芯片，其包括具有包含有源电路的顶部和底部的衬底和在所述衬底的所述底部上的至少一个背部金属层，其中所述背部金属层直接连接到所述半导体芯片的所述底部，并且所述背部金属层的区域与所述半导体芯片的所述底部的区域匹配；
封装，其包括具有芯片焊盘和多条引线的成型材料，所述芯片焊盘和多条引线被封装入所述成型材料内，其中所述多条引线包括含有接合部分的暴露部分；
其中所述半导体芯片的所述顶部连接到所述芯片焊盘，并且其中所述封装包括将所述背部金属层沿着所述封装的底部暴露的间隙；和
接线，其将所述半导体芯片的所述顶部上的焊盘耦合至所述多条引线；
其中，所述接合部分、沿着所述封装的所述底部的所述成型材料和所述背部金属层相对于彼此全部基本位于一个平面；
印制电路板即PCB，其包括多个表面焊盘；和
从所述背部金属层和所述多条引线的所述接合部分到所述PCB上的所述多个表面焊盘的直接焊接连接。
11.根据权利要求10所述的电子组件，其中所述PCB包括多层PCB。
12.一种形成电子组件的方法，其包括：
提供包括半导体芯片的封装的半导体器件，其中半导体芯片，其包括具有包含有源电路的顶部和底部的衬底和在所述衬底的所述底部上的至少一个背部金属层，其中所述背部金属层直接附着到所述半导体芯片的所述底部，并且所述背部金属层的区域与所述半导体芯片的所述底部的区域匹配；封装，其包括具有芯片焊盘和多条引线的成型材料，所述芯片焊盘和多条引线被封装入所述成型材料内，其中所述多条引线包括含有接合部分的暴露部分；其中所述半导体芯片的所述底部连接到所述芯片焊盘，并且其中所述封装包括将所述背部金属层沿着所述封装的底部暴露的间隙；和接线，其将所述半导体芯片的所述顶部上的焊盘耦合至所述多条引线；其中，所述接合部分、沿着所述封装的所述底部的所述成型材料和所述背部金属层相对于彼此全部基本位于一个平面；以及
直接将所述封装的半导体器件焊接到印制电路板即PCB上，所述PCB包括多个表面焊盘，其中所述背部金属层和所述多条引线的所述接合部分被焊接在所述PCB上的多个衬底焊盘。
13.根据权利要求12所述的方法，其中所述包括暴露的部分横向延伸超过所述成型材料并弯曲超过所述成型材料，并且所述接合部分包括远端引脚。
14.根据权利要求12所述的方法，其中所述多条引线包括没有延伸超过所述成型材料的多条外围终端引线，并且其中所述多条外围终端引线提供所述接合部分。
15.根据权利要求12所述的方法，其中所述背部金属层包括所述半导体芯片的所述底部上的第一金属层和在所述第一金属层上的与所述第一金属层不同的至少一层第二金属层。
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CN107863332A (zh) * 2016-09-21 2018-03-30 英飞凌科技股份有限公司 电子器件、电子模块及其制造方法
CN116779571A (zh) * 2016-10-05 2023-09-19 安世有限公司 可翻转的半导体芯片
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US20130034937A1 (en) 2013-02-07
EP2727135A2 (en) 2014-05-07
WO2012138868A3 (en) 2013-02-21
JP2014515187A (ja) 2014-06-26
US20120256306A1 (en) 2012-10-11
US8304871B2 (en) 2012-11-06
EP2727135A4 (en) 2015-10-21
WO2012138868A2 (en) 2012-10-11

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