JPS6064457A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6064457A
JPS6064457A JP58171158A JP17115883A JPS6064457A JP S6064457 A JPS6064457 A JP S6064457A JP 58171158 A JP58171158 A JP 58171158A JP 17115883 A JP17115883 A JP 17115883A JP S6064457 A JPS6064457 A JP S6064457A
Authority
JP
Japan
Prior art keywords
electrode film
film
electrode
silicon substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58171158A
Other languages
English (en)
Inventor
Kenji Iimura
飯村　健二
Yoichi Nakajima
中島　羊一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58171158A priority Critical patent/JPS6064457A/ja
Publication of JPS6064457A publication Critical patent/JPS6064457A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置、特に、シリコン酸化物を含む皮膜
が設けられたシリコン基体に半田によシ銅を一成分とし
て宮む電極部拐を設ける場合の電極俗造に関するもので
ある。
〔発明の背景〕
シリコン基体上の皮膜の開孔を通してオーミックコンタ
クトのために設けられる′電極膜として良く用いられて
いるものにアルミニウム隠極膜、あるいは、クロム−ニ
ッケルー銀またはチタン−ニッケルー銀の三層構造の電
極膜がある。アルミニウム電極膜はシリコン基体やシリ
コン基体上の二酸化シリコン、二酸化シリコンをよむガ
ラス、あるいは、半、絶縁性の多結晶７リコンなどのシ
リコン酸化物を含む皮膜に対する密着性は良いが鉛−錫
系半田とのぬれ性が極めて低い。一方、上記の三層構造
の１−極膜はシリコン基体との密着性、半田付は性は艮
いが、シリコン酸化物を含む皮膜との密着性が悪い。
〔発明の目的〕
本発明の目的は、シリコン基体、シリコン基体上のシリ
コン酸化物を含む皮膜との密着性が良く、かつ、半田付
は性の良い電極構造を有する半導体装置’ｉ−提供する
にある。
〔発明の概要〕
上記目的を達成する本発明の特徴とするところは、シリ
コン基体およびその上のシリコン酸化物を含む皮膜上に
アルミニウム電極膜を設け、更に、クロム又はチタン−
ニッケルー金または銀の三層構造の電極膜を設けて半田
によシ銅を一成分として含む電極部材を設けていること
にある。
ここで、三層構造の電＠！、膜はアルミニウム電極膜よ
シも小さい平面寸法にされている。
〔発明の実施例〕
以下、図面に示す実施例と共に本発明を説明する。
第１図において、１はシリコン基体で、下主表面側から
順次Ｎ＋＋層、Ｎ９層、Ｎ層、Ｐ層を有し、Ｎ層とＰａ
ｄはプレーナ構造のＰＮ接合Ｊを形成している。下車表
面には、クロム−ニッケルー銀あるいはチタン−ニッケ
ルー銀等の三層構造のカソード電極膜２が設けられてお
シ、図示していない支持板に半田付けされている。玉虫
表面にはシリコン酸化膜３が表面安定化膜として設けら
れている。シリコン酸化膜３には開孔３ａが設けられて
おり、Ｐ層が露呈している。乙の露呈部分およびシリコ
ン酸化膜３の開孔全周縁部分にアルミニウム電極膜４が
設けられている。アルミニウム電極膜４の周縁端はＰ、
Ｎ接合Ｊの玉虫表面への歳出端よシ平面寸法が大きくさ
れ、シリコン酸化膜３を介してＮ層上に位置する部分は
、所謂、フィールドプレートとして働く。アルミニウム
電極膜４上に順次、クロム電極膜５、ニッケル′電極膜
６、銀電極膜７が設けられている。これらのｔ極膜５〜
７はアルミニウム’ｔｆＬ　極膜４の周縁よりも小さい
周として銅リード９が半田付けされている。
アルミニウム電極膜４は、シリコン基体１や、シリコン
酸化膜３への密着性を高めるために用いられておシ、ニ
ッケルｔａｂ膜６はシリコン基体１と半田８中の錫が相
互拡散によシ反応してわずかな力で剥離することを防止
するために用いられている。クロム電＋ｙＨ＠ｓはアル
ミニウム電極膜４中のアルミニウムがニッケル電極膜６
中を拡散して銀電極膜７にまで達することによシ半田８
がぬ五づらくなることを防止するため、および、シリコ
ン基体１とニッケルＦｌ　ｉＭ　膜６中のシリコンとニ
ッケルが合金化し、シリコン基体１の破壊強度を低下さ
せることを防止するために用いられている。
ま友、銀電極Ｍ７は半田８とのぬれ性を向上させるため
に用いられており、クロム電極膜５およびニッケル電極
膜６はシリコン基体１と電極リード９中の銅とが反応し
て半導体そのものの特性を劣化させることを防止してい
る。
シリコン基体１および電極膜４〜７相互の関係は応力計
算上は問題のない構成である。しかし、各電極膜４〜７
の周縁端をそろえた状態で、電極リード９を半田例けし
、また、カソード電極膜２を図示していない支持体へ固
着する熱処理を施したところ、シリコン基体１、シリコ
ン酸化膜３に亀裂を生じた。一方、シリコン酸化膜３が
無いものではとのような亀裂を生じないものの、半田８
が周縁端をたれ下った時に、シリコン基体１と電極リー
ド９中の銅が合金化した。
そこでアルミニウム電極膜４の周縁端を他の電極膜５〜
７０周縁端よシ大きくしたところ、これらの問題は同時
に解決された。このようなことは皮膜３として、硼けい
酸ガラスや燐けい酸ガラス等の二酸化シリコンを組成物
として′ざむガラスや半絶縁性の多結晶シリコン、所謂
、５ＩＰＯ８が設けられている場合でも同様である。
クロム電極膜５はチタン這極膜に、まだ、銀電極膜７は
金電極膜に代えても、同様な効果がある。
第１図に示す実施例で、シリコン基体１と電極リード９
間の接着強度は３　Ｋ４　ｆ　／　ｍｍ　２以）：あっ
たが、クロム電極）換５を設けなかったものは、シリコ
ン基体１と反応を生じ、また、アルミニウム電極膜４を
設けなかったものは０．　Ｉ　Ｋｇ　ｆ　／　ｒｕｎ”
以下であり、光分な接着強度を有していないことが確認
されている。
第２図、第３図はそれぞれ本発明の他の実施例を示して
おシ、第１図に示すものと同一物、和尚物には同一符号
が付けられている。
＠２図の実施例では、シリコン酸化膜３の開孔３ａの段
差を越えてクロム電極膜５、ニッケル電極膜６、銀’ｉ
ｉ　ｉ膜７が設けられている。
第３図の実施例ではＰＮ接合Ｊの上皇表面への露出端よ
シ内側でアルミニウム畦極膜４の周縁が終端し、フィー
ルドプレートとして働かない場合の構成である。
以上の実施例では、ダイオードを例にとって説明してい
るが、トランジスタ、サイリスタ等の他の半導体装置に
も適用可能である。そして、Ｐ層に対するオーミックコ
ンタクトだけでなく、Ｎ層に対するオーミックコンタク
トをとる場合にも適用できる。
〔発明の効果〕
以上説明したように、本発明によれば、シリコン基体お
よびその上のシリコン酸化物を含む皮膜との密着性が良
く、かつ、半田付は性の良い電極構造の半導体装置を得
ることができる。
【図面の簡単な説明】
第１図〜第３図はそれぞれ本発明の異なる実施例社示す
シリコン基体の断面図である。

Claims (1)

    【特許請求の範囲】
  1. １、　シリコン基体、上記シリコン基体の一主表面に設
    けられ開孔を有するシリコン酸化物を含む皮膜、上記開
    孔内のシリコン基体の一主表面部分および上記開孔の周
    囲の皮膜にかけて設けられたアルミニウムからなる第一
    の電極膜、上記第一の電極膜上に設けられその全周縁よ
    シ小さい周縁のクロムおよびチタンのいずれかよシなる
    第二の電極膜、上記第二の電極膜上に設けられその周縁
    とｔ″！ぼ同じ周縁のニッケルからなる第三の′ＫＬ極
    膜、上記第三の電極膜上に設けられその周縁とほぼ同じ
    周縁の金および銀のいずれかよりなる第四の電極膜、上
    記第四の電極膜上に半田を介して設けられた銅を一成分
    として含む電極部材を有することを特徴とする半導体装
    置。
JP58171158A 1983-09-19 1983-09-19 半導体装置 Pending JPS6064457A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58171158A JPS6064457A (ja) 1983-09-19 1983-09-19 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58171158A JPS6064457A (ja) 1983-09-19 1983-09-19 半導体装置

Publications (1)

Publication Number Publication Date
JPS6064457A true JPS6064457A (ja) 1985-04-13

Family

ID=15918060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58171158A Pending JPS6064457A (ja) 1983-09-19 1983-09-19 半導体装置

Country Status (1)

Country Link
JP (1) JPS6064457A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303164A (ja) * 1989-05-18 1990-12-17 Nec Kansai Ltd 半導体装置
JP2000036511A (ja) * 1998-07-01 2000-02-02 Motorola Inc 電子部品の製造方法
WO2012138868A2 (en) 2011-04-05 2012-10-11 Texas Instruments Incorporated Exposed die package for direct surface mounting

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131766A (en) * 1977-04-22 1978-11-16 Hitachi Ltd Semiconductor device electrode structural body and production of the same
JPS5733867A (en) * 1980-08-08 1982-02-24 Toshiba Corp Facsimile equipment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131766A (en) * 1977-04-22 1978-11-16 Hitachi Ltd Semiconductor device electrode structural body and production of the same
JPS5733867A (en) * 1980-08-08 1982-02-24 Toshiba Corp Facsimile equipment

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303164A (ja) * 1989-05-18 1990-12-17 Nec Kansai Ltd 半導体装置
JP2000036511A (ja) * 1998-07-01 2000-02-02 Motorola Inc 電子部品の製造方法
WO2012138868A2 (en) 2011-04-05 2012-10-11 Texas Instruments Incorporated Exposed die package for direct surface mounting
JP2014515187A (ja) * 2011-04-05 2014-06-26 日本テキサス・インスツルメンツ株式会社 ダイレクト表面実装のための露出されたダイパッケージ
EP2727135A4 (en) * 2011-04-05 2015-10-21 Texas Instruments Inc EXPOSED CHIP CAPSULE FOR DIRECT SURFACE MOUNTING

Similar Documents

Publication Publication Date Title
US4693770A (en) Method of bonding semiconductor devices together
JPS6146058B2 (ja)
JPS59220982A (ja) 光素子用パッケ−ジ
JPS6064457A (ja) 半導体装置
JPS5936425B2 (ja) 中間層を有するリ−ドフレ−ム構造
JPH03136334A (ja) 半導体集積回路上の外部電極構造
JP2914409B2 (ja) 半導体素子
JPS61115332A (ja) 半導体装置及びその製造方法
JPS63308924A (ja) 半導体装置
JPH04322435A (ja) 半導体装置およびその製造方法
JPS6321871A (ja) 半導体装置
JPS60262434A (ja) 半導体装置
JPS6373561A (ja) 半導体装置
JPS62208654A (ja) リ−ドフレ−ム
JPS59231828A (ja) ボンデイングパツドをもつ半導体装置
JPH0199217A (ja) 半導体装置の製造方法
JPS5824442Y2 (ja) 半導体装置
JPS58191449A (ja) 多層配線構造
JPS59101878A (ja) 半導体装置
JPS6027166A (ja) 半導体装置
JPS62219934A (ja) 半導体装置
JPH05326527A (ja) バンプ形成用アンダバリヤメタルリボン
JPH0434955A (ja) 集積回路装置
JPS5940574A (ja) 半導体素子
JPH01179434A (ja) 半導体集積回路装置