CN110277375B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN110277375B
CN110277375B CN201810895777.7A CN201810895777A CN110277375B CN 110277375 B CN110277375 B CN 110277375B CN 201810895777 A CN201810895777 A CN 201810895777A CN 110277375 B CN110277375 B CN 110277375B
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substrate
semiconductor device
metal layer
layer
semiconductor
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CN110277375A (zh
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竹本康男
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Kioxia Corp
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Kioxia Corp
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Abstract

实施方式提供能抑制来自衬底或粘接层的放射线的影响的半导体装置。实施方式中的半导体装置具有衬底。半导体芯片的第1面上具有半导体元件。半导体芯片的与第1面为相反侧的第2面朝衬底的上表面而设在该衬底上。金属层设在半导体芯片的第2面与衬底的上表面之间。金属层采用的是α射线的射程比硅单晶短的金属材料。

Description

半导体装置
[相关申请案]
本申请案享受以日本专利申请2018-48194号(申请日：2018年3月15日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本实施方式涉及一种半导体装置。
背景技术
半导体装置具有搭载于衬底上的半导体芯片，且通过利用树脂将该半导体芯片密封而封装。衬底采用的是包含玻璃纤维的树脂材料。而且，有时，在半导体芯片与衬底之间介有包含玻璃填料的粘接层。这种衬底或粘接层中所含的玻璃材料有时会释放出α射线等放射线。
发明内容
实施方式提供一种能抑制来自衬底或粘接层的放射线的影响的半导体装置。
实施方式中的半导体装置具有衬底。半导体芯片的第1面上具有半导体元件。半导体芯片的第1面相反侧的第2面朝衬底的上表面而设在该衬底上。金属层设在半导体芯片的第2面与衬底的上表面之间。金属层采用的是α射线的射程比硅单晶短的金属材料。
附图说明
图1是表示第1实施方式中的半导体装置的构成例的剖视图。
图2是更详细地表示图1的虚线框C内的结构的剖视图。
图3(A)、(B)、图4(A)、(B)、图5(A)、(B)、图6(A)、(B)是表示第1实施方式中的半导体装置的制造方法的一例的概略的立体图。
图7是表示α射线的射程的曲线图。
图8是表示第2实施方式中的半导体装置的构成例的剖视图。
图9(A)及(B)是表示第2实施方式中的半导体装置的制造方法的一例的立体图。
具体实施方式
以下，参照附图说明本发明的实施方式。本实施方式并不限制本发明。以下的实施方式中，衬底的上下方向表示将设置着半导体芯片的面朝上时的相对方向，有与顺应重力加速度的上下方向不同的情况。附图是示意性或概念性的附图，各部分的比率等未必限于与实际情况相同。在说明书及附图中，对于与在上文中对应既有附图已作说明的要素相同的要素标注相同的符号并适当省略详细的说明。
(第1实施方式)
图1是表示第1实施方式中的半导体装置1的构成例的剖视图。半导体装置1可为例如NAND(Not AND，与非)型EEPROM(Electrically Erasable Programmable Read-OnlyMemory，带电可擦可编程只读存储器)等半导体存储器。该情况下，半导体装置1的1个封装体内具有存储器控制器CNT、及积层的多个存储器芯片CH。而且，半导体装置1具有衬底11、导线W、树脂层12、13、金属凸块B及粘接层DAF(Die Attachment Film)。
衬底11具有多个配线层112a～112c、树脂层110、阻焊层SRa、SRb。配线层112a～112c是以将任意导线W与任意金属凸块B之间电连接的方式配线。配线层112a～112c采用的是例如铜、钨等导电性金属。树脂层110设在配线层112a～112c之间、或它们的表面。树脂层110采用的是例如玻璃环氧树脂等在玻璃纤维中含有树脂的绝缘性玻璃树脂材料。
衬底11的上表面Ft上，积层有存储器控制器CNT及多个存储器芯片CH。作为半导体芯片的存储器控制器CNT设在积层的多个存储器芯片CH之下，且被树脂层13被覆。存储器控制器CNT控制多个存储器芯片CH的动作。在树脂层13之上，利用树脂层13粘接有多个存储器芯片CH。多个存储器芯片CH通过粘接层DAF而在纵向(与衬底11的上表面Ft大致垂直的方向)积层。
如图1所示，多个存储器芯片CH呈阶梯状错开而积层，进而从中途朝相反方向错开而积层。由此，抑制在存储器芯片CH的电极垫(未图示)上重复有其他存储器芯片CH，导线W能够连接于各存储器芯片CH的电极垫。存储器芯片CH例如可以是分别具有相同构成的存储器芯片。存储器芯片例如也可以是具有将存储器单元三维地排列的立体型存储器单元阵列的NAND型EEPROM芯片。
导线W接合在存储器控制器CNT或存储器芯片CH的电极垫与衬底11的配线层112a上的电极垫(未图示)之间，从而将它们之间电连接。导线W采用的是例如金等导电性金属。
树脂层12将存储器芯片CH及导线W密封在衬底11及树脂层13上。由此，树脂层12保护存储器控制器CNT、存储器芯片CH及导线W不受来自外部的冲击或外部大气的影响。
金属凸块B设置在与上表面Ft为相反侧的衬底11的下表面Fb，且连接于配线层112c的一部分。金属凸块B是为了将半导体装置1与外部的安装衬底(未图示)等电连接而设置。金属凸块B采用的是例如焊料等导电性金属。
图2是更详细地表示图1的虚线框C内的结构的剖视图。半导体装置1还具有设在存储器控制器CNT与衬底11之间的金属层50及粘接层DAF。
衬底11还具有设在上表面Ft侧的阻焊层SRa、及设在下表面Fb侧的阻焊层SRb。阻焊层SRa、SRb有时含有例如玻璃填料。存储器控制器CNT设在阻焊层SRa的上方。
存储器控制器CNT具有第1面F1及位于第1面F1相反侧的第2面F2。在存储器控制器CNT的第1面F1上设有半导体元件(未图示)。例如，存储器控制器CNT具有用于控制存储器芯片CH的控制电路、或临时储存数据的SRAM等作为半导体元件。存储器控制器CNT将第2面F2朝衬底11的上表面Ft而粘接在该衬底11上。
金属层50设在存储器控制器CNT的第2面F2与衬底11的上表面Ft之间。本实施方式中，金属层50是以被覆存储器控制器CNT的整个第2面F2的方式设置。金属层50采用的是α射线的射程比硅单晶短的金属材料。例如，当将某材料的密度设为ρ、空气中α射线的射程设为R、该材料的原子量设为A时，该材料中α射线的射程Rs如式1所示。式1是所谓的布拉格-克里曼式。
Rs＝(3.2×10-4×R×A1/2)/ρ (式1)
金属层50的材料可以其Rs小于硅单晶的Rs的方式选择。
这里，将说明金属层50采用α射线的射程比硅单晶短的金属材料的理由。
作为α射线，当半导体芯片的硅衬底薄时，会透过该硅衬底而到达半导体芯片表面的电路。该情况下，α射线可能会使半导体芯片的电路发生误动作从而引起软错误。对此，也考虑到利用α射线等放射线少的材料构成衬底。然而，这种衬底材料价格高，且在翘曲或可靠性等特性上存在问题。
如上所述，衬底11及阻焊层SRa、SRb含有玻璃纤维或玻璃填料，有时会释放出α射线等放射线。例如，α射线有时会透过存储器控制器CNT的硅衬底而到达设在其第1面F1上的SRAM等的电路。该情况下，可能会对储存在存储器控制器CNT的SRAM中的数据造成不良影响，从而发生软错误。
存储器控制器CNT中使用的硅衬底随着半导体装置1的微细化而薄膜化，成为约30μm～40μm左右。来自衬底11的阻焊层SRa或树脂层110的α射线可透过膜厚约40μm以下的薄硅衬底，到达存储器控制器CNT的电路。
因此，本实施方式中的半导体装置1中，在存储器控制器CNT与衬底11之间，设有α射线的射程比硅单晶短的金属层50。由此，金属层50吸收α射线，能抑制α射线到达设在存储器控制器CNT的第1面F1的SRAM等的电路。结果，能抑制存储器控制器CNT的SRAM的数据丢失或电路的误动作。
作为α射线的射程比硅单晶短的金属材料，考虑到例如铜或镍。而且，当使用铜或镍作为金属层50的材料时，金属层50的膜厚可为例如几μm～20μm。
第2面F2上设有金属层50的存储器控制器CNT通过粘接层DAF而粘接在阻焊层SRa上。
导线W电连接于存储器控制器CNT的第1面F1上的电极垫114与配线层112a上的电极垫116之间。树脂层13将最下层的存储器芯片CH粘接在衬底11上，且被覆存储器控制器CNT及导线W而予以保护。
接着，说明本实施方式中的半导体装置1的制造方法。
图3(A)～图6(B)是表示第1实施方式中的半导体装置1的制造方法的一例的概略的立体图及剖视图。首先，在硅衬底101的第1面F1上形成半导体元件。半导体元件是存储器控制器CNT所需的电路元件。
接着，如图3(A)所示，使用CMP(Chemical Mechanical Polishing，化学机械研磨)法等方法对硅衬底101的第2面F2进行研磨。由此，硅衬底101被薄膜化为约20μm～40μm的厚度。
接着，如图3(B)所示，在硅衬底101的第2面F2上形成金属层50。由此，金属层50形成在硅衬底101的第2面F2上。金属层50是使用例如溅镀法、镀覆法等而成膜。如上所述，金属层50是例如具有数μm～20μm的膜厚的铜或镍。
接着，如图4(A)所示，在金属层50上贴附粘接层DAF。接着，将切割胶带(未图示)贴附在硅衬底101的第2面F2侧的金属层50上。或者，将贴附有粘接层DAF的切割胶带贴附在硅衬底101的第2面F2侧的金属层50上。
接着，如图4(B)所示，使用切割刀片或切割激光等，将硅衬底101单片化成芯片单位。由此，完成存储器控制器CNT的芯片。
接着，准备衬底11。衬底11的上表面Ft及下表面Fb分别具有阻焊层SRa、SRb。使用光刻技术，如图5(A)所示对阻焊层SRa、SRb进行加工。
接着，将图4(B)所示的经单片化的存储器控制器CNT的芯片载置在衬底11的阻焊层SRa上。这时，利用粘接层DAF将存储器控制器CNT粘接在阻焊层SRa上。金属层50介于存储器控制器CNT的第2面F2与粘接层DAF之间。如上所述，金属层50例如为铜、镍等这样的式1中的Rs小于硅单晶的材料。金属层50的膜厚例如为几μm～20μm。由此，金属层50抑制来自衬底11的α射线到达设在存储器控制器CNT的第1面F1侧的电路。
接着，如图5(B)所示，利用导线W将存储器控制器CNT的电极垫114与衬底11的电极垫116之间连接。
接着，在最下层的存储器芯片CH的背面贴附或涂布树脂层13，将该存储器芯片CH放在存储器控制器CNT及导线W上。由此，将最下层的存储器芯片CH粘接在衬底11上，且如图6(A)所示，利用树脂层13将存储器控制器CNT及导线W密封。
接着，虽未图示，但将背面具有粘接层DAF的多个存储器芯片CH积层在最下层的存储器芯片CH上。接着，利用导线W将多个存储器芯片CH与衬底11之间连接。而且，利用树脂层12将多个存储器芯片CH及导线W密封。由此，形成图1所示的衬底11的第1面F1更上方的构造。
接着，在除去了阻焊层SRb的区域形成金属凸块B。由此，金属凸块B与配线层112c电连接，从而完成图1所示的本实施方式中的半导体装置1。
如以上所述，本实施方式中的半导体装置1中，在存储器控制器CNT与衬底11之间，设有α射线的射程比硅单晶短的金属层50。由此，金属层50吸收α射线，能抑制α射线到达设在存储器控制器CNT的第1面F1的SRAM等的电路。结果，能抑制存储器控制器CNT的SRAM的数据丢失或电路的误动作。
图7是表示α射线的射程的曲线图。纵轴表示α射线的射程。横轴表示α射线的能量。参照该曲线图可知，就α射线的射程Rs而言，铜明显小于硅单晶、硅氧化膜、聚酰亚胺、铝。该曲线图中虽未图示，但可知镍的Rs与铜的程度相同地较小。因此，通过在存储器控制器CNT与衬底11之间设置铜或镍这样的金属层50，能抑制因来自衬底或粘接层的α射线引起的误动作，且使半导体装置1的厚度变薄。
而且，根据本实施方式，衬底11也可为例如玻璃环氧树脂等含有玻璃纤维等树脂衬底，能选择适于各封装体的低价的衬底。
(第2实施方式)
图8是表示第2实施方式中的半导体装置1的构成例的剖视图。第2实施方式中，金属层50被夹在存储器控制器CNT的第2面F2与衬底11的上表面Ft之间的2个粘接层DAF1、DAF2之间。
第1粘接层DAF1设在衬底11的上表面Ft上。第2粘接层DAF2设在存储器控制器CNT的第2面F2。金属层50设在第1粘接层DAF1与第2粘接层DAF2之间。即，金属层50及粘接层DAF1、DAF2作为三层构造而设在存储器控制器CNT与衬底11之间。
第2实施方式的其他结构可与第1实施方式的相应结构相同。由此，第2实施方式能获得与第1实施方式相同的效果。
图9(A)及图9(B)是表示第2实施方式中的半导体装置1的制造方法的一例的立体图。首先，如参照图3(A)的说明所述，在硅衬底101的第1面F1上形成半导体元件。接着，使用CMP法等对硅衬底101的第2面F2进行研磨。
接着，如图9(A)所示，在切割胶带60上放置第1粘接层DAF1，在第1粘接层DAF1上放置金属层50，进而在金属层50上放置第2粘接层DAF2。
接着，如图9(B)所示，使硅衬底101的第2面F2朝第2粘接层DAF2侧而将硅衬底101粘接在第2粘接层DAF2上。由此，在硅衬底101的第2面F2与衬底11的上表面Ft之间，形成有包括第1粘接层DAF1、金属层50、第2粘接层DAF2的三层构造。金属层50自身的结构可与第1实施方式中的相同。
接着，如图4(B)所示，通过切割将硅衬底101单片化成芯片单位。之后，经过参照图5(A)～图6(B)所说明的工序，可获得第2实施方式中的半导体装置1。通过在硅衬底101的第2面F2与衬底11的上表面Ft之间设置金属层50，第2实施方式能获得与第1实施方式相同的效果。
而且，第1及第2实施方式中的半导体装置1中，设在衬底11的上表面Ft上的半导体芯片是存储器控制器CNT。因此，应受保护以免受α射线影响的半导体芯片是存储器控制器CNT。然而，当存储器芯片CH搭载在衬底11的上表面Ft上时，应受保护以免受α射线影响的半导体芯片成为存储器芯片CH。即，半导体芯片也可为存储器控制器CNT或多个存储器芯片CH的积层体中的任一种。
而且，所述实施方式中，半导体装置1是半导体存储器。然而，本实施方式中的半导体装置也可为半导体存储器以外的半导体装置。
已对本发明的若干实施方式进行了说明，但这些实施方式是作为示例提出的，并非旨在限定发明的范围。这些实施方式能够以其他各种形态实施，且可在不脱离发明主旨的范围内进行各种省略、置换、变更。这些实施方式或其变化包含在发明的范围或主旨中，同样也包含在权利要求书中记载的发明及与其同等的范围内。
[符号说明]
1 半导体装置
CNT 存储器控制器
CH 存储器芯片
11 衬底
W 导线
12、13、110 树脂层
B 金属凸块
DAF 粘接层
112a～112c 配线层
SRa、SRb 阻焊层
50 金属层

Claims (7)

1.一种半导体装置，具有：
衬底；
第1半导体芯片，在第1面上具有半导体元件，且为40μm以下的厚度，使所述第1面相反侧的第2面朝所述衬底的上表面而设在该衬底上；
金属层，设在所述第1半导体芯片的所述第2面与所述衬底的上表面之间；
多个第2半导体芯片，设在所述第1半导体芯片的所述第1面侧；以及
树脂层，设置在所述第1半导体芯片的所述第1面以及所述衬底的上表面，以使所述金属层不露出在外部大气的方式覆盖所述金属层，并与所述衬底的上表面直接接触；
所述金属层采用的是α射线的射程比硅单晶短的金属材料；
当将某材料的密度设为ρ、空气中的α射线的射程设为R、该材料的原子量设为A时，将该材料中的α射线的射程Rs以式1表示
Rs＝(3.2×10-4×R×A1/2)/ρ (式1)
所述金属层的Rs小于硅单晶的Rs。
2.根据权利要求1所述的半导体装置，其中所述金属层采用的是铜或镍。
3.根据权利要求1所述的半导体装置，其中所述金属层的膜厚为20μm以下。
4.根据权利要求1所述的半导体装置，其中所述衬底采用的是玻璃纤维中含有树脂的玻璃树脂材料。
5.根据权利要求1所述的半导体装置，其中还具有设在所述衬底的上表面上的阻焊层，
所述阻焊层含有玻璃填料。
6.根据权利要求1所述的半导体装置，其中所述金属层设在所述第1半导体芯片的所述第2面。
7.根据权利要求1所述的半导体装置，其中还具有：
第1粘接层，设在所述衬底的上表面上；及
第2粘接层，设在所述第1半导体芯片的所述第2面；
所述金属层设在所述第1粘接层与所述第2粘接层之间。
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