TWI692067B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TWI692067B
TWI692067B TW107124766A TW107124766A TWI692067B TW I692067 B TWI692067 B TW I692067B TW 107124766 A TW107124766 A TW 107124766A TW 107124766 A TW107124766 A TW 107124766A TW I692067 B TWI692067 B TW I692067B
Authority
TW
Taiwan
Prior art keywords
substrate
semiconductor device
metal layer
layer
semiconductor
Prior art date
Application number
TW107124766A
Other languages
English (en)
Other versions
TW201939687A (zh
Inventor
竹本康男
Original Assignee
日商東芝記憶體股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東芝記憶體股份有限公司 filed Critical 日商東芝記憶體股份有限公司
Publication of TW201939687A publication Critical patent/TW201939687A/zh
Application granted granted Critical
Publication of TWI692067B publication Critical patent/TWI692067B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

實施形態提供能抑制來自基板或接著層之放射線之影響之半導體裝置。 實施形態之半導體裝置具備基板。半導體晶片於其第1面上具有半導體元件。半導體晶片係將與第1面為相反側之第2面朝向基板之上表面而設於該基板上。金屬層設於半導體晶片之第2面與基板之上表面之間。金屬層中採用α射線之射程比單晶矽更短的金屬材料。

Description

半導體裝置
本實施形態關於一種半導體裝置。
半導體裝置具有搭載於基板上之半導體晶片，且藉由利用樹脂將該半導體晶片密封而封裝。基板採用包含玻璃纖維之樹脂材料。而且，存在於半導體晶片與基板之間介有包含玻璃填料之接著層的情況。此種基板或接著層中所含之玻璃材料有時會釋放出α射線等放射線。
實施形態提供一種能抑制來自基板或接著層之放射線之影響之半導體裝置。
實施形態之半導體裝置具備基板。半導體晶片於其第1面上具有半導體元件。半導體晶片係將與第1面為相反側之第2面朝向基板之上表面而設於該基板上。金屬層設於半導體晶片之第2面與基板之上表面之間。金屬層中採用α射線之射程比單晶矽更短的金屬材料。
以下，參照附圖說明本發明之實施形態。本實施形態並不限制本發明。以下之實施形態中，基板之上下方向表示將設置著半導體晶片之面朝上時的相對方向，有與順應重力加速度之上下方向不同的情況。附圖係示意性或概念性的附圖，各部分的比率等未必限於與實際情況相同。在說明書及附圖中，對於與在上文中對應既有附圖已作說明之要素相同的要素標註相同的符號並適當省略詳細的說明。
(第1實施形態） 圖1係表示第1實施形態中之半導體裝置1之構成例之剖視圖。半導體裝置1可為例如NAND(Not AND，與非)型EEPROM(Electrically Erasable Programmable Read-Only Memory，帶電可擦可編程只讀記憶體)等半導體記憶體。該情形時，半導體裝置1的1個封裝體內具有記憶體控制器CNT、及積層之複數個記憶體晶片CH。而且，半導體裝置1具有基板11、導線W、樹脂層12、13、金屬凸塊B及接著層DAF(Die Attachment Film)。
基板11具有複數個配線層112a～112c、樹脂層110、阻焊層SRa、SRb。配線層112a～112c係以將任意導線W與任意金屬凸塊B之間電連接之方式配線。配線層112a～112c採用例如銅、鎢等導電性金屬。樹脂層110設於配線層112a～112c之間、或其等之表面。樹脂層110採用例如玻璃環氧樹脂等在玻璃纖維中含有樹脂之絕緣性玻璃樹脂材料。
基板11之上表面Ft上，積層有記憶體控制器CNT及複數個記憶體晶片CH。作為半導體晶片之記憶體控制器CNT設於積層之複數個記憶體晶片CH之下，且被樹脂層13被覆。記憶體控制器CNT控制複數個記憶體晶片CH之動作。於樹脂層13之上，利用樹脂層13接著有複數個記憶體晶片CH。複數個記憶體晶片CH藉由接著層DAF而於縱向（與基板11之上表面Ft大致垂直之方向）積層。
如圖1所示，複數個記憶體晶片CH呈階梯狀錯開而積層，進而從中途朝相反方向錯開而積層。藉此，抑制於記憶體晶片CH之電極墊（未圖示）上重複有其他記憶體晶片CH，導線W能夠連接於各記憶體晶片CH之電極墊。記憶體晶片CH例如可以為分別具有相同構成之記憶體晶片。記憶體晶片例如亦可以為具有將記憶體單元三次元地排列之立體型記憶體單元陣列的NAND型EEPROM晶片。
導線W接合於記憶體控制器CNT或記憶體晶片CH之電極墊與基板11的配線層112a上之電極墊（未圖示）之間，從而將其等之間電連接。導線W採用例如金等導電性金屬。
樹脂層12將記憶體晶片CH及導線W密封於基板11及樹脂層13上。藉此，樹脂層12保護記憶體控制器CNT、記憶體晶片CH及導線W不受來自外部之衝擊或外部大氣之影響。
金屬凸塊B設置於與上表面Ft為相反側之基板11之下表面Fb，且連接於配線層112c之一部分。金屬凸塊B係為了將半導體裝置1與外部之安裝基板（未圖示）等電連接而設置。金屬凸塊B採用例如焊料等導電性金屬。
圖2係更詳細地表示圖1之虛線框C內之構成之剖視圖。半導體裝置1還具有設於記憶體控制器CNT與基板11之間的金屬層50及接著層DAF。
基板11還具有設於上表面Ft側之阻焊層SRa、及設於下表面Fb側之阻焊層SRb。阻焊層SRa、SRb有時含有例如玻璃填料。記憶體控制器CNT設於阻焊層SRa之上方。
記憶體控制器CNT具有第1面F1及位於第1面F1相反側之第2面F2。於記憶體控制器CNT之第1面F1上設有半導體元件（未圖示）。例如，記憶體控制器CNT具有用於控制記憶體晶片CH之控制電路、或臨時儲存資料之SRAM等作為半導體元件。記憶體控制器CNT將第2面F2朝基板11之上表面Ft而接著於該基板11上。
金屬層50設於記憶體控制器CNT之第2面F2與基板11之上表面Ft之間。本實施形態中，金屬層50係以被覆記憶體控制器CNT之第2面F2整面之方式設置。金屬層50採用α射線之射程比單晶矽更短的金屬材料。例如，當將某材料之密度設為ρ、空氣中α射線之射程設為R、該材料之原子量設為A時，該材料中α射線之射程Rs如式1所示。式1係所謂的布拉格-克里曼式。 Rs=(3.2×10-4 ×R×A1/2 )/ρ (式1)
金屬層50之材料可以其Rs小於單晶矽之Rs之方式選擇。
此處，說明金屬層50中採用α射線之射程比單晶矽更短的金屬材料之理由。
若半導體晶片之矽基板較薄，α射線會透過該矽基板而到達半導體晶片表面之電路。該情形時，α射線可能會使半導體晶片之電路發生誤動作從而引起軟錯誤。對此，亦有考量以α射線等放射線較少之材料構成基板。然而，此種基板材料價格高，且於翹曲或可靠性等特性上存在問題。
如上所述，基板11及阻焊層SRa、SRb含有玻璃纖維或玻璃填料，有時會釋放出α射線等放射線。例如，α射線有時會透過記憶體控制器CNT之矽基板而到達設於其第1面F1上之SRAM等電路。該情形時，可能會對儲存於記憶體控制器CNT之SRAM中之資料造成不良影響，從而發生軟錯誤。
記憶體控制器CNT中使用之矽基板隨著半導體裝置1之微細化而薄膜化，為約30 μm～40 μm左右。來自基板11之阻焊層SRa或樹脂層110之α射線可透過膜厚約40 μm以下的薄矽基板而到達記憶體控制器CNT之電路。
因此，本實施形態中之半導體裝置1係於記憶體控制器CNT與基板11之間，設有α射線之射程比單晶矽更短的金屬層50。藉此，金屬層50吸收α射線，能抑制α射線到達設於記憶體控制器CNT之第1面F1之SRAM等電路。其結果，能抑制記憶體控制器CNT之SRAM之資料遺失或電路誤動作。
作為α射線之射程比單晶矽更短的金屬材料，可考量例如銅或鎳。再者，若使用銅或鎳作為金屬層50之材料，金屬層50之膜厚可為例如數μm～20 μm。
第2面F2上設有金屬層50之記憶體控制器CNT藉由接著層DAF而接著於阻焊層SRa上。
導線W電連接於記憶體控制器CNT之第1面F1上之電極墊114與配線層112a上之電極墊116之間。樹脂層13將最下層之記憶體晶片CH接著於基板11上，且被覆記憶體控制器CNT及導線W而予以保護。
接著，說明本實施形態中之半導體裝置1之製造方法。
圖3(A)～圖6(B)係表示第1實施形態中之半導體裝置1之製造方法之一例的概略的立體圖及剖視圖。首先，於矽基板101之第1面F1上形成半導體元件。半導體元件係記憶體控制器CNT所需之電路元件。
接著，如圖3(A)所示，使用CMP(Chemical Mechanical Polishing，化學機械研磨)法等方法對矽基板101之第2面F2進行研磨。藉此，矽基板101被薄膜化為約20 μm～40 μm之厚度。
接著，如圖3(B)所示，於矽基板101之第2面F2上形成金屬層50。藉此，金屬層50形成於矽基板101之第2面F2上。金屬層50係使用例如濺鍍法、鍍覆法等而成膜。如上所述，金屬層50係例如具有數μm～20 μm之膜厚的銅或鎳。
接著，如圖4(A)所示，於金屬層50上貼附接著層DAF。接著，將切割膠帶（未圖示）貼附於矽基板101之第2面F2側之金屬層50上。或者，將貼附有接著層DAF之切割膠帶貼附於矽基板101之第2面F2側之金屬層50上。
接著，如圖4(B)所示，使用切割刀片或切割雷射等，將矽基板101單片化成晶片單位。藉此，完成記憶體控制器CNT之晶片。
接著，準備基板11。基板11之上表面Ft及下表面Fb分別具有阻焊層SRa、SRb。使用光刻技術，如圖5(A)所示對阻焊層SRa、SRb進行加工。
接著，將圖4(B)所示之經單片化之記憶體控制器CNT之晶片載置於基板11之阻焊層SRa上。此時，利用接著層DAF將記憶體控制器CNT接著於阻焊層SRa上。金屬層50介於記憶體控制器CNT之第2面F2與接著層DAF之間。如上所述，金屬層50例如為如銅、鎳等般之式1中之Rs小於單晶矽之材料。金屬層50之膜厚例如為幾μm～20 μm。藉此，金屬層50抑制來自基板11之α射線到達設於記憶體控制器CNT之第1面F1側之電路。
接著，如圖5(B)所示，利用導線W將記憶體控制器CNT之電極墊114與基板11之電極墊116之間連接。
接著，於最下層之記憶體晶片CH之背面貼附或塗佈樹脂層13，將該記憶體晶片CH放在記憶體控制器CNT及導線W上。藉此，將最下層之記憶體晶片CH接著於基板11上，且如圖6(A)所示，利用樹脂層13將記憶體控制器CNT及導線W密封。
接著，雖未圖示，但將背面具有接著層DAF的複數個記憶體晶片CH積層在最下層之記憶體晶片CH上。接著，利用導線W將複數個記憶體晶片CH與基板11之間連接。而且，利用樹脂層12將複數個記憶體晶片CH及導線W密封。藉此，形成圖1所示之基板11之第1面F1更上方的構造。
接著，於除去了阻焊層SRb之區域形成金屬凸塊B。藉此，金屬凸塊B與配線層112c電連接，從而完成圖1所示之本實施形態中之半導體裝置1。
如以上所述，本實施形態中之半導體裝置1中，於記憶體控制器CNT與基板11之間，設有α射線之射程比單晶矽短的金屬層50。藉此，金屬層50吸收α射線，能抑制α射線到達設於記憶體控制器CNT之第1面F1的SRAM等的電路。結果，能抑制記憶體控制器CNT之SRAM之資料遺失或電路的誤動作。
圖7係表示α射線之射程之曲線圖。縱軸表示α射線之射程。橫軸表示α射線的能量。參照該曲線圖可知，α射線之射程Rs在銅中明顯小於單晶矽、矽氧化膜、聚醯亞胺、鋁。該曲線圖中雖未圖示，但可知鎳之Rs與銅相同程度地小。因此，藉由在記憶體控制器CNT與基板11之間設置如銅或鎳般之金屬層50，能抑制因來自基板或接著層之α射線引起的誤動作，並將半導體裝置1之厚度薄化。
而且，根據本實施形態，基板11亦可為例如玻璃環氧樹脂等含有玻璃纖維等樹脂基板，可選擇適於各封裝體的低價之基板。
(第2實施形態） 圖8係表示第2實施形態之半導體裝置1之構成例之剖視圖。第2實施形態中，金屬層50於記憶體控制器CNT之第2面F2與基板11之上表面Ft之間被夾在2個接著層DAF1、DAF2之間。
第1接著層DAF1設於基板11之上表面Ft上。第2接著層DAF2設於記憶體控制器CNT之第2面F2。金屬層50設於第1接著層DAF1與第2接著層DAF2之間。即，金屬層50及接著層DAF1、DAF2作為三層構造而設於記憶體控制器CNT與基板11之間。
第2實施形態之其他構成可與第1實施形態之對應之構成相同。藉此，第2實施形態能獲得與第1實施形態相同的效果。
圖9(A)及圖9(B)係表示第2實施形態之半導體裝置1之製造方法之一例的立體圖。首先，如參照圖3(A)之說明所述，於矽基板101之第1面F1上形成半導體元件。接著，使用CMP法等對矽基板101之第2面F2進行研磨。
接著，如圖9(A)所示，於切割膠帶60上放置第1接著層DAF1，於第1接著層DAF1上放置金屬層50，進而在金屬層50上放置第2接著層DAF2。
接著，如圖9(B)所示，將矽基板101之第2面F2朝向第2接著層DAF2側而將矽基板101接著於第2接著層DAF2上。藉此，於矽基板101之第2面F2與基板11之上表面Ft之間，形成由第1接著層DAF1、金屬層50、第2接著層DAF2構成的三層構造。金屬層50自身之構成可與第1實施形態者相同。
接著，如圖4(B)所示，藉由切割將矽基板101單片化成晶片單位。之後，經過參照圖5(A)～圖6(B)所說明之步驟，可獲得第2實施形態之半導體裝置1。藉由在矽基板101之第2面F2與基板11之上表面Ft之間設置金屬層50，第2實施形態能獲得與第1實施形態相同的效果。
又，第1及第2實施形態之半導體裝置1中，設於基板11之上表面Ft上之半導體晶片係記憶體控制器CNT。因此，應受保護以避開α射線之半導體晶片係記憶體控制器CNT。然而，若將記憶體晶片CH搭載於基板11之上表面Ft上，則應受保護以避開α射線之半導體晶片成為記憶體晶片CH。即，半導體晶片可為記憶體控制器CNT或複數個記憶體晶片CH之積層體之任一種。
再者，上述實施形態中，半導體裝置1係半導體記憶體。然而，本實施形態之半導體裝置亦可為半導體記憶體以外的半導體裝置。
已對本發明之若干實施形態進行了說明，但該等實施形態係作為示例提出，並非旨在限定發明之範圍。該等實施形態能夠以其他各種形態實施，且可於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，同樣亦包含於請求項中記載之發明及與其同等之範圍內。 [相關申請案]
本申請案享受以日本專利申請2018-48194號（申請日：2018年3月15日）為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
1‧‧‧半導體裝置11‧‧‧基板12、13、110‧‧‧樹脂層50‧‧‧金屬層60‧‧‧切割膠帶101‧‧‧矽基板112a～112c‧‧‧配線層114、116‧‧‧電極墊B‧‧‧金屬凸塊CH‧‧‧記憶體晶片CNT‧‧‧記憶體控制器DAF、DAF1、DAF2‧‧‧接著層F1‧‧‧第1面F2‧‧‧第2面Fb‧‧‧下表面Ft‧‧‧上表面SRa、SRb‧‧‧阻焊層W‧‧‧導線
圖1係表示第1實施形態中之半導體裝置之構成例之剖視圖。 圖2係更詳細地表示圖1之虛線框C內之構成之剖視圖。 圖3(A)、(B)、圖4(A)、(B)、圖5(A)、(B)、圖6(A)、（B)係表示第1實施形態中之半導體裝置之製造方法之一例之概略的立體圖。 圖7係表示α射線之射程之曲線圖。 圖8係表示第2實施形態中之半導體裝置之構成例之剖視圖。 圖9(A)及（B)係表示第2實施形態中之半導體裝置之製造方法之一例的立體圖。
11‧‧‧基板
13、110‧‧‧樹脂層
50‧‧‧金屬層
112a~112c‧‧‧配線層
114、116‧‧‧電極墊
B‧‧‧金屬凸塊
CNT‧‧‧記憶體控制器
DAF‧‧‧接著層
F1‧‧‧第1面
F2‧‧‧第2面
Fb‧‧‧下表面
Ft‧‧‧上表面
SRa、SRb‧‧‧阻焊層
W‧‧‧導線

Claims (7)

  1. 一種半導體裝置，其具有：基板；第1半導體晶片，其在第1面上具有半導體元件，且厚度係40μm以下，且將與上述第1面為相反側之第2面朝上述基板之上表面而設於該基板上；金屬層，其設於上述第1半導體晶片之上述第2面與上述基板之上表面之間；及複數個第2半導體晶片，其設於上述第1半導體晶片之第1面側；上述金屬層中採用α射線之射程比單晶矽更短的金屬材料；且當將某材料之密度設為ρ、空氣中之α射線之射程設為R、該材料之原子量設為A時，將該材料中之α射線之射程Rs以式1表示：Rs=(3.2×10-4×R×A1/2)/ρ (式1)上述金屬層之Rs小於單晶矽之Rs。
  2. 如請求項1之半導體裝置，其中上述金屬層中採用銅或鎳。
  3. 如請求項1之半導體裝置，其中上述金屬層之膜厚為20μm以下。
  4. 如請求項1之半導體裝置，其中上述基板中採用使玻璃纖維中含有樹脂之玻璃樹脂材料。
  5. 如請求項1之半導體裝置，其更具有設於上述基板之上表面上之阻焊層，上述阻焊層含有玻璃填料。
  6. 如請求項1之半導體裝置，其中上述金屬層設於上述第1半導體晶片之上述第2面。
  7. 如請求項1之半導體裝置，其更具有：第1接著層，其設於上述基板之上表面上；及第2接著層，其設於上述第1半導體晶片之上述第2面；上述金屬層設於上述第1接著層與上述第2接著層之間。
TW107124766A 2018-03-15 2018-07-18 半導體裝置 TWI692067B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-048194 2018-03-15
JP2018048194A JP2019161105A (ja) 2018-03-15 2018-03-15 半導体装置

Publications (2)

Publication Number Publication Date
TW201939687A TW201939687A (zh) 2019-10-01
TWI692067B true TWI692067B (zh) 2020-04-21

Family

ID=67906014

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107124766A TWI692067B (zh) 2018-03-15 2018-07-18 半導體裝置

Country Status (4)

Country Link
US (1) US10916508B2 (zh)
JP (1) JP2019161105A (zh)
CN (1) CN110277375B (zh)
TW (1) TWI692067B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020038902A (ja) * 2018-09-04 2020-03-12 キオクシア株式会社 半導体装置
JP2020047714A (ja) * 2018-09-18 2020-03-26 キオクシア株式会社 半導体メモリおよびその製造方法
US11244844B2 (en) 2018-10-26 2022-02-08 Applied Materials, Inc. High flow velocity, gas-purged, side storage pod apparatus, assemblies, and methods

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143053A (en) * 1979-04-25 1980-11-08 Hitachi Ltd Semiconductor device
JPH04179150A (ja) * 1990-11-09 1992-06-25 Nec Yamagata Ltd 半導体封止用容器
JP2932840B2 (ja) * 1992-08-06 1999-08-09 日本電気株式会社 半導体素子のボンディング方法
JP2990968B2 (ja) * 1992-09-17 1999-12-13 富士通株式会社 半導体チップの実装構造
TWI233179B (en) * 2002-08-21 2005-05-21 Toshiba Corp Manufacturing method of mounting body, semiconductor device and mounting body
TWI256715B (en) * 2002-05-16 2006-06-11 Hitachi Ltd Semiconductor device and its manufacturing method
TWI277128B (en) * 2004-12-03 2007-03-21 Taiwan Semiconductor Mfg Low stress semiconductor device coating and method of forming thereof
TWI396243B (zh) * 2006-02-16 2013-05-11 Nitto Denko Corp 半導體裝置的製造方法
CN105789066A (zh) * 2016-05-09 2016-07-20 南通富士通微电子股份有限公司 一种半导体封装结构的制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63262867A (ja) 1987-04-20 1988-10-31 Nec Corp 半導体記憶装置
JPS6457650A (en) 1987-08-27 1989-03-03 Hitachi Ltd Semiconductor device
US5264726A (en) * 1989-07-21 1993-11-23 Nec Corporation Chip-carrier
JPH0936315A (ja) 1995-07-13 1997-02-07 Sony Corp 半導体装置
TW434646B (en) 1997-11-21 2001-05-16 Rohm Co Ltd Semiconductor device and method for making the same
JP2000058598A (ja) * 1998-08-13 2000-02-25 Citizen Watch Co Ltd 半導体装置の実装構造および実装方法
JP3394029B2 (ja) * 2000-03-21 2003-04-07 大塚化学株式会社 難燃性エポキシ樹脂組成物、及びその成形物、及び電子部品
US7221055B2 (en) * 2005-05-23 2007-05-22 Texas Instruments Incorporated System and method for die attach using a backside heat spreader
US7910156B2 (en) * 2007-03-30 2011-03-22 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate with selected conductors having solder thereon
JP4431628B1 (ja) 2008-06-05 2010-03-17 新光電気工業株式会社 半導体装置及びその製造方法
US8304871B2 (en) * 2011-04-05 2012-11-06 Texas Instruments Incorporated Exposed die package for direct surface mounting
KR20140057982A (ko) * 2012-11-05 2014-05-14 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143053A (en) * 1979-04-25 1980-11-08 Hitachi Ltd Semiconductor device
JPH04179150A (ja) * 1990-11-09 1992-06-25 Nec Yamagata Ltd 半導体封止用容器
JP2932840B2 (ja) * 1992-08-06 1999-08-09 日本電気株式会社 半導体素子のボンディング方法
JP2990968B2 (ja) * 1992-09-17 1999-12-13 富士通株式会社 半導体チップの実装構造
TWI256715B (en) * 2002-05-16 2006-06-11 Hitachi Ltd Semiconductor device and its manufacturing method
TWI233179B (en) * 2002-08-21 2005-05-21 Toshiba Corp Manufacturing method of mounting body, semiconductor device and mounting body
TWI277128B (en) * 2004-12-03 2007-03-21 Taiwan Semiconductor Mfg Low stress semiconductor device coating and method of forming thereof
TWI396243B (zh) * 2006-02-16 2013-05-11 Nitto Denko Corp 半導體裝置的製造方法
CN105789066A (zh) * 2016-05-09 2016-07-20 南通富士通微电子股份有限公司 一种半导体封装结构的制造方法

Also Published As

Publication number Publication date
US20190287922A1 (en) 2019-09-19
CN110277375A (zh) 2019-09-24
US10916508B2 (en) 2021-02-09
TW201939687A (zh) 2019-10-01
JP2019161105A (ja) 2019-09-19
CN110277375B (zh) 2023-08-22

Similar Documents

Publication Publication Date Title
TWI695492B (zh) 半導體裝置及其製造方法
US7560302B2 (en) Semiconductor device fabricating method
US7245008B2 (en) Ball grid array package, stacked semiconductor package and method for manufacturing the same
TWI692067B (zh) 半導體裝置
KR102649471B1 (ko) 반도체 패키지 및 그의 제조 방법
US10756060B2 (en) Semiconductor device
JP5543086B2 (ja) 半導体装置及びその製造方法
TW201320259A (zh) 半導體封裝及其製造方法
US20160079222A1 (en) Semiconductor device having terminals formed on a chip package including a plurality of semiconductor chips and manufacturing method thereof
US20130015570A1 (en) Stacked semiconductor package and manufacturing method thereof
JP2021129083A (ja) 半導体装置およびその製造方法
JP4496241B2 (ja) 半導体素子とそれを用いた半導体パッケージ
TWI750439B (zh) 半導體裝置及其製造方法
TW202008529A (zh) 半導體裝置及其製造方法
US11282818B2 (en) Semiconductor device
TWI812922B (zh) 半導體裝置
JP2022002249A (ja) 半導体装置およびその製造方法
JP2022036756A (ja) 半導体装置
US20230402431A1 (en) Semiconductor device and manufacturing method thereof
US20230063204A1 (en) Method for manufacturing semiconductor device
JP2023136139A (ja) 半導体装置およびその製造方法
JP2022098115A (ja) 半導体装置およびその製造方法
JP2022182532A (ja) 半導体装置およびその製造方法