TWI812922B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI812922B
TWI812922B TW110104997A TW110104997A TWI812922B TW I812922 B TWI812922 B TW I812922B TW 110104997 A TW110104997 A TW 110104997A TW 110104997 A TW110104997 A TW 110104997A TW I812922 B TWI812922 B TW I812922B
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semiconductor
wiring substrate
semiconductor device
metal layer
layer
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TW110104997A
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TW202207421A (zh
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山下真司
茨木聡一郎
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日商鎧俠股份有限公司
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Abstract

本實施方式之半導體裝置具備配線基板。半導體晶片具有半導體基板，該半導體基板具有第1面及與該第1面為相反側之第2面，該半導體晶片於第1面側具有SRAM，於第2面側接著於配線基板。半導體晶片包含設置於SRAM與配線基板間之半導體基板內的第1金屬層。

Description

半導體裝置
本發明之實施方式係關於一種半導體裝置。
半導體裝置之系統之大規模化使得暫時儲存資料之SRAM(Static Random Access Memory，靜態隨機存取記憶體)隨之不斷大電容化及低電壓化。若使SRAM微細化以實現大電容化及低電壓化，則SRAM之每單位記憶胞之軟性誤差率(FIT(Failure In Time，失效率))增大。
實施方式提供一種可兼顧SRAM之微細化與軟性誤差率之半導體裝置。
本實施方式之半導體裝置具備配線基板。半導體晶片具有半導體基板，該半導體基板具有第1面及與該第1面為相反側之第2面，且該半導體晶片於第1面側具有SRAM，於第2面側接著於配線基板。半導體晶片包含設置於SRAM與配線基板間之半導體基板內的第1金屬層。
以下，參照圖式對本發明之實施方式進行說明。本實施方式並不限定本發明。以下之實施方式中，配線基板之上下方向表示使設置半導體晶片之面朝上時之相對方向，可能與符合重力加速度之上下方向相反。圖式係模式性或概念性之圖，各部分之比率等未必與現實相同。說明書與圖式中，對於已經出現之圖式，對與已經敍述者相同之要素標註同一符號並適當省略詳細說明。
圖1、圖13係表示本實施方式之半導體裝置1之構成例之剖視圖。
半導體裝置1具備配線基板10、控制器晶片20、接著層30、金屬線40、金屬層50、記憶體晶片60、樹脂層80及金屬塊90。
半導體裝置1例如係於配線基板10上安裝記憶體晶片60及控制器晶片20並以樹脂層80密封之半導體封裝。半導體封裝例如可為BGA(Ball Grid Array，球柵陣列)、LGA(Land Grid Array，平面柵格陣列)等。
配線基板10係積層複數個樹脂層11及複數個配線層12而構成。樹脂層11例如使用玻璃材料及樹脂材料。例如，樹脂層11可為使玻璃纖維含有環氧樹脂而成之玻璃環氧樹脂等。配線層12例如可使用銅、鎢等低電阻金屬。使用此種玻璃材料之樹脂層11放射α射線。擔心α射線會對控制器晶片20內之SRAM中鎖存之資料產生不良影響，引起軟性誤差。
記憶體晶片60例如為搭載NAND(Not AND，反及)型快閃記憶體之半導體晶片。控制器晶片20例如為控制記憶體晶片60之半導體晶片。記憶體晶片60及控制器晶片20安裝於同一配線基板10上，藉由樹脂層80密封。藉此，半導體裝置1構成為1個半導體封裝。再者，亦可於配線基板10上進而安裝其他半導體晶片。又，半導體裝置1亦可為記憶體以外之其他LSI(Large Scale Integration，大型積體電路)。
控制器晶片20及記憶體晶片60係藉由接著層30接著於配線基板10上。圖1中，積層有2個記憶體晶片60，其等藉由接著層30而相互接著。再者，亦可積層3個以上之記憶體晶片60，亦可僅將1個記憶體晶片60接著於配線基板10上。本實施方式中，控制器晶片20未設置於記憶體晶片60上，而是經由接著層30設置於配線基板10之上方。控制器晶片20及記憶體晶片60經由金屬線40而電性連接於配線基板10之配線層12之任一者。接著層30例如使用DAF(Die Attachment Film，晶粒黏著膜)等樹脂材料。金屬線40例如使用金等低電阻金屬。
如圖1所示，控制器晶片20亦可配置於與配線基板10上設置記憶體晶片60之區域不同的區域。或者如圖13所示，控制器晶片20亦可於配線基板10上設置記憶體晶片60之區域內設置於記憶體晶片60之下方。即，控制器晶片20亦可設置於配線基板10與記憶體晶片60之間。
接著層31(第1接著部分)將控制器晶片20之背面F2與配線基板10接著。接著層32具有第2接著部分32a及第3接著部分32b。圖13之虛線表示接著部分32a與第3接著部分32b之邊界。第2接著部分32a將記憶體晶片60與配線基板10接著。第3接著部分32b將控制器晶片20之正面F1與記憶體晶片60接著。接著層31、32亦可包含同一樹脂材料(例如DAF)。
於配線基板10之背面設置有金屬塊90。金屬塊90連接於配線層12之任一者，經由配線基板10及金屬線40而電性連接於記憶體晶片60或控制器晶片20。金屬塊90例如使用焊料等低電阻金屬。
於控制器晶片20設置有金屬層50。參照圖2及圖3於下文說明控制器晶片20及金屬層50之構成。
圖2係表示控制器晶片20及金屬層50之構成例之剖視圖。圖3係表示控制器晶片20及金屬層50之構成例之俯視圖。圖2表示沿圖3之A-A線之剖面。
如圖2所示，控制器晶片20具備半導體基板20a，半導體基板20a具有作為第1面之正面F1、及與正面F1相反之側的作為第2面之背面F2。於半導體基板20a之正面F1側設置有半導體元件。半導體元件包含構成控制電路之CMOS(Complementary Metal Oxide Semiconductor，互補金屬氧化物半導體)電路21、及於CMOS電路21動作期間暫時儲存資料之SRAM22。控制器晶片20亦可包含其他半導體元件。
SRAM22例如形成於設置在半導體基板20a之井擴散層W。圖2表示構成SRAM22之1個電晶體。該電晶體具備閘極電極G、源極層S、漏極層D。圖2中，於半導體基板20a之正面F1側示出1個電晶體，但並不限定於此，亦可設置複數個電晶體。
於半導體基板20a之背面F2側設置有凹部99。於凹部99內之半導體基板20a之內壁被覆著絕緣膜55。進而，於絕緣膜55上設置有障壁金屬56。即，絕緣膜55設置於半導體基板20a與金屬層50之間，障壁金屬56設置於絕緣膜55與金屬層50之間。對絕緣膜55例如使用矽氧化膜等絕緣材料。對作為第2金屬層之障壁金屬56，例如使用鈦膜(Ti)、氮化鈦膜(TiN)、鉭膜(Ta)、氮化鉭膜(TaN)等金屬材料。
金屬層50於障壁金屬56上填充於凹部99內。即，絕緣膜55及障壁金屬56薄層地被覆凹部99內之半導體基板20a之內壁，金屬層50介隔絕緣膜55及障壁金屬56填充於凹部99內。對金屬層50例如使用銅及鋁等金屬材料。因絕緣膜55及障壁金屬56被覆凹部99內之內壁，因此金屬層50未與半導體基板20a、CMOS電路21及SRAM22直接接觸。藉此，可抑制金屬層50向半導體基板20a、CMOS電路21及SRAM22擴散，抑制金屬污染。
金屬層50設置於SRAM22之正下方，如圖1及圖2所示，設置於SRAM22與配線基板10之間之半導體基板20a內。金屬層50與SRAM22對應地設置於背面F2側，從背面F2填埋至半導體基板20a內。
又，如圖1及圖2所示，控制器晶片20係以背面F2朝向配線基板10之方式藉由接著層30而接著於配線基板10上。金屬層50與半導體基板20a之背面F2構成在大致同一平面上，因此可容易地以接著層30接著於配線基板10上。
如圖3、圖12所示，從相對於半導體基板20a之正面F1或背面F2大致垂直之方向觀察時，金屬層50覆蓋SRAM之整個形成區域。於平面佈局中，如圖12所示，金屬層50之形成區域亦可與SRAM之形成區域大致一致。於該情形時，金屬層50之形成區域之外緣與SRAM之形成區域之外緣大致一致。或者，金屬層50之形成區域亦可設置至SRAM之形成區域之外側，具有一定裕度。於該情形時，如圖3所示，相較SRAM之形成區域之外緣，金屬層50之形成區域之外緣位於略外側。
如此，藉由將金屬層50設置於SRAM22之正下方，配置於SRAM22與配線基板10之間，可保護SRAM22不受來自配線基板10之樹脂層11之α射線影響。
圖4係表示矽及銅之α粒子之射程之曲線圖。
放射性物質產生之α射線具有約9 MeV之能量，係造成SRAM之軟性誤差之原因之一。已知此種α射線係從包含玻璃材料之樹脂層11產生，該α射線會引起控制器晶片20之SRAM之軟性誤差。
如圖4所示，α粒子之射程於矽結晶中約為58 μm，於銅中約為23 μm。如此，與矽相比，α粒子之射程於銅中更短。因此，包含銅之金屬層50若厚度為23 μm以上，則可吸收來自樹脂層11之α射線，抑制SRAM22之軟性誤差。再者，鋁吸收α射線之效果雖與銅相比較差，但比矽好。因此，金屬層50亦可使用鋁。
假設於未設置金屬層50之情形時，半導體基板(矽基板)20a係配置於SRAM22與配線基板10之間。於該情形時，為了吸收來自樹脂層11之α射線，需要使半導體基板20a具有58 μm以上之厚度。即，藉由設置金屬層50，可使半導體基板20a之厚度變薄至一半以下。
金屬層50之厚度較佳為23 μm以上且未達58 μm。藉此，可使控制器晶片20之厚度變薄，並且有效地保護SRAM22不受來自樹脂層11之α射線影響。
如上所述，根據本實施方式，控制器晶片20於SRAM22與配線基板10之間之半導體基板20a內具有金屬層50。藉此，即便使半導體基板20a之厚度變薄，亦可抑制配線來自基板10之α射線到達SRAM22。例如，於金屬層50為銅之情形時，可使半導體基板20a之厚度變薄至23 μm以上且未達58 μm。其結果為，可使控制器晶片20之厚度變薄，並且抑制控制器晶片20之SRAM22之軟性誤差。尤其於如圖13所示之情形時，若使控制器晶片20之厚度變薄，則半導體裝置1整體變薄。因此，可抑制SRAM之軟性誤差，並且使半導體封裝薄厚度化(小型化)。
其次，對本實施方式之半導體裝置之製造方法進行說明。
圖5係表示本實施方式之半導體裝置之製造方法之一例之立體圖。圖6～圖11係本實施方式之半導體裝置之製造方法之一例之剖視圖。
首先，使用半導體製程，於圖5所示之晶圓狀之半導體基板20a上形成半導體元件。半導體基板20a例如為矽基板。半導體元件例如為電晶體、電容器元件、電阻元件等。藉此，如圖6所示，於半導體基板20a之正面F1側形成CMOS電路21及SRAM22。
其次，使用微影技術及RIE(Reactive Ion Etching，反應性離子蝕刻)法等，如圖7所示，從半導體基板20a之背面F2朝向半導體基板20a內形成凹部99。凹部99係設置於SRAM22之正下方，設置於與SRAM22對應之背面F2之區域。如參照圖3所說明，當從正面F1之上方觀察時，凹部99覆蓋SRAM22之形成區域整體。又，使凹部99之形成深度不會對CMOS電路21及SRAM22之特性造成影響。另一方面，為了使金屬層50之厚度變厚，且儘可能使半導體晶片20之厚度變薄，較佳為將凹部99儘可能形成得較深。因此，以於CMOS電路21及SRAM22之背面F2側保留較薄之半導體基板20a之方式形成凹部99。於後述絕緣膜55約為0.1 μm且障壁金屬56約為0.1 μm之非常薄之情形時，凹部99自背面F2起之深度為約23 μm以上且未達約58 μm。再者，視測定機器不同，有時會因進行測定之環境條件等而包含測定誤差。因此，本說明書中之「約」表示亦存在測定誤差引起與各數值不一致之情形。
其次，如圖8所示，使用CVD(Chemical Vapor Deposition，氣相沈積)法，於凹部99之內壁及背面F2上沈積絕緣膜(例如矽氧化膜)55。絕緣膜55之厚度例如約為0.1 μm。絕緣膜55將金屬層50與半導體基板20a電性絕緣。
其次，如圖9所示，使用濺鍍法或PVD(Physical Vapor Deposition，物理氣相沈積)法，於凹部99內及背面F2上之絕緣膜55上沈積障壁金屬(例如氮化鈦膜)56。障壁金屬56之厚度例如約為0.1 μm。障壁金屬56於藉由鍍覆法形成金屬層50時成為晶種層。絕緣膜55及障壁金屬56以不填埋凹部99內之方式形成得較薄。
其次，如圖10所示，使用電鍍法等，使金屬層50之材料(例如銅)沈積凹部99內及半導體基板20a之背面F2上。藉此，金屬層50之材料以填埋凹部99內之方式形成。金屬層50之厚度為23 μm以上且未達58 μm。
其次，使用CMP(Chemical Mechanical Polishing，化學機械研磨)法，研磨金屬層50、障壁金屬56及絕緣膜55，直至半導體基板20a之背面F2露出。藉此，獲得圖11所示之構造。此時，金屬層50之厚度較佳為約23 μm以上且未達58 μm。藉此，可由金屬層50吸收來自配線基板10之α射線，並盡量將半導體裝置1之厚度薄化。
其次，雖未圖示，使用刀片切割法或雷射切割法，將晶圓狀之半導體基板20a單片為控制器晶片20。藉此，完成控制器晶片20。又，記憶體晶片60亦經由半導體製程及切割法形成。
其次，如圖1所示，於控制器晶片20之背面F2貼附接著層30，將控制器晶片20貼附於配線基板10上。再者，相對於圖1所示之半導體裝置，圖13所示之半導體裝置中貼附控制器晶片20之位置不同，但可大致同樣地製造。又，記憶體晶片60亦藉由接著層30而貼附於配線基板10上。再者，本實施方式中，控制器晶片20未介隔記憶體晶片60而是藉由接著層30貼附於配線基板10上。控制器晶片20位於配線基板10之正上方，控制器晶片20之背面F2與配線基板10之上表面對向。又，此時，金屬層50位於SRAM22與配線基板10之間，可保護SRAM22不受來自配線基板10之α射線影響。
其次，以金屬線40將控制器晶片20及記憶體晶片60之電極墊與配線基板10之電極墊之間連接。金屬線40例如為金線。
其次，以樹脂層80將控制器晶片20、記憶體晶片60及金屬線40密封。藉此，樹脂層80可被覆保護控制器晶片20、記憶體晶片60及金屬線40。
其後，使用刀片切割法或雷射切割法而切割配線基板10，藉此將半導體裝置1單片化。藉此，完成本實施方式之半導體裝置1之封裝。
如上所述，根據本實施方式，可於控制器晶片20之SRAM22與配線基板10之間形成金屬層50。藉此，可使半導體基板20a之厚度變薄，並由金屬層50抑制來自配線基板10之包含玻璃材料之樹脂層11的α射線到達SRAM22。即，可使控制器晶片20之厚度變薄，並抑制控制器晶片20之SRAM之軟性誤差。可兼顧SRAM22之微細化與軟性誤差率。
本實施方式尤其於控制器晶片20配置於配線基板10附近之情形時有效。
對本發明之若干實施方式進行了說明，但該等實施方式係作為例而提出者，並非意圖限定發明之範圍。該等實施方式可另外以各種形態實施，可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。該等實施方式及其變化包含於發明之範圍及主旨內，且同樣包含於申請專利範圍所記載之發明及與其均等之範圍內。 [相關申請案]
本申請案享受以日本專利申請案2020-134076號(申請日：2020年8月6日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之所有內容。
1:半導體裝置 10:配線基板 11:樹脂層 12:配線層 20:控制器晶片 20a:半導體基板 21:CMOS電路 22:SRAM 30:接著層 31:接著層 32:接著層 32a:第2接著部分 32b:第3接著部分 40:金屬線 50:金屬層 55:絕緣膜 56:障壁金屬 60:記憶體晶片 80:樹脂層 90:金屬塊 99:凹部 D:漏極層 F1:正面 F2:背面 G:閘極電極 S:源極層 W:井擴散層
圖1係表示本實施方式之半導體裝置之構成例之剖視圖。 圖2係表示控制器晶片及金屬層之構成例之剖視圖。 圖3係表示控制器晶片及金屬層之構成例之俯視圖。 圖4係表示矽及銅之α粒子之射程之曲線圖。 圖5係表示本實施方式之半導體裝置之製造方法之一例的立體圖。 圖6～11係表示圖5後續之半導體裝置之製造方法之一例的剖視圖。 圖12係表示控制器晶片及金屬層之構成例之俯視圖。 圖13係表示本實施方式之半導體裝置之構成例之剖視圖。
1:半導體裝置
10:配線基板
11:樹脂層
12:配線層
20:控制器晶片
30:接著層
40:金屬線
50:金屬層
60:記憶體晶片
80:樹脂層
90:金屬塊

Claims (12)

  1. 一種半導體裝置，其具備：配線基板；及半導體晶片，其具有半導體基板，上述半導體基板具有第1面及與上述第1面為相反側之第2面，且上述半導體晶片於上述第1面側具有SRAM(Static Random Access Memory)，於上述第2面側接著於上述配線基板；上述半導體晶片包含：設置於上述SRAM與上述配線基板間之上述半導體基板內的第1金屬層；當相對於上述第2面從垂直方向觀察時，上述第1金屬層覆蓋上述SRAM整體。
  2. 如請求項1之半導體裝置，其進而具備：設置於上述配線基板上之第1區域之記憶體晶片，上述半導體晶片設置於上述配線基板上之第2區域，上述半導體晶片控制上述記憶體晶片。
  3. 如請求項1之半導體裝置，其進而具備：設置於上述配線基板之上方之記憶體晶片，上述半導體晶片設置於上述配線基板與上述記憶體晶片之間，上述半導體晶片控制上述記憶體晶片。
  4. 如請求項3之半導體裝置，其進而具備：接著層，上述接著層包含：第1部分，其將上述第2面與上述配線基板接著；第2部分，其將上述記憶體晶片與上述配線基板接著；及第3部分，其將上述記憶體晶片與上述半導體晶片接著。
  5. 如請求項1之半導體裝置，其中上述第1金屬層包含銅或鋁。
  6. 如請求項1之半導體裝置，其中上述第1金屬層之厚度為23μm以上且未達58μm。
  7. 如請求項1之半導體裝置，其中上述配線基板具有配線層，上述半導體裝置進而具有：將上述半導體晶片與上述配線層電性連接之金屬線。
  8. 如請求項1之半導體裝置，其中上述配線基板包含玻璃。
  9. 如請求項1之半導體裝置，其進而具備：將上述半導體晶片之上述第2面與上述配線基板接著之接著層。
  10. 如請求項9之半導體裝置，其中上述第1金屬層之上述配線基板側之面與上述半導體晶片之上述第2面位於同一平面上，上述接著層將上述第1金屬層與上述配線基板接著。
  11. 如請求項1之半導體裝置，其中上述半導體晶片進而具有：絕緣膜，其設置於上述半導體基板與上述第1金屬層之間；及第2金屬層，其設置於上述絕緣膜與上述第1金屬層之間。
  12. 如請求項11之半導體裝置，其中上述絕緣膜包含矽及氧，上述第2金屬層包含鈦及鉭之任一者。
TW110104997A 2020-08-06 2021-02-09 半導體裝置 TWI812922B (zh)

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