TW202008529A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW202008529A
TW202008529A TW107147241A TW107147241A TW202008529A TW 202008529 A TW202008529 A TW 202008529A TW 107147241 A TW107147241 A TW 107147241A TW 107147241 A TW107147241 A TW 107147241A TW 202008529 A TW202008529 A TW 202008529A
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semiconductor wafer
region
substrate
semiconductor
semiconductor device
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TW107147241A
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TWI720394B (zh
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松浦永悟
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日商東芝記憶體股份有限公司
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Abstract

實施形態提供一種可於不使用間隔晶片之情況下將一半導體晶片配置於另一半導體晶片上方從而縮小封裝尺寸之半導體裝置及其製造方法。 本實施形態之半導體裝置具備形成有電極之基板、設置於基板之表面上之第1及第2半導體晶片、將第1半導體晶片與電極連接之導線、接著層、及樹脂層。第2半導體晶片於朝向基板側之面即背面具有形成有突出部之第1區域及第1區域以外之第2區域，第2區域位於第1半導體晶片或導線之至少一部分之上方。接著層設置於第1區域與基板之間及第2區域與基板之間。樹脂層設置於基板上，且被覆第1及第2半導體晶片。

Description

半導體裝置及其製造方法
本實施形態係關於一種半導體裝置及其製造方法。
存在如記憶體晶片及其控制器晶片般將複數個半導體晶片密封於1個封裝內之情形。於該情形時，例如存在利用間隔晶片將記憶體晶片堆疊並重疊配置於控制器晶片上方之封裝構造。此種封裝構造可比將複數個半導體晶片單純地橫向並列配置而成之構造進一步縮小封裝整體之尺寸。
然而，為了將記憶體晶片堆疊而必需間隔晶片，因此成本增高。
又，於使用厚DAF(Die Attachment Film，晶片接著膜)代替間隔晶片之情形時，記憶體晶片變得容易傾斜。或者亦有記憶體晶片本身之形狀容易變形之虞。若記憶體晶片傾斜或者變形，則當於記憶體晶片上進而積層其他記憶體晶片時，所積層之記憶體晶片變得容易剝落而難以將接合線連接。又，有當DAF被壓扁時記憶體晶片會與其下方之控制器晶片接觸之虞。進而，亦存在當DAF被壓扁時，DAF自記憶體晶片之下方向接合墊伸出，之後難以將金屬導線與接合墊接合之情況。
實施形態提供一種可於不使用間隔晶片之情況下將一半導體晶片配置於另一半導體晶片上方從而縮小封裝尺寸之半導體裝置及其製造方法。
本實施形態之半導體裝置具備形成有電極之基板、設置於基板之表面上之第1及第2半導體晶片、將第1半導體晶片與電極連接之導線、接著層、及樹脂層。第2半導體晶片於朝向基板側之面即背面具有形成有突出部之第1區域及第1區域以外之第2區域，第2區域位於第1半導體晶片或導線之至少一部分之上方。接著層設置於第1區域與基板之間及第2區域與基板之間。樹脂層設置於基板上，且被覆第1及第2半導體晶片。
以下，參照圖式對本發明之實施形態進行說明。本實施形態並不限定本發明。於以下之實施形態中，上下方向表示把將半導體晶片安裝於基板之面設為上方之情形時之相對方向，存在與依據重力加速度之上下方向不同之情形。圖式係模式圖或概念圖，各部分之比率等未必與實物相同。於說明書與圖式中，對於關於已經出現過之圖式而於上文中說明過之要素相同之要素標註相同之符號，並適當省略詳細之說明。
(第1實施形態) 圖1(A)及圖1(B)係表示第1實施形態之半導體裝置1之構成例之剖視圖及俯視圖。半導體裝置1具備樹脂基板10、控制器晶片20、記憶體晶片30、接著層40、50、金屬導線60、70、及塑模樹脂80。本實施形態之半導體裝置1係面安裝型之半導體封裝，例如可為BGA(Ball Grid Array package，球柵陣列封裝)、LGA(Land Grid Array Package，焊盤網格陣列封裝)等。半導體裝置1例如亦可為NAND(Not AND，反及)型快閃記憶體等半導體記憶裝置。
作為基板之樹脂基板10例如可為將複數個絕緣層與複數個配線層(均未圖示)積層並一體化而成之多層配線基板。絕緣層例如使用玻璃環氧樹脂、有機高分子材料或陶瓷材料(例如氧化鋁(Al2 O3 ))等樹脂材料。配線層設置於樹脂基板10內，並電性連接於接合墊。配線層例如使用銅等低電阻之導電性材料。樹脂基板10之平面形狀並無特別限定，如圖1(B)所示，可為大致長方形或者大致正方形。
於樹脂基板10之表面上設置有接合墊12、14。金屬導線60、70接合於接合墊12、14。金屬導線60、70例如使用金。
作為第1半導體晶片之控制器晶片20利用接著層(DAF(Die Attachment Film))40接著並固定於樹脂基板10之表面上。控制器晶片20係控制記憶體晶片30之半導體晶片，且於半導體基板之表面設置有構成控制電路之半導體元件(例如電晶體等)。又，控制器晶片20具有連接於內部之控制電路之接合墊22，接合墊22藉由金屬導線60與樹脂基板10之接合墊12電性連接。
作為第2半導體晶片之記憶體晶片30利用接著層(DAF)50接著並固定於樹脂基板10之表面上。記憶體晶片30例如係具有NAND型閃速記憶體之半導體晶片，於半導體基板之表面上設置有平面型或立體型之記憶胞陣列。又，記憶體晶片30具有連接於內部電路之接合墊24，接合墊24藉由金屬導線70與樹脂基板10之接合墊14電性連接。藉此，記憶體晶片30經由金屬導線60、70及樹脂基板10之內部配線與控制器晶片20電性連接，並可接收控制器晶片20之控制來進行動作。
如圖1(A)所示，記憶體晶片30之背面具有於第1區域R1突出之突出部31。又，記憶體晶片30之背面具有於第1區域R1以外之背面之第2區域R2凹陷之凹部。於使突出部31接著於樹脂基板10之表面時，第2區域R2之凹部32係以重疊於將控制器晶片20與樹脂基板10之間連接之金屬導線60之至少一部分之上方之方式存在。此時，凹部32未與控制器晶片20及金屬導線60接觸。
接著層50設置於第1區域R1與樹脂基板10之間，將突出部31接著於樹脂基板10上。並且，接著層50亦設置於第2區域R2與樹脂基板10之間，將凹部32接著於樹脂基板10。又，位於第2區域R2與樹脂基板10之間之接著層50與金屬導線60之一部分及接合墊12接觸，並被覆該等。即，自樹脂基板10之表面上方觀察時，記憶體晶片30之第2區域R2與金屬導線60之至少一部分重疊。
如此一來，藉由於記憶體晶片30之背面設置突出部31及凹部32，可使記憶體晶片30不與控制器晶片20及金屬導線60接觸而是使記憶體晶片30之第2區域R2向控制器晶片20側突出。藉此，可使記憶體晶片30重疊於控制器晶片20或金屬導線60之上方，從而可縮小半導體裝置1之整體尺寸。
第2區域R2與第1區域R1中之記憶體晶片30之厚度差較佳為大於控制器晶片20之厚度使得即便使第2區域R2向控制器晶片20側突出，記憶體晶片30亦不會與控制器晶片20接觸。又，第2區域R2與第1區域R1中之記憶體晶片30之厚度差較佳為大於金屬導線60之高度使得即便使第2區域R2向控制器晶片20側突出，金屬導線60亦不會與控制器晶片20接觸。
塑模樹脂80設置於樹脂基板10上，且被覆控制器晶片20、記憶體晶片30、金屬導線60、70。塑模樹脂80保護控制器晶片20、記憶體晶片30、金屬導線60、70免受半導體裝置1之外部之損害。
如圖1(B)所示，第1區域R1位於第2區域R2之內側而並未伸出至第2區域R2之外側。又，如圖1(A)所示，於沿控制器晶片20及記憶體晶片30之排列方向切斷之剖面中，第2區域R2向自記憶體晶片30朝向控制器晶片20之第1方向D1及與第1方向D1相反之第2方向D2之兩者延伸。於該情形時，當接著層50自第1區域R1伸出時，第2區域R2接受所伸出之接著層50，從而可抑制接著層50向橫向擴展。即，於第2區域R2自記憶體晶片30之兩側向D1及D2方向延伸之情形時，接著層50於端部E1之第2區域R2與樹脂基板10之間、以及端部E2之第2區域R2與樹脂基板10之間被接受。
雖必須於靠近控制器晶片20之端部E1設置第2區域R2，但未必於遠離控制器晶片20之端部E2設置第2區域R2。即，第2區域R2未必必須向第2方向D2延伸。於該情形時，亦可使記憶體晶片30重疊於金屬導線60之上方。又，自第1區域R1之端部E1向D1方向伸出之接著層50可被第2區域R2接受而被覆金屬導線60之一部分。
再者，金屬導線60係於記憶體晶片30之接著前接合，因此接著層50可與接合墊12及金屬導線60接觸。毋寧可謂藉由接著層50被覆接合墊12及金屬導線60，而可使接著層50保護接合墊12及金屬導線60。
另一方面，於未於端部E2設置第2區域R2之情形時，存在自第1區域R1之端部E2向D2方向伸出之接著層50未被接受而向橫向擴展之情形。金屬導線70係於記憶體晶片30之接著後接合，因此若於搭載記憶體晶片30時接著層50伸出至接合墊14，則有無法使金屬導線70接合於接合墊14之虞。因此，第2區域R2較佳為亦設置於端部E2。然而，即便接著層50向橫向擴展，但只要不對接合墊14及金屬導線70造成影響，則第2區域R2亦可不設置於端部E2。
又，如圖1(B)所示，於自樹脂基板10之上方觀察之俯視下，第2區域R2亦可以包圍第1區域R1之方式設置於第1區域R1之整個外周。於該情形時，不僅向D1、D2方向伸出之接著層50，於背面F2面內向相對於D1、D2方向大致直行方向伸出之接著層50亦可於第2區域R2與樹脂基板10之間被接受。結果，可抑制接著層50過度擴展。
於本實施形態中，複數個記憶體晶片30分開設置於控制器晶片20之兩側。於該情形時，並未於控制器晶片20之正上方設置記憶體晶片30，因此於複數個記憶體晶片30間設置有塑模樹脂80。藉此，記憶體晶片30、控制器晶片20及金屬導線60、70由塑模樹脂80保護。金屬導線60之一部分與接合墊12由接著層50保護。
根據本實施形態，記憶體晶片30於背面之第1區域R1具有突出部31。於使突出部31接著於樹脂基板10之表面時，記憶體晶片30之第2區域R2於不與控制器晶片20接觸之情形時配置於金屬導線60之至少一部分之上方。於自樹脂基板10之表面上方觀察之俯視下，第2區域R2與金屬導線60之至少一部分重疊。藉此，相較於僅將控制器晶片20及記憶體晶片30橫向並列而成之封裝構造，依據本實施形態之封裝構造之尺寸減小。
進而，於記憶體晶片30之端部E1側之第2區域R2之下方設置有接著層50。藉此，接著層50被覆金屬導線60之一部分及接合墊12從而可保護該等。
又，可於端部E2側之第2區域R2之下方接受接著層50。藉此，於搭載記憶體晶片30時，接著層50不會自記憶體晶片30伸出至接合墊14，從而可抑制接合墊14之污染等。
進而，藉由將第2區域R2設置於第1區域R1之整個外周，可進而有效地抑制接著層50自記憶體晶片30伸出。
繼而，對本實施形態之半導體裝置1之製造方法進行說明。
圖2(A)~圖6(B)係表示第1實施形態之半導體裝置1之製造方法之一例之圖。再者，以下之半導體晶片之製造方法可應用於控制器晶片20及記憶體晶片30之任一者。
首先，如圖2(A)及圖2(B)所示，於半導體晶圓100之正面F1上形成半導體元件15。於各半導體晶片間設置切割線DL。再者，圖2(B)係圖2(A)之一部分之剖視圖。
繼而，如圖3(A)所示，將保護膠帶110貼附於半導體晶圓100之正面F1，如圖3(B)所示，通過CMP(Chemical Mechanical Polishing，化學機械研磨)法對半導體晶圓100之背面F2進行研磨。
繼而，如圖4(A)所示，利用修剪刀片TB對半導體晶圓100之背面F2之第2區域R2進行切削。藉此，形成於背面F2之第1區域R1突出之突出部31及於除此以外之背面F2之第2區域R2凹陷之凹部32。
繼而，如圖4(B)所示，將背面F2朝向接著層50而將半導體晶圓100搭載於具有接著層50之切割保護膠帶120上。進而，如圖5(A)所示，藉由將半導體晶圓100向切割保護膠帶120加壓，而使接著層50嵌入半導體晶圓100之凹部32內。
繼而，如圖5(B)所示，使用鐳射振盪器130對與半導體晶圓100之背面F2之切割線DL對應之部分照射鐳射。藉此，於半導體晶圓100之內部形成改質層LM。
繼而，如圖6(A)所示，利用上推部件140將切割保護膠帶120自下方往上推，藉此將切割保護膠帶120拉伸(使之延伸)。藉此，切割保護膠帶120與半導體晶圓100一起被朝向外方拉伸。此時，如圖6(B)所示，半導體晶圓100及接著層50沿著改質層LM(即沿著切割線)被劈開，從而被單片化成複數個半導體晶片。
之後，分別拾取半導體晶片(控制器晶片20及/或記憶體晶片30)並安裝於樹脂基板10上。
例如，將控制器晶片20安裝於樹脂基板10上。此時，如圖1所示，接著層40將控制器晶片20接著於樹脂基板10上。此時，亦可對接著層40進行加熱而將控制器晶片20接著於樹脂基板10上。
繼而，利用金屬導線60將控制器晶片20與樹脂基板10之接合墊12接合。
繼而，將記憶體晶片30安裝於樹脂基板10上。此時，如圖1所示，接著層50將記憶體晶片30接著於樹脂基板10上。亦可對接著層50進行加熱而將記憶體晶片30接著於樹脂基板10上。此時，利用接著層50將記憶體晶片30之突出部31接著於樹脂基板10之表面，並且將凹部32配置於金屬導線60之上方。
記憶體晶片30係以其端部E1突出至金屬導線60之上方之方式配置，並與金屬導線60之一部分重疊。藉此，可縮小半導體裝置1之尺寸。並且，記憶體晶片30之端部E1側之接著層50可將金屬導線60之一部分及接合墊12掩埋從而保護該等。
於本實施形態中，2個記憶體晶片30配置於控制器晶片20之兩側，且於控制器晶片20之兩側，接著層50保護金屬導線60及接合墊12。
繼而，藉由塑模樹脂80將控制器晶片20及記憶體晶片30密封。藉此，完成圖1所示之半導體裝置1之封裝。
根據本實施形態，於使記憶體晶片30之突出部31接著於樹脂基板10之表面時，可將記憶體晶片30之凹部32不與金屬導線60接觸而配置於其上方。藉此，不使用間隔晶片等便可使記憶體晶片30之一部分重疊於控制器晶片20之上方，而可縮小封裝構造之尺寸。
進而，於記憶體晶片30之端部E1側之第2區域R2之下方設置有接著層50。藉此，接著層50被覆金屬導線60之一部分及接合墊12，而可保護該等。
又，可於端部E2側之第2區域R2之下方接受接著層50。藉此，於搭載記憶體晶片30時，接著層50不會伸出至接合墊14，而可抑制接合墊14之污染等。
(變化例1) 圖7係表示第1實施形態之變化例1之半導體裝置1之製造方法之圖。於第1實施形態之製造方法中，如圖5(A)所示，利用接著層50填充凹部32後，藉由鐳射切割及延伸來使半導體晶片單片化。
然而，於變化例1中，進行刀片切割代替鐳射切割及延伸。於刀片切割中，使用圖7之切割刀片DB將切割線DL切斷。
修剪刀片之寬度(相對於旋轉面垂直之方向上之寬度)寬於切割刀片之寬度。因此，凹部32之寬度寬於切割線DL，且寬於利用切割刀片而切出之區域之寬度。藉此，即便於單片化後，於記憶體晶片30之背面F2亦殘留有突出部31及凹部32。
(變化例2) 圖8(A)~圖9(B)係表示依據第1實施形態之變化例2之半導體裝置1之製造方法之剖視圖。
於第1實施形態中，於進行修剪處理後進行半導體晶片之單片化。相對於此，於變化例2中，於進行半導體晶片之單片化後進行修剪處理。
首先，經過參照圖2(A)及圖2(B)所說明之步驟，如圖8(A)所示，利用切割刀片DB沿著切割線DL切至半導體晶圓100之中途(半切)。
繼而，如圖8(B)所示，將保護膠帶110貼附於半導體晶圓100之正面F1，如圖9(A)所示，藉由CMP法對半導體晶圓100之背面F2進行研磨。藉由該背面F2之研磨，而將半導體晶圓100單片化成半導體晶片。
之後，如圖9(B)所示，利用修剪刀片TB對半導體晶圓100之背面F2之第2區域R2進行切削。藉此，形成於背面F2之第1區域R1突出之突出部31及於除此以外之背面F2之第2區域R2凹陷之凹部32。進而，經過參照圖4(B)~圖5(A)所說明之步驟，形成半導體晶片。於變化例2中，無需圖5(B)及圖6(A)所示之鐳射切割及延伸之步驟。
之後，經過與第1實施形態相同之步驟，完成與第1實施形態相同之半導體裝置1。即便於如上所述般進行半導體晶片之單片化後進行修剪處理，亦可形成與第1實施形態相同之半導體裝置1。
(第2實施形態) 圖10係表示第2實施形態之半導體裝置2之構成例之剖視圖。於第2實施形態中，控制器晶片20係無需打線接合之倒裝晶片。於控制器晶片20為倒裝晶片之情形時，將具有半導體元件之表面朝向樹脂基板10接合。另一方面，控制器晶片20之背面與記憶體晶片30之凹部32對向。因此，即便接著層50被覆控制器晶片20，接著層50之應力亦不易施加至控制器晶片20之半導體元件。
因此，於第2實施形態中，於記憶體晶片30之端部E1側向D1方向突出之第2區域R2大於第1實施形態之於記憶體晶片30之端部E1側向D1方向突出之第2區域R2。記憶體晶片30之凹部32配置於控制器晶片20之上方。隨之，接著層50設置於控制器晶片20上。藉此，接著層50可保護控制器晶片20之一部分。
第2實施形態之其他構成可與第1實施形態之構成相同。又，第2實施形態之製造方法亦可與第1實施形態之製造方法相同。因此，第2實施形態可獲得與第1實施形態相同之效果。
(第3實施形態) 圖11係表示第3實施形態之半導體裝置3之構成例之剖視圖。於第3實施形態中，於記憶體晶片30之端部E1、E2，於突出部31與凹部32之間，將階差部33設置於第3區域R3。即，第3實施形態之記憶體晶片30之背面F2具有突出部31、階差部33、及凹部32之3段。階差部33及凹部32配置於金屬導線60及/或控制器晶片20之上方。
又，於圖11中，接著層50設置到階差部33為止，亦可設置到凹部32為止。於接著層50設置到階差部33為止之情形時，接著層50被覆金屬導線60。雖未圖示，但於接著層50設置到凹部32為止之情形時，接著層50被覆金屬導線60及控制器晶片20之一部分。於該情形時，接著層50可保護整個金屬導線60、金屬導線60與接合墊12之接合部、及金屬導線60與控制器晶片20之接合部。
即便如第3實施形態般設置階差部33，亦不會失去本實施形態之效果。又，藉由設置階差部33，即便使凹部32向D1方向延長，亦可維持記憶體晶片30之機械強度。再者，設置於突出部31與凹部32之間之階差部33之數量並無特別限定。因此，亦可將複數個階差部33呈階梯狀設置於突出部31與凹部32之間。
(第4實施形態) 圖12係表示第4實施形態之半導體裝置4之構成例之剖視圖。於第4實施形態中，於記憶體晶片30上進而積層其他記憶體晶片(第3半導體晶片)35。第4實施形態之其他構成可與第1實施形態相同。
可如上所述般於記憶體晶片30上積層記憶體晶片35。但是，記憶體晶片35之背面不具有突出部31及凹部32而是平坦。又，積層於記憶體晶片30上之記憶體晶片35之數量並無特別限定。即便如第4實施形態般於記憶體晶片30上積層其他記憶體晶片35，亦不會失去本實施形態之效果。
(第5實施形態) 圖13(A)及圖13(B)係表示第5實施形態之半導體裝置5之構成例之剖視圖及俯視圖。再者，於圖13(B)之俯視圖中，控制器晶片20僅示出其概略性之位置，並省略與金屬導線60等相關之圖示。
於第5實施形態中，記憶體晶片30於其背面F2具有複數個第1區域R1，且於各第1區域R1設置有突出部31。藉此，如圖1(A)所示，記憶體晶片30之背面F2於相對於樹脂基板10之表面垂直之剖面中形成為大致U形狀。記憶體晶片30係以橫跨控制器晶片20之上方之方式設置，且於控制器晶片20之兩側，突出部31利用接著層50被接著於樹脂基板10。控制器晶片20配置於2個突出部31間，且於其上方配置有凹部32。凹部32被覆控制器晶片20之表面上方。如上所述，記憶體晶片30亦可不左右分離而為一體型晶片。於記憶體晶片30為一體型之情形時，記憶體晶片30之機械強度及穩定性提高。因此，記憶體晶片30之彎曲得到抑制，從而可增大記憶體晶片35之積層數。
半導體裝置5只要變更半導體晶圓100之修剪處理之位置，便可與第1實施形態之半導體裝置1同樣地形成。例如，於第1實施形態之圖4(A)中，第2區域R2之凹部32只要形成於相鄰之切割線DL間即可。再者，修剪刀片TB之寬度設為小於各記憶體晶片30之寬度。藉此，於半導體晶片之中心部形成凹部32，於凹部32之兩側形成2個突出部31。切割線DL與突出部31之中間位置對應。因此，切割後，各半導體晶片形成為於其中心部具有凹部32且於凹部32之兩側具有2個突出部31之大致U形狀。關於上述變化例1，亦同樣地，只要變更半導體晶圓100之修剪處理之位置，便可製造半導體裝置5。
作為半導體裝置5之製造方法，亦存在如以下之製造方法。
圖14(A)及圖14(B)係表示第5實施形態之半導體裝置5之製造方法之剖視圖。例如，於經過參照圖2(A)~圖3(A)所說明之步驟後，使用修剪刀片如圖14(A)所示般，於切割線DL間之半導體晶片之中心部形成凹部32。
繼而，使用CMP法對半導體晶圓100之背面F2進行研磨。此時，對背面F2進行研磨直至半導體晶圓100之背面F2之突出部31成為所需高度為止。藉此，如圖14(B)所示，於凹部32之兩側形成2個突出部31。
之後，經過參照圖4(B)~圖7所說明之步驟，對半導體晶圓100進行切割。藉此，形成如圖13(A)所示之記憶體晶片30。可如上所述般形成凹部32後對背面F2進行研磨。
(第6實施形態) 圖15係表示第6實施形態之半導體裝置6之構成例之剖視圖。於第6實施形態中，於記憶體晶片30上進而積層其他記憶體晶片(第3半導體晶片)35。第6實施形態之其他構成可與第5實施形態相同。
可如上所述般於記憶體晶片30上積層其他記憶體晶片35。但是，記憶體晶片35之背面不具有突出部31及凹部32而是平坦。又，積層於記憶體晶片30上之記憶體晶片35之數量並無特別限定。即便如第6實施形態般於記憶體晶片30上積層其他記憶體晶片35，亦不會失去本實施形態之效果。
(第7實施形態) 圖16係表示第7實施形態之半導體裝置7之構成例之剖視圖。於第7實施形態中，於整個記憶體晶片30之背面F2與樹脂基板10之間設置有接著層50。即，接著層50不僅設置於突出部31與樹脂基板10之間，亦設置於凹部32與控制器晶片20或樹脂基板10之間。第7實施形態之其他構成可以與第5實施形態相同。
若如上所述般接著層50填滿記憶體晶片30之下方，則接著層50被覆整個控制器晶片20，因此對控制器晶片20施加大致均勻之應力。因此，第7實施形態即便於控制器晶片20並非為倒裝晶片型之情形時亦可應用。
第7實施形態亦可與第6實施形態進行組合。
已對本發明之若干實施形態進行了說明，但該等實施形態係作為例而提出，並無意圖限定發明之範圍。該等實施形態可以其他各種形態加以實施，且可於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，同樣地包含於申請專利範圍所記載之發明與其均等之範圍內。
[相關申請案] 本申請案享有以日本專利申請案2018-146821號(申請日：2018年8月3日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1‧‧‧半導體裝置2‧‧‧半導體裝置3‧‧‧半導體裝置4‧‧‧半導體裝置5‧‧‧半導體裝置6‧‧‧半導體裝置7‧‧‧半導體裝置10‧‧‧樹脂基板12‧‧‧接合墊14‧‧‧接合墊15‧‧‧半導體元件20‧‧‧控制器晶片22‧‧‧接合墊24‧‧‧接合墊30‧‧‧記憶體晶片31‧‧‧突出部32‧‧‧凹部33‧‧‧階差部35‧‧‧記憶體晶片40‧‧‧接著層50‧‧‧接著層60‧‧‧金屬導線70‧‧‧金屬導線80‧‧‧塑模樹脂100‧‧‧半導體晶圓110‧‧‧保護膠帶120‧‧‧切割保護膠帶130‧‧‧鐳射振盪器140‧‧‧上推部件D1‧‧‧第1方向D2‧‧‧第2方向DB‧‧‧切割刀片DL‧‧‧切割線E1‧‧‧端部E2‧‧‧端部F1‧‧‧正面F2‧‧‧背面LM‧‧‧改質層R1‧‧‧第1區域R2‧‧‧第2區域TB‧‧‧修剪刀片
圖1(A)及(B)係表示第1實施形態之半導體裝置之構成例之剖視圖及俯視圖。 圖2(A)~圖6(B)係表示第1實施形態之半導體裝置之製造方法之一例之圖。 圖7係表示第1實施形態之變化例1之半導體裝置之製造方法之圖。 圖8(A)~圖9(B)係表示依據第1實施形態之變化例2之半導體裝置之製造方法之剖視圖。 圖10係表示第2實施形態之半導體裝置之構成例之剖視圖。 圖11係表示第3實施形態之半導體裝置之構成例之剖視圖。 圖12係表示第4實施形態之半導體裝置之構成例之剖視圖。 圖13(A)及(B)係表示第5實施形態之半導體裝置之構成例之剖視圖及俯視圖。 圖14(A)及(B)係表示第5實施形態之半導體裝置之製造方法之剖視圖。 圖15係表示第6實施形態之半導體裝置之構成例之剖視圖。 圖16係表示第7實施形態之半導體裝置之構成例之剖視圖。
1‧‧‧半導體裝置
10‧‧‧樹脂基板
12‧‧‧接合墊
14‧‧‧接合墊
20‧‧‧控制器晶片
22‧‧‧接合墊
24‧‧‧接合墊
30‧‧‧記憶體晶片
31‧‧‧突出部
32‧‧‧凹部
40‧‧‧接著層
50‧‧‧接著層
60‧‧‧金屬導線
70‧‧‧金屬導線
80‧‧‧塑模樹脂
D1‧‧‧第1方向
D2‧‧‧第2方向
E1‧‧‧端部
E2‧‧‧端部
R1‧‧‧第1區域
R2‧‧‧第2區域

Claims (15)

  1. 一種半導體裝置，其具備： 基板，其形成有電極； 第1半導體晶片，其設置於上述基板之表面上； 導線，其將上述第1半導體晶片與上述電極連接； 第2半導體晶片，其設置於上述基板之表面上，於朝向上述基板側之面即背面具有形成有突出部之第1區域及上述第1區域以外之第2區域，上述第2區域位於上述第1半導體晶片或上述導線之至少一部分之上方； 接著層，其設置於上述第1區域與上述基板之間及上述第2區域與上述基板之間；及 樹脂層，其設置於上述基板上，且被覆上述第1及第2半導體晶片。
  2. 如請求項1之半導體裝置，其中上述接著層與上述第1半導體晶片或上述導線之至少一部分接觸。
  3. 如請求項1之半導體裝置，其中於沿上述第1及第2半導體晶片之排列方向切斷之剖面中，上述第2區域向自上述第2半導體晶片朝向上述第1半導體晶片之第1方向及相對於該第1方向為相反側之第2方向之兩者延伸， 上述接著層設置於自上述第2半導體晶片向上述第1方向延伸之上述第2區域與上述基板之間、以及自上述第2半導體晶片向上述第2方向延伸之上述第2區域與上述基板之間。
  4. 如請求項1之半導體裝置，其中上述第2區域設置於上述第2半導體晶片之上述第1區域之整個外周。
  5. 如請求項1之半導體裝置，其中複數個上述第2半導體晶片分開設置於上述第1半導體晶片之兩側，且 於複數個上述第2半導體晶片間設置有上述樹脂層。
  6. 如請求項1之半導體裝置，其中上述第2半導體晶片具有複數個上述第1區域，且遍及上述第1半導體晶片之上方而設置， 上述第1半導體晶片配置於上述複數個第1區域間。
  7. 一種半導體裝置，其具備： 基板，其形成有電極； 第1半導體晶片，其設置於上述基板之表面上； 導線，其將上述第1半導體晶片與上述電極連接； 第2半導體晶片，其設置於上述基板之表面上，於朝向上述基板側之面即背面具有形成有突出部之第1區域及上述第1區域以外之第2區域，上述第2區域位於上述第1半導體晶片或上述導線之至少一部分之上方； 接著層，其設置於上述第1區域與上述基板之間及上述第2區域與上述基板之間，且與上述第1半導體晶片或上述導線之至少一部分接觸；及 樹脂層，其設置於上述基板上，且被覆上述第1及第2半導體晶片；且 於沿上述第1及第2半導體晶片之排列方向切斷之剖面中，上述第2區域向自上述第2半導體晶片朝向上述第1半導體晶片之第1方向及相對於該第1方向為相反側之第2方向之兩者延伸， 複數個上述第2半導體晶片分開設置於上述第1半導體晶片之兩側。
  8. 一種半導體裝置，其具備： 基板，其形成有電極； 第1半導體晶片，其設置於上述基板之表面上； 導線，其將上述第1半導體晶片與上述電極連接； 第2半導體晶片，其設置於上述基板之表面上，於朝向上述基板側之面即背面具有形成有突出部之第1區域及上述第1區域以外之第2區域，上述第2區域位於上述第1半導體晶片或上述導線之至少一部分之上方； 接著層，其設置於上述第1區域與上述基板之間及上述第2區域與上述基板之間，且與上述第1半導體晶片或上述導線之至少一部分接觸；及 樹脂層，其設置於上述基板上，且至少被覆上述第2半導體晶片；且 於沿上述第1及第2半導體晶片之排列方向切斷之剖面中，上述第2區域向自上述第2半導體晶片朝向上述第1半導體晶片之第1方向及相對於該第1方向為相反側之第2方向之兩者延伸， 上述第2半導體晶片具有複數個上述第1區域，且遍及上述第1半導體晶片之上方而設置， 上述第1半導體晶片配置於上述複數個第1區域之間。
  9. 如請求項1至8中任一項之半導體裝置，其中上述第2區域與上述第1區域之厚度差大於上述第1半導體晶片之厚度。
  10. 如請求項7或8之半導體裝置，其進而具備積層於上述第2半導體晶片上之第3半導體晶片。
  11. 一種半導體裝置之製造方法，其包括如下步驟： 於形成有電極之基板設置第1半導體晶片； 利用導線將上述第1半導體晶片與上述電極連接； 將半導體晶圓之元件形成面之相反面即背面之一部分切削，而形成於該背面之第1區域突出之突出部、及於上述第1區域以外之上述背面之第2區域凹陷之凹部； 以填埋上述半導體晶圓之凹部之方式於該背面設置接著層； 將上述半導體晶圓切斷，並單片化成第2半導體晶片； 利用上述接著層將第2半導體晶片之上述突出部接著於基板之表面，並且將上述第2半導體晶片之上述凹部配置於設置於該第2半導體晶片之下之第1半導體晶片或上述導線之上方；及 利用樹脂層被覆上述基板上之至少第2半導體晶片。
  12. 如請求項11之半導體裝置之製造方法，其中於形成上述突出部與上述凹部之步驟中，上述凹部係包含將上述第2半導體晶片單片化之切斷線之區域。
  13. 如請求項11之半導體裝置之製造方法，其中形成上述突出部與上述凹部時所使用之修剪刀片比將上述半導體晶圓單片化成上述第2半導體晶片時所使用之切割刀片寬。
  14. 如請求項11之半導體裝置之製造方法，其中於形成上述突出部與上述凹部後，對上述半導體晶圓進行切割而單片化成複數個上述第2半導體晶片。
  15. 如請求項11之半導體裝置之製造方法，其中於形成上述突出部與上述凹部之前，對上述半導體晶圓進行切割並對上述半導體晶圓之背面進行研磨，藉此將上述半導體晶圓單片化成複數個上述第2半導體晶片。
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