TW202401722A - 半導體裝置及其製造方法 - Google Patents
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Abstract
本發明之實施形態提供一種可抑制裂痕之影響之半導體裝置及其製造方法。 本實施形態之半導體裝置包含:基板、第1半導體晶片、第2半導體晶片、接著層、及構件。基板具有第1面。第1半導體晶片設置於第1面上。第2半導體晶片設置於第1半導體晶片之上方,具有第1面及與第1半導體晶片對向之第2面,自大致垂直於第1面之方向觀察,被覆第1半導體晶片。接著層設置於第2面與第1面及第1半導體晶片之間。構件自大致垂直於第1面之方向觀察,設置於接著層之外周之至少一部分。
Description
本實施形態係關於一種半導體裝置及其製造方法。
於半導體裝置之封裝構造中,有時以利用較厚之DAF(Die Attach Film,晶片黏結薄膜)覆蓋基板上之控制器晶片之方式,配置記憶體晶片。
本發明所欲解決之問題在於提供一種可抑制裂痕之影響之半導體裝置及其製造方法。
本實施形態之半導體裝置包含:基板、第1半導體晶片、第2半導體晶片、接著層、及構件。基板具有第1面。第1半導體晶片設置於第1面上。第2半導體晶片設置於第1半導體晶片之上方,具有第1面及與第1半導體晶片對向之第2面,自大致垂直於第1面之方向觀察,被覆第1半導體晶片。接著層設置於第2面與第1面及第1半導體晶片之間。構件自大致垂直於第1面之方向觀察,設置於接著層之外周之至少一部分。
以下,參照圖式說明本發明之實施形態。本實施形態並非係限定本發明者。於以下之實施形態中,配線基板之上下方向表示將供搭載半導體晶片之面設為上時之相對方向,有時與依照重力加速度之上下方向不同。圖式係示意性或概念性圖式,各部分之比率等未必限定於與實物相同。於說明書與圖式中,對與關於已出現之圖式所前述之要素同樣之要素賦予同一符號,且適宜省略詳細之說明。
(第1實施形態) 圖1係顯示第1實施形態之半導體裝置1之構成之一例之剖視圖。半導體裝置1具備:配線基板10、半導體晶片20、30~33、接著層40~43、構件50、接著層60、接合線90、及密封樹脂91。半導體裝置1例如係NAND型快閃記憶體之封裝。
配線基板10可為包含配線層(未圖示)及絕緣層(未圖示)之印刷基板或中介層。對於配線層,例如使用銅、鎳或其等之合金等低電阻金屬。對於絕緣層,例如使用玻璃環氧樹脂等絕緣性材料。配線基板10可具有將複數個配線層及複數個絕緣層積層而構成之多層配線構造。配線基板10例如可如中介層般具有貫通其正面與背面之貫通電極(未圖示)。
於配線基板10之正面(上表面)即面F10a,設置連接於配線層之焊墊10p1、10p2。面F10a係第1面之一例。
於配線基板10之背面(下表面)設置有金屬凸塊13。金屬凸塊13係為了電性連接未圖示之其他零件與配線基板10而設置。
半導體晶片20設置於配線基板10之正面(面F10a)側。半導體晶片20經由接著層21接著於配線基板10。半導體晶片20例如係控制記憶體晶片之控制器晶片。於半導體晶片20中與朝向配線基板10之面為相反側之面(正面)設置有未圖示之半導體元件。半導體元件例如可為構成控制器之CMOS(Complementary Metal Oxide Semiconductor,互補式金屬氧化物半導體))電路。接合線22電性連接設置於配線基板10之正面之焊墊10p2與設置於半導體晶片20之正面之焊墊(未圖示)。
於半導體晶片20之上方經由接著層40接著半導體晶片30。半導體晶片30例如係包含NAND型快閃記憶體之記憶體晶片。半導體晶片30於其正面具有半導體元件(未圖示)。半導體元件例如可為記憶胞陣列及其周邊電路(CMOS電路)。記憶胞陣列可為將複數個記憶胞三維配置之立體型記憶胞陣列。又,於半導體晶片30上經由接著層41接著半導體晶片31。於半導體晶片31上經由接著層42接著半導體晶片32。於半導體晶片32上經由接著層43接著半導體晶片33。半導體晶片31~33例如與半導體晶片30同樣地為包含NAND型快閃記憶體之記憶體晶片。半導體晶片30~33可為同一記憶體晶片。於圖中,除作為控制器晶片之半導體晶片20外,亦積層有4個作為記憶體晶片之半導體晶片30~33。然而,半導體晶片之積層數可為3以下,亦可為5以上。
更詳細而言,半導體晶片30具有面F30a、及面F30a之相反側之面F30b,且於面F30a具有接著層40。面F30a係配線基板10之面F10a、及與半導體晶片20對向之面。面F30a係第2面之一例。面F30b係第3面之一例。
又,接著層40較接著層41~43為厚,設置為將半導體晶片20及接合線22埋入(被覆)。亦即,接著層40設置於半導體晶片30之面F30a與配線基板10之面F10a及半導體晶片20之間。又,接著層40之側面與位於面F30a與面F30b之間之半導體晶片30之側面大致平行。亦即,接著層40之寬度與半導體晶片30之寬度大致相同。此外,寬度係大致平行於面F10a之方向之寬度。此乃為了如參照圖3A~圖3E後續說明般,將貼附有接著層之晶圓藉由切割而單片化。
構件50設置於接著層40之外周。構件50經由接著層60接著於配線基板10。此外,針對構件50之配置之細節,參照圖2,後續進行說明。又,於圖1所示之例中,構件50之上表面之高度與半導體晶片30之面F30a之高度大致相同。
接合線90連接於配線基板10、半導體晶片30~33之任意之焊墊。為了以接合線90連接,而半導體晶片30~33挪移焊墊之份額而積層。
更詳細而言,接合線90將設置於配線基板10之正面之焊墊10p1、與設置於半導體晶片30~33之正面之焊墊(未圖示)之間電性連接。
進而,密封樹脂(樹脂層)91將半導體晶片20、30~33、接著層40~43、60、構件50、接合線90等密封。藉此,半導體裝置1將複數個半導體晶片20、30~33於配線基板10上構成為1個半導體封裝。
圖2係顯示圖1之配線基板10、半導體晶片20、接著層40及構件50之位置關係之一例之俯視圖。圖2係自圖1之紙面上方觀察平行於圖1所示之面F30a之面(參照圖1之A-A線)之圖。
自大致垂直於面F10a之方向觀察到之接著層40之外緣(半導體晶片30之外緣)係較半導體晶片20之外緣靠外側。亦即,半導體晶片30自大致垂直於面F10a之方向觀察,設置為被覆(覆蓋)半導體晶片20。
構件50自大致垂直於面F10a之方向觀察設置於接著層40之外周。更詳細而言,構件50設置為沿接著層40之外周覆蓋接著層40之外周。亦即,構件50設置於接著層40與密封樹脂91之間。
又,構件50係由強度較密封樹脂91為高之材料構成。強度例如為拉伸強度、彎曲強度、及硬度。構件50之拉伸強度例如大於10 kgf/mm
2。藉此,可抑制產生裂痕。
接著層40例如係熱固性接著劑。接著層40之主成分例如係壓克力系樹脂。接著層40之熱膨脹係數例如於常溫下為約70 ppm/℃,於260℃下為約120 ppm/℃。此外,接著層40之構成材料不限於上述。
密封樹脂91例如係熱固性樹脂。密封樹脂91之主成分例如係環氧樹脂。密封樹脂91之熱膨脹係數例如於常溫下為約9 ppm/℃,於260℃下為約36 ppm/℃。密封樹脂91之彎曲強度例如於30℃下為約170 MPa,於260℃下為約19 MPa。此外,密封樹脂91之構成材料不限於上述。
構件50例如由矽(Si)構成。此外,構件50之構成材料不限於矽,例如只要為強度較密封樹脂91為高之材料即可。又,構件50更佳為由可加工成任意之形狀之材料構成。構件50例如可由樹脂構成。
其次,針對半導體裝置之製造方法進行說明。
圖3A~圖3E顯示將貼附有接著層40之晶圓W單片化為半導體晶片30之步序。圖4A~圖4F顯示在配線基板10上設置半導體晶片20、30及構件50之步序。
圖3A~圖3E係顯示第1實施形態之半導體裝置1之製造方法之一例之圖。
如圖3A所示,準備形成有複數個半導體元件部之矽晶圓W(以下稱為晶圓)。晶圓W包含:具備半導體元件部之第3面、及於Z軸方向上與第3面分開之第4面。其次,於晶圓W之第3面之上接著表面保護帶110。
其次,如圖3B所示,使晶圓W反轉,對晶圓W之第4面使用研削磨石120進行研削,而使其後退。該步序係所謂之BSG(Back Side Grinding,背面研磨)步序。
其次,如圖3C所示,使晶圓W反轉,將晶圓W之第4面接著於貼合於切割環130之上之接著樹脂。接著樹脂之1例係DAF(Die Attach Film,晶粒黏結薄膜)140a。
其次,如圖3D所示,自晶圓W之第3面剝落表面保護帶110。
其次,如圖3E所示,使用刀片150切割晶圓W。於晶圓W形成切割線160。切割線160沿X軸方向及Y軸方向之各方向形成。晶圓W被分離成複數個半導體晶片30。
此外,作為第2接著層之DAF 140a與晶圓W一起被單片化,成為作為第1接著層之接著層40。
圖4A~圖4F係顯示第1實施形態之半導體裝置1之製造方法之一例之圖。圖4A~圖4F之左側顯示俯視圖。圖4A~圖4F之右側顯示側視圖。
如圖4A所示,經由接著層21,於配線基板10之面F10a上設置(安裝)半導體晶片20。接著層21預先貼附於半導體晶片20。之後,形成接合線22。此外,省略接著層21、接合線22及焊墊10p2等。
其次,如圖4B所示,將藉由圖3A~圖3E之步序而單片化之半導體晶片30經由接著層40設置於配線基板10之面F10a上。更詳細而言,半導體晶片30設置為設置於面F30a之接著層40將半導體晶片20及接合線22埋入(被覆)。
此外,如上述般,接著層40之側面與位於面F30a與面F30b之間之半導體晶片30之側面大致平行。亦即,接著層40之寬度與半導體晶片30之寬度大致相同。
其次,如圖4C所示,經由接著層60,於配線基板10之面F10a上設置構件5。接著層60預先貼附於構件51。構件51例如沿半導體晶片30之1個邊(短邊)設置。構件51係構件50之一部分。
其次,如圖4D所示,經由接著層60於配線基板10之面F10a上設置構件52。接著層60預先貼附於構件52。構件52例如沿半導體晶片30之1個邊(長邊)設置。構件52係構件50之一部分。
其次,如圖4E所示,經由接著層60,於配線基板10之面F10a上設置構件53。接著層60預先貼附於構件53。構件53例如沿半導體晶片30之1個邊(短邊)設置。構件53係構件50之一部分。
其次,如圖4F所示,經由接著層60,於配線基板10之面F10a上設置構件54。接著層60預先貼附於構件54。構件54例如沿半導體晶片30之1個邊(長邊)設置。構件54係構件50之一部分。
如圖4F所示,沿半導體晶片30之所有之邊(接著層40之外周)設置構件51~54。構件51~54對應於圖2所示之構件50。此外,設置構件51~54之順序不限於圖4C~圖4F所示之例。
如以上般,根據第1實施形態,構件50自大致垂直於面F10a之方向觀察設置於接著層40之外周。構件50由於由強度較密封樹脂91為高之材料構成,故可抑制產生因應力集中所致之裂痕,可抑制裂痕之影響。
(比較例) 圖5係顯示比較例之半導體裝置1a之構成之一例之剖視圖。比較例就不設置構件50及接著層60之點,與第1實施形態不同。
於圖5所示之例中,有時產生裂痕C。接著層40與密封樹脂91之間之區域可能成為由於因溫度變化產生之應力之集中而產生之裂痕C之起點。於圖5所示之例中,裂痕C有可能以半導體晶片30與接著層40及密封樹脂91之邊界部分為起點而產生。
若裂痕C延展至配線基板10,則對配線基板10內之配線造成影響,有可能產生斷線不良等電氣不良。
針對於此,於第1實施形態中,藉由設置構件50,而可抑制接著層40與密封樹脂91之接觸。藉由將強度較密封樹脂91為高之構件50設置於接著層40之周圍、亦即接著層40與密封樹脂91之間,而可抑制產生裂痕。
此外,於圖4F所示之例中,構件51~54大致無間隙的設置。然而,構件50可於接著層40之外周之一部分中不設置。因此,構件50自大致垂直於面F10a之方向觀察,可設置於接著層40之外周之至少一部分。
例如,根據接著層40之材料、構造或形狀等,因溫度變化(膨脹)造成之應力之影響有可能發生變化。其結果,根據接著層40與密封樹脂91之接觸位置,裂痕之易產生度有時改變。該情形下,可於容易產生裂痕之位置配置構件50,於其他部位不配置構件50。例如,於圖4B~圖4F中,在預先知悉於半導體晶片30之短邊部分中容易產生裂痕等之不良之情形下,可設置沿短邊配置之構件51、53,不設置構件52、54。
(變化例) 圖6係顯示變化例之配線基板10、半導體晶片30及構件50之位置關係之一例之俯視圖。
配線基板10有時具有:於內部設置配線之區域A1、及於內部未設置配線之區域A2。於圖6中,區域A2係區域A1以外之配線基板10上之區域。即便裂痕延展至區域A2,亦不會產生斷線不良。因此,構件50自大致垂直於面F10a之方向觀察,可不設置於接著層40之區域A2側之外周(半導體晶片30之區域A2側之邊)。藉此,可抑制構件50之材料成本。於圖6所示之例中,半導體晶片20之左側之短邊側係區域A2。因此,構件50不設置於半導體晶片20之左側之短邊側。
(第2實施形態) 圖7係顯示第2實施形態之半導體裝置1之構成之一例之剖視圖。於第2實施形態中,與第1實施形態進行比較,構件50之上表面之高度不同。
構件50之上表面之高度較半導體晶片30之面F30a之高度為高。更詳細而言,構件50之上表面之高度係半導體晶片30之面F30b之高度。構件50作為支持設置於半導體晶片30上之半導體晶片31之間隔件發揮功能。藉此,可於向半導體晶片31之接合線90之形成時支撐半導體晶片31。其結果,可抑制於打線接合時施加之加重及應力之影響,可抑制產生裂痕。
第2實施形態之半導體裝置1之其他構成由於與第1實施形態之半導體裝置之對應之構成同樣,故省略其詳細之說明。第2實施形態之半導體裝置1可獲得與第1實施形態同樣之效果。
(第3實施形態) 圖8係顯示第3實施形態之半導體裝置1之構成之一例之剖視圖。於第3實施形態中,與第1實施形態進行比較,構件50之上表面之高度不同。
構件50之上表面之高度較半導體晶片30之面F30a為低。該情形下,可減小構件50之體積,抑制材料成本。
即便於產生圖5所示之裂痕C之情形下,藉由構件50覆蓋配線基板10之面F10a,亦可使裂痕C不致到達配線基板10。亦即,第3實施形態之構件50作為配線基板10中之配線保護構件發揮功能。藉此,可抑制裂痕C之影響。
構件50例如自接著層40之外周設置至焊墊10p1。構件50為了保護配線,較佳為於面F10a之平行方向遍及更寬廣之範圍設置。然而,於焊墊10p1位處之方向(圖8之紙面左右方向)上,構件50較佳為以不與接合線90接觸之方式設置至焊墊10p1之近前。
第3實施形態之半導體裝置1之其他構成由於與第1實施形態之半導體裝置1之對應之構成同樣,故省略其詳細之說明。第3實施形態之半導體裝置1可獲得與第1實施形態同樣之效果。
說明了本發明之若干個實施形態,但該等實施形態係作為例子而提出者,並非意欲限定發明之範圍。該等實施形態可以其他各種形態實施,在不脫離本發明之要旨之範圍內能夠進行各種省略、置換、變更。該等實施形態及其變化係與包含於發明之範圍及要旨內同樣地,包含於申請專利範圍所記載之發明及其均等之範圍內。 [相關申請案之參考]
本發明申請案享有以日本專利申請案2022-093908號(申請日:2022年6月9日)為基礎申請案之優先權。本發明申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1,1a:半導體裝置
10:配線基板
10p1,10p2:焊墊
13:金屬凸塊
20,30,31,32,33:半導體晶片
21,40,41,42,43,60:接著層
22,90:接合線
50,51,52,53,54:構件
91:密封樹脂
110:表面保護帶
120:研削磨石
130:切割環
140a:DAF
150:刀片
160:切割線
A-A:線
A1:區域
C:裂痕
F10a,F30a,F30b:面
W:晶圓
圖1係顯示第1實施形態之半導體裝置之構成之一例之剖視圖。 圖2係顯示圖1之配線基板、半導體晶片、接著層及構件之位置關係之一例之俯視圖。 圖3A係顯示第1實施形態之半導體裝置之製造方法之一例之圖。 圖3B係顯示連續於圖3A之半導體裝置之製造方法之一例之圖。 圖3C係顯示連續於圖3B之半導體裝置之製造方法之一例之圖。 圖3D係顯示連續於圖3C之半導體裝置之製造方法之一例之圖。 圖3E係顯示連續於圖3D之半導體裝置之製造方法之一例之圖。 圖4A係顯示第1實施形態之半導體裝置之製造方法之一例之圖。 圖4B係顯示連續於圖4A之半導體裝置之製造方法之一例之圖。 圖4C係顯示連續於圖4B之半導體裝置之製造方法之一例之圖。 圖4D係顯示連續於圖4C之半導體裝置之製造方法之一例之圖。 圖4E係顯示連續於圖4D之半導體裝置之製造方法之一例之圖。 圖4F係顯示連續於圖4E之半導體裝置之製造方法之一例之圖。 圖5係顯示比較例之半導體裝置之構成之一例之剖視圖。 圖6係顯示變化例之配線基板、半導體晶片及構件之位置關係之一例之俯視圖。 圖7係顯示第2實施形態之半導體裝置之構成之一例之剖視圖。 圖8係顯示第3實施形態之半導體裝置之構成之一例之剖視圖。
1:半導體裝置
10:配線基板
10p1,10p2:焊墊
13:金屬凸塊
20,30,31,32,33:半導體晶片
21,40,41,42,43,60:接著層
22,90:接合線
50:構件
91:密封樹脂
A-A:線
F10a,F30a,F30b:面
Claims (12)
- 一種半導體裝置,其包含: 基板,其具有第1面; 第1半導體晶片,其設置於前述第1面上; 第2半導體晶片,其設置於前述第1半導體晶片之上方,具有前述第1面及與前述第1半導體晶片對向之第2面,自大致垂直於前述第1面之方向觀察,被覆前述第1半導體晶片; 第1接著層,其設置於前述第2面與前述第1面及前述第1半導體晶片之間;及 構件,其自大致垂直於前述第1面之方向觀察,設置於前述第1接著層之外周之至少一部分。
- 如請求項1之半導體裝置,其中前述第1接著層包含壓克力。
- 如請求項1之半導體裝置,其進一步包含樹脂層,該樹脂層設置於前述第1面上,被覆前述第2半導體晶片、前述第1接著層、及前述構件;且 前述構件之拉伸強度較前述樹脂層之拉伸強度為高。
- 如請求項3之半導體裝置,其中前述樹脂層包含環氧樹脂。
- 如請求項1之半導體裝置,其中前述構件之上表面之高度為前述第2面之高度以上。
- 如請求項5之半導體裝置,其中前述構件之上表面之高度為與前述第2面為相反側之前述第2半導體晶片之第3面之高度。
- 如請求項6之半導體裝置,其進一步包含設置於前述第2半導體晶片上之第3半導體晶片;且 前述構件支持前述第3半導體晶片。
- 如請求項1之半導體裝置,其中前述構件之上表面之高度較前述第2面為低。
- 如請求項8之半導體裝置,其進一步包含: 焊墊,其設置於前述基板之前述第1面;及 引線,其電性連接前述焊墊與前述第2半導體晶片;且 前述構件自前述第1接著層之外周設置至前述焊墊。
- 如請求項1之半導體裝置,其中前述基板具有:於內部設置配線之第1區域、及於內部不設置配線之第2區域;且 前述構件自大致垂直於前述第1面之方向觀察,不設置於前述第1接著層之前述第2區域側之外周。
- 一種半導體裝置之製造方法,其包含: 於基板之第1面上設置第1半導體晶片; 以設置於第2半導體晶片之第2面之第1接著層被覆前述第1半導體晶片之方式,於前述第1面上設置前述第2半導體晶片;及 自大致垂直於前述第1面之方向觀察,於前述第1接著層之外周之至少一部分設置構件。
- 如請求項11之半導體裝置之製造方法,其進一步包含: 在具有形成有半導體元件之第3面、及與前述第3面為相反側之第4面的晶圓之前述第4面設置第2接著層;及 藉由將前述晶圓與前述第2接著層一起單片化,而形成在前述第2面設置有前述第1接著層之前述第2半導體晶片。
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