TWI673852B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI673852B
TWI673852B TW107124040A TW107124040A TWI673852B TW I673852 B TWI673852 B TW I673852B TW 107124040 A TW107124040 A TW 107124040A TW 107124040 A TW107124040 A TW 107124040A TW I673852 B TWI673852 B TW I673852B
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Taiwan
Prior art keywords
wafer
semiconductor
functional layer
laminated
wafers
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TW107124040A
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English (en)
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TW201941397A (zh
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河崎一茂
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日商東芝記憶體股份有限公司
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Publication of TWI673852B publication Critical patent/TWI673852B/zh
Publication of TW201941397A publication Critical patent/TW201941397A/zh

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Abstract

本發明之實施形態提供能夠小型化及低成本化之半導體裝置及其製造方法。 本發明之實施形態之半導體裝置具備：基座構件；第1積層體，其包含交替積層於與上述基座構件之表面交叉之第1方向之第1半導體晶片與第2半導體晶片；及第2積層體，其於沿上述基座構件之上述表面之第2方向與上述第1積層體並排配置，且包含交替積層於上述第1方向之其他第1半導體晶片與其他第2半導體晶片。上述第1積層體包含與上述基座構件連接之最下層之第1半導體晶片，上述第2積層體包含與上述基座構件連接之最下層之第2半導體晶片。

Description

半導體裝置及其製造方法
實施形態係關於半導體裝置及其製造方法。
例如存在如下半導體記憶體器件，其具有將積層於基板上之複數個半導體記憶體晶片樹脂鑄模之構造。此種半導體裝置中，隨著記憶容量之大容量化，晶片之積層數增大，從而器件之尺寸變大，並且製造成本上升。
本發明之實施形態提供能夠小型化及低成本化之半導體裝置及其製造方法。
本發明之實施形態之半導體裝置具備：基座構件；第1積層體，其包含交替積層於與上述基座構件之表面交叉之第1方向之第1半導體晶片與第2半導體晶片；及第2積層體，其於沿上述基座構件之上述表面之第2方向與上述第1積層體並排配置，且包含交替積層於上述第1方向之其他第1半導體晶片與其他第2半導體晶片。上述第1積層體包含與上述基座構件連接之最下層之第1半導體晶片，上述第2積層體包含與上述基座構件連接之最下層之第2半導體晶片。
以下，參照圖式對實施形態進行說明。對圖式中之相同部分附上相同編號並適當省略其詳細說明，且對不同部分進行說明。再者，圖式為模式性或概念性之圖，各部分之厚度與寬度之關係、部分間之大小比率等未必與現實情形相同。又，即便於表示相同部分之情形時，也存在根據圖式之不同而不同地表示相互之尺寸或比率之情形。
進而，使用各圖中所示之X軸、Y軸及Z軸對各部分之配置及構成進行說明。X軸、Y軸、Z軸相互正交，分別表示X方向、Y方向、Z方向。又，存在將Z方向設為上方，且將其相反方向設為下方進行說明之情形。
圖1及圖2係表示實施形態之半導體裝置1之模式圖。圖1係表示半導體裝置1之構造之剖視圖，圖2係表示半導體裝置1之上表面之模式俯視圖。
半導體裝置1為例如大容量之非揮發性記憶裝置，包含基座構件10、積層體20A、及積層體20B。積層體20A及20B配置於基座基座構件10之上。
積層體20A及20B於沿基座構件10之上表面之X方向上並排配置。積層體20A及20B分別包含有於與基座構件10之上表面交叉之方向上，例如於Z方向上交替積層之複數個半導體晶片CA與複數個半導體晶片CB。積層體20A及20B例如樹脂鑄模於基座構件10之上。
積層體20A包含位於與基座構件10連接之最下層之半導體晶片CA。又，積層體20B包含位於與基座構件10連接之最下層之半導體晶片CB。
如圖1所示，半導體裝置1進而包含邏輯晶片30。邏輯晶片30例如經由倒裝晶片凸塊（以下，FC凸塊33)連接於基座構件10之下表面。
基座構件10為例如安裝基板，包含連接焊墊13、配線15、導通孔接點17。配線15設置於基座構件10之上表面側，連接焊墊13設置於基座構件10之下表面側。導通孔接點17從基座構件10之下表面向上表面貫通，將連接焊墊13與配線15電性連接。
半導體晶片CA及CB分別包含導通孔接點21及23。導通孔接點21及23例如以將半導體晶片CA及CB各自之基板從背面向表面貫通之方式設置。導通孔接點21及23分別與半導體晶片CA及CB之功能層（參照圖3）連接。積層體20A及20B分別包含之半導體晶片CA及CB經由導通孔接點21及23相互電性連接。
如圖1所示，最下層之半導體晶片CA及CB例如分別經由連接凸塊43而與配線15電性連接。即，連接凸塊43將最下層之半導體晶片CA及CB之導通孔接點21及23分別連接於配線15。
邏輯晶片30經由連接有FC凸塊33之連接焊墊13及導通孔接點17而與配線15電性連接。由此，積層體20A與邏輯晶片30之間、及積層體20B與邏輯晶片30之間電性連接。
半導體裝置1進而包含配置於基座構件10之下表面之連接構件，例如焊料凸塊50。焊料凸塊50設置於連接焊墊13上，經由導通孔接點17與配線15電性連接。焊料凸塊50電性連接於例如與連接於積層體20A及20B之配線15不同之配線15。焊料凸塊50例如與外部電路連接，將外部電路與邏輯晶片30電性連接。
如圖2所示，積層體20A以於Z方向觀察與邏輯晶片30之一部分重疊之方式配置。又，積層體20B以於Z方向觀察與邏輯晶片30之另一部分重疊之方式配置。
例如，積層體20A及20B之導通孔接點21及23配置於邏輯晶片30之上方。由此，能夠將積層體20A及20B與邏輯晶片30之間以最短距離連接。
圖3及圖4係表示實施形態之半導體裝置1之構成之模式圖。圖3係表示半導體裝置1之部分剖面之模式圖。圖4係表示半導體晶片CA及CB之端子配置之模式圖。
如圖3所示，半導體晶片CA包含半導體基板SS、功能層FLA、及接合層WBL。又，半導體晶片CB包含半導體基板SS、功能層FLB、及接合層WBL。又，於半導體晶片CA及CB之背面（與功能層FL為相反側之面）分別設置有連接焊墊45或者連接焊墊47。
如圖3所示，半導體晶片CA及CB以各自之接合層WBL對向之方式接合。積層體20A具有將貼合半導體晶片CA及CB而成之積層晶片SC1於Z方向積層之構造。積層體20B具有將貼合半導體晶片CA及CB而成之積層晶片SC2於Z方向積層之構造。
積層晶片SC1以具有隔著連接焊墊47設置於半導體晶片CA之背面上之連接凸塊43之方式構成。而且，積層體20A以半導體晶片CB之背面（與功能層FLB為相反側之面）與半導體晶片CA之背面經由連接凸塊43、連接焊墊45及47連接之方式構成。
積層晶片SC2以具有隔著連接焊墊47設置於半導體晶片CB之背面之連接凸塊43之方式構成。而且，積層體20B以半導體晶片CB之背面與半導體晶片CA之背面經由連接凸塊43、連接焊墊45及47連接之方式構成。
如此，藉由將半導體晶片CA與半導體晶片CB隔著接合層WBL貼合，與將所有晶片隔著連接凸塊積層之情形相比，可縮小積層體20A及20B之尺寸（高度）。由此，可使半導體裝置1小型化。
再者，圖3中，省略貫通半導體晶片CA及CB之導通孔接點21及23。又，積層體20A及20B分別經由基座構件10之連接焊墊13、配線15及導通孔接點17而與邏輯晶片30及焊料凸塊50連接。
如圖4所示，半導體晶片CA及CB分別具有資料端子0〜7、及指令端子0〜3。半導體晶片CA之資料端子及指令端子為例如導通孔接點21，半導體晶片CB之資料端子及指令端子為例如導通孔接點23。半導體晶片CA及CB之資料端子及指令端子與邏輯晶片30之資料端子及指令端子連接。
例如，資料端子及指令端子沿半導體晶片CA及CB各自之外緣並排配置為一列。又，半導體晶片CA及CB以各自之資料端子及指令端子以最短距離對向之方式配置。於X方向上鄰接之半導體晶片CA及CB具有沿相互對向之側面配置之資料端子及指令端子，以於X方向上排列兩者之資料端子，且排列兩者之指令端子之方式配置。
進而，於貼合於半導體晶片CA之上之半導體晶片CB中，資料端子配置於與下層之資料端子連接之位置，指令端子配置於與下層之指令端子連接之位置。於貼合於半導體晶片CB之上之半導體晶片CA中也相同。
如此，於積層體20A及20B中，藉由將資料端子及指令端子分別配置於特定區域，而積層體20A及20B與邏輯晶片30之間之連接變得容易。
例如，圖14及圖15所示之半導體裝置2具有如下構造，即，於基座構件10之上配置積層體20A及20B，且於基座構件10之背面側配置邏輯晶片30。積層體20A及20B均具有將積層晶片SC1於Z方向上積層之構造。又，積層體20A及20B經由基座構件10之連接焊墊13、配線15及導通孔接點17與邏輯晶片30連接。
如圖15所示，於半導體裝置2中，沿鄰接之半導體晶片CA之相互相向之側面配置之資料端子及指令端子之配列於Y方向上反轉。因此，產生資料端子及指令端子於X方向上鄰接配置之部分。因此，將積層體20A及20B之端子與邏輯晶片30之端子連接之配線較圖4所示之半導體裝置1變得更複雜。
即，無法使積層體20A及20B之端子配列與邏輯晶片30之端子配列一致，例如，必須將基座構件10之配線15變更為能夠相互連接之圖案。又，作為邏輯晶片30，必須使用配合積層體20A及20B之端子配列而對端子配列進行了變更之專用晶片。因此，製造成本上升。
本實施形態之半導體裝置1中，能夠配合邏輯晶片30之端子配列而配列積層體20A及20B之資料端子及指令端子，從而可降低製造成本。
圖5〜圖8係表示實施形態之半導體裝置1中所包含之半導體晶片CA及CB之模式剖視圖。例如，若區分包括有無連接凸塊43之構成，則半導體裝置1包含4種半導體晶片CA1、CA2、CB1及CB2。
如圖5〜圖8所示，接合層WBL包含接合焊墊51與絕緣膜53。接合焊墊51例如與功能層FLA或者FLB電性連接。絕緣膜53為例如氧化矽膜，保護功能層FLA或者FLB。功能層FLA及FLB包含例如NAND型記憶體元件之記憶單元陣列及周邊電路。
如圖5及圖7所示，半導體晶片CA1及CB1於背面側具有連接凸塊43。另一方面，圖6及圖8所示之半導體晶片CA2及CB2於背面側不具有連接凸塊43。
積層體20A包含將半導體晶片CA1與半導體晶片CB2貼合而成之積層晶片SC1。積層體20B包含將半導體晶片CA2與半導體晶片CB1貼合而成之積層晶片SC2。
其次，參照圖9〜圖13對實施形態之半導體裝置1之製造方法進行說明。圖9〜圖13係依序表示半導體裝置1之製造過程之模式剖視圖。再者，圖9〜圖13中也省略導通孔接點21及23。
如圖9所示，形成包含功能層FLA與功能層FLB之晶圓100。功能層FLA及功能層FLB為例如形成於半導體基板SS之上之記憶體元件。功能層FLA及功能層FLB沿半導體基板SS之表面交替配置。
進而，形成覆蓋功能層FLA及FLB之接合層WBL。接合層WBL包含例如接合焊墊51及絕緣膜53。接合焊墊51為包含例如銅之金屬層。絕緣膜53為例如氧化矽膜。
如圖10所示，形成於半導體基板SS之背面具有連接凸塊43之晶圓110。晶圓110為於晶圓100之背面形成有連接凸塊43者。連接凸塊43例如經由連接焊墊47與半導體基板SS之背面連接。連接凸塊43例如使用焊料材等連接構件形成。連接焊墊47為包含例如銅等之金屬層。連接凸塊43並不限定於焊料材，例如，也可使用較連接焊墊47為低熔點之金屬材料。
又，於半導體基板SS之背面上形成有間隔件SA。間隔件SA為例如樹脂構件。藉由配置間隔件SA，可將使用連接凸塊43連接之積層晶片SC1或者SC2之相互之間隔保持於固定(參照圖1）。
如圖11所示，形成於半導體基板SS之背面具有連接焊墊45之晶圓120。連接焊墊45為包含例如銅等之金屬層。晶圓120為於晶圓100之背面形成有連接焊墊45者。
如圖12所示，將晶圓110與晶圓120貼合。例如，以晶圓110之接合層WBL與晶圓120之接合層WBL對向之方式配置之後，使晶圓110與晶圓120接觸，並藉由例如於高溫下加壓而將兩者貼合。
此時，藉由晶圓110之接合焊墊51與晶圓120之接合焊墊51接觸，又兩者之絕緣膜53接觸而進行貼合。又，晶圓110與晶圓120以功能層FLA與功能層FLB對向之方式接合。
如圖13所示，將貼合之晶圓110與晶圓120藉由例如切片機切斷而切出積層晶片SC1及SC2。其後，藉由於基座構件10之上隔著連接凸塊43積層複數個積層晶片SC1而形成積層體20A。同樣，藉由將複數個積層晶片SC2隔著連接凸塊43積層而形成積層體20B（參照圖1）。
上述製造方法中，可藉由將例如於X方向及Y方向中之至少1個方向交替配置功能層FLA與功能層FLB之2片晶圓100貼合而形成積層晶片SC1及SC2。由此，能以低成本製造半導體裝置1。例如，為了製作包含功能層FLA之晶圓、及包含功能層FLB之晶圓之2種晶圓，必須使用2個遮罩組，但於本實施形態之製造方法中，可使用1個遮罩組製作積層晶片SC1及SC2。
對本發明之幾個實施形態進行了說明，但該等實施形態係作為示例提出者，並未意圖限定發明之範圍。該等新穎之實施形態能夠以其他各種形態實施，且可於不脫離發明要旨之範圍進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或要旨中，並且包含於申請專利範圍中所記載之發明及其均等之範圍。
[相關申請案] 本申請案享有以日本專利申請案2018-55029號（申請日：2018年3月22日）為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1、2‧‧‧半導體裝置
10‧‧‧基座構件
13、45、47‧‧‧連接焊墊
15‧‧‧配線
17、21、23‧‧‧導通孔接點
20A、20B‧‧‧積層體
30‧‧‧邏輯晶片
33‧‧‧FC凸塊
43‧‧‧連接凸塊
50‧‧‧焊料凸塊
51‧‧‧接合焊墊
53‧‧‧絕緣膜
100、110、120‧‧‧晶圓
CA、CA1、CA2、CB、CB1、CB2‧‧‧半導體晶片
FLA、FLB‧‧‧功能層
SS‧‧‧半導體基板
SA‧‧‧間隔件
SC1‧‧‧積層晶片
SC2‧‧‧積層晶片
WBL‧‧‧接合層
X‧‧‧軸
Y‧‧‧軸
Z‧‧‧軸
圖1及圖2係表示實施形態之半導體裝置之模式圖。 圖3及圖4係表示實施形態之半導體裝置之構成之模式圖。 圖5〜圖8係表示實施形態之半導體裝置中所包含之半導體晶片之模式剖視圖。 圖9〜圖13係表示實施形態之半導體裝置之製造方法之模式剖視圖。 圖14及圖15係表示比較例之半導體裝置之構成之模式圖。

Claims (7)

  1. 一種半導體裝置，其具備： 基座構件； 第1積層體，其包含交替積層於與上述基座構件之表面交叉之第1方向之第1半導體晶片與第2半導體晶片；及 第2積層體，其於沿上述基座構件之上述表面之第2方向與上述第1積層體並排配置，且包含交替積層於上述第1方向之其他第1半導體晶片與其他第2半導體晶片；且 上述第1積層體包含與上述基座構件連接之最下層之第1半導體晶片， 上述第2積層體包含與上述基座構件連接之最下層之第2半導體晶片。
  2. 如請求項1之半導體裝置，其中上述第1半導體晶片及上述第2半導體晶片分別具有半導體基板、及設置於上述半導體基板上之功能層， 上述第1積層體及上述第2積層體包含：第1接合部，其使上述第1半導體晶片之功能層與上述第2半導體晶片之功能層相向接合；及第2接合部，其使上述第1半導體晶片之半導體基板與上述第2半導體晶片之半導體基板相向接合。
  3. 如請求項2之半導體裝置，其中上述第1半導體晶片及上述第2半導體晶片分別具有：接合焊墊，其設置於上述功能層上；及連接焊墊，其設置於上述半導體基板之與上述功能層為相反側之背面側；且 上述第1接合部包含將上述第1半導體晶片之接合焊墊與上述第2半導體晶片之接合焊墊直接連接之部分， 上述第2接合部包含將上述第1半導體晶片之連接焊墊與上述第2半導體晶片之連接焊墊經由連接構件連接之部分。
  4. 如請求項1至3中任一項之半導體裝置，其進而具備與上述第1積層體及上述第2積層體電性連接之第3半導體晶片， 上述第3半導體晶片具有指令端子與資料端子， 上述第1積層體及上述第2積層體分別具有與上述指令端子連接之第1端子、及與上述資料端子連接之第2端子， 上述第1積層體之第1端子與上述第2積層體之第1端子於上述第2方向上並排配置， 上述第1積層體之第2端子與上述第2積層體之第2端子於上述第2方向上並排配置。
  5. 一種半導體裝置之製造方法，其形成具有第1面及與上述第1面為相反側之第2面之第1晶圓，該第1面包含第1功能層、及與上述第1功能層交替並排配置之第2功能層， 形成具有第1面、及與上述第1面為相反側之第2面，且具有配置於上述第2面上之複數個連接構件之第2晶圓，該第1面包含第1功能層、及與上述第1功能層交替並排配置之第2功能層， 形成晶圓接合體，該晶圓接合體係以將上述第1晶圓之第1功能層與上述第2晶圓之第2功能層接合，且將上述第1晶圓之第2功能層與上述第1晶圓之第1功能層接合之方式，貼合上述第1晶圓之第1面與上述第2晶圓之第1面而成， 將上述晶圓接合體分割為複數個第1積層晶片與複數個第2積層晶片，該等複數個第1積層晶片分別包含上述第1晶圓之第1功能層、及與上述第1晶圓之第1功能層接合之上述第2晶圓之第2功能層，該等複數個第2積層晶片分別包含上述第2晶圓之第1功能層、及與上述第2晶圓之第1功能層接合之上述第1晶圓之第2功能層。
  6. 如請求項5之半導體裝置之製造方法，其中上述第1積層晶片及上述第2積層晶片具有作為上述第1晶圓之一部分之第1基板、及作為上述第2晶圓之一部分之第2基板， 上述複數個連接構件以上述第1積層晶片及上述第2積層晶片之各者於與上述第1功能層或者上述第2功能層為相反側之上述第2基板之背面側，具有上述複數個連接導體之一部分之方式配置。
  7. 如請求項5或6之半導體裝置之製造方法，其中將包含複數個上述第1積層晶片之第1積層體、及包含複數個上述第2積層晶片之第2積層體形成於基座構件上。
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