TW201511213A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 126
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 93
- 239000002184 metal Substances 0.000 claims abstract description 93
- 229920005989 resin Polymers 0.000 claims abstract description 91
- 239000011347 resin Substances 0.000 claims abstract description 91
- 238000007789 sealing Methods 0.000 claims abstract description 26
- 230000002093 peripheral effect Effects 0.000 claims abstract description 24
- 235000012431 wafers Nutrition 0.000 claims description 21
- 238000005520 cutting process Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000010030 laminating Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 19
- 230000015654 memory Effects 0.000 description 8
- 238000000465 moulding Methods 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000004840 adhesive resin Substances 0.000 description 4
- 229920006223 adhesive resin Polymers 0.000 description 4
- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract
本發明提供一種難以剝離為了謀求散熱性之提高而露出之金屬板之半導體裝置。
本發明提供一種包括金屬板1、複數個半導體晶片3、絕緣層6a、配線層6b、外部連接端子19、及密封樹脂部2之半導體裝置10。金屬板1具有呈方形形狀之第1面1a。複數個半導體晶片3係積層於金屬板1之第2面1g上。絕緣層6a及配線層6b係相對於半導體晶片3而設置於金屬板1之相反側。外部連接端子19係相對於絕緣層6a及配線層6b而設置於半導體晶片3之相反側。密封樹脂部2係使金屬板1之第1面1a露出,並且密封半導體晶片3。金屬板1之自第1面1a之外周邊連續之外周面中的至少1個對向之2個面係由密封樹脂部2覆蓋。
Description
本申請案係享受以日本專利申請2013-189846號(申請日:2013年9月12日)為基礎申請之優先權。本申請案係藉由參照該基礎申請而包含基礎申請之所有內容。
本發明之實施形態係關於一種半導體裝置及其製造方法。
使用有積層複數個半導體晶片並以樹脂模製部密封之半導體裝置。例如,為了謀求散熱性之提高或強度提高,而使用於金屬板上,積層複數個半導體晶片,亦包含金屬板在內而以樹脂模製部密封之半導體裝置。
為了謀求半導體裝置之散熱性之提高,存在使金屬板之一部分自樹脂模製部露出之情形。於使金屬板露出之情形時,期望防止金屬板之剝離而謀求半導體裝置之可靠性之提高。
本發明之一實施形態之目的在於提供一種難以剝離為了謀求散熱性之提高而露出之金屬板之半導體裝置。
根據本發明之一實施形態,提供一種包括金屬板、複數個半導體晶片、絕緣層、配線層、外部連接端子、及密封樹脂部之半導體裝置。金屬板具有呈方形形狀之第1面。複數個半導體晶片係積層於金屬板之第1面之相反面即第2面上。絕緣層及配線層係相對於半導體晶
片而設置於金屬板之相反側。外部連接端子係相對於絕緣層及配線層而設置於半導體晶片之相反側。密封樹脂部係使金屬板之第1面露出,並且密封複數個半導體晶片。金屬板之自第1面之外周邊連續之外周面中的至少1個對向之2個面由密封樹脂部覆蓋。
1‧‧‧金屬板
1a‧‧‧第1面
1b~1e‧‧‧外周面
1f‧‧‧溝槽
1g‧‧‧第2面
2‧‧‧樹脂模製部(密封樹脂部)
3‧‧‧半導體記憶體(半導體晶片)
4‧‧‧第1底填充樹脂(密封樹脂部)
5‧‧‧第2底填充樹脂(密封樹脂部)
6‧‧‧配線基板(支持基板)
6a‧‧‧絕緣層
6b‧‧‧配線層
8、9‧‧‧凸塊
10‧‧‧半導體裝置
11‧‧‧接著性樹脂
12‧‧‧邏輯LSI(半導體晶片)
13‧‧‧切割線
15‧‧‧接著劑
19‧‧‧凸塊(外部連接端子)
20、21‧‧‧模具
22‧‧‧膜
30、50‧‧‧半導體裝置
A-A‧‧‧線
B-B‧‧‧線
C-C‧‧‧線
D-D‧‧‧線
S1~S23‧‧‧步驟
圖1係第1實施形態之半導體裝置之俯視圖。
圖2係沿著圖1所示之A-A線之箭視剖面圖。
圖3係沿著圖1所示之B-B線之箭視剖面圖。
圖4係用以說明圖1所示之半導體裝置之製造步驟之流程圖。
圖5係表示圖1所示之半導體裝置之製造步驟之一步驟的圖。
圖6係表示圖1所示之半導體裝置之製造步驟之一步驟的圖。
圖7係表示圖1所示之半導體裝置之製造步驟之一步驟的圖。
圖8係表示圖1所示之半導體裝置之製造步驟之一步驟的圖。
圖9係表示圖1所示之半導體裝置之製造步驟之一步驟的圖。
圖10係表示圖1所示之半導體裝置之製造步驟之一步驟的圖。
圖11係表示圖1所示之半導體裝置之製造步驟之一步驟的圖。
圖12係表示圖1所示之半導體裝置之製造步驟之一步驟的圖。
圖13係表示圖1所示之半導體裝置之製造步驟之一步驟的圖。
圖14係第2實施形態之半導體裝置之俯視圖。
圖15係沿著圖14所示之C-C線而觀察之箭視剖面圖。
圖16係沿著圖14所示之D-D線而觀察之箭視剖面圖。
圖17係用以說明製造圖14所示之半導體裝置時之切割線之剖面圖。
圖18係第3實施形態之半導體裝置之剖面圖。
圖19係用以說明圖18所示之半導體裝置之製造步驟之流程圖。
圖20係表示圖18所示之半導體裝置之製造步驟之一步驟的圖。
圖21係表示圖18所示之半導體裝置之製造步驟之一步驟的圖。
以下,參照隨附圖式,詳細地對實施形態之半導體裝置及其製造方法進行說明。再者,本發明並不由該等實施形態限定。
圖1係第1實施形態之半導體裝置10之俯視圖。圖2係沿著圖1所示之A-A線之箭視剖面圖。圖3係沿著圖1所示之B-B線之箭視剖面圖。半導體裝置10包括金屬板1、半導體記憶體(半導體晶片)3、邏輯LSI(Large Scale Integration,大型積體電路)(半導體晶片)12、配線基板(支持基板)6、及樹脂模製部2。
金屬板1係使用有鋁或42合金等金屬之板構件。金屬板1具有呈長方形形狀之第1面1a。複數個半導體記憶體3係積層於金屬板1之第1面1a之相反面即第2面1g上。半導體記憶體3為記憶元件,例如為NAND(Not AND,反及)快閃記憶體。
相對於金屬板1直接積層之半導體記憶體3係使用接著劑15而接著至第2面1g。所積層之半導體記憶體3彼此係藉由接著性樹脂11而接著。半導體記憶體3彼此係隔著凸塊8而電性連接。
於最遠離金屬板1之半導體記憶體3,積層邏輯LSI12。邏輯LSI12與半導體記憶體3係隔著凸塊8而電性連接。邏輯LSI12係對資訊向半導體記憶體3之寫入或自半導體記憶體3之讀出進行控制之控制元件,例如為NAND控制器或NAND I/F(Interface,介面)控制LSI。
於半導體記憶體3彼此之間隙及半導體記憶體3與邏輯LSI12之間隙,填充有第1底填充樹脂4。藉由填充第1底填充樹脂4,而更牢固地固定金屬板1、半導體記憶體3、及邏輯LSI12。於金屬板1之第2面1g,以包圍所積層之半導體記憶體3之方式形成有溝槽1f。溝槽1f係於填充第1底填充樹脂4時,抑制第1底填充樹脂4自金屬板1之第2面1g
溢出。再者,於以下之說明中,將於金屬板1積層有半導體記憶體3及邏輯LSI12者亦稱為第1積層體。
配線基板6具有樹脂製之絕緣層6a、及金屬製之配線層6b。絕緣層6a具有核心層及增層。於配線基板6上,使形成於最上層(於圖2及圖3中為最下層)之半導體晶片對向而搭載第1積層體,本實施形態係使邏輯LSI12對向而搭載第1積層體。於最遠離金屬板1之半導體記憶體3與配線基板6之間,設置凸塊9。形成於配線基板6之配線層6b與半導體記憶體3係隔著凸塊9而電性連接。於第1積層體與配線基板6之間隙,填充第2底填充樹脂5。藉由填充第2底填充樹脂5,而更牢固地固定第1積層體與配線基板6。再者,於以下之說明中,將於配線基板6上搭載有第1積層體者亦稱為第2積層體。
於配線基板6中之搭載第1積層體之面之相反面,形成作為外部連接端子之凸塊19。凸塊19係與配線基板6之配線層6b電性連接。因此,凸塊19係隔著配線層6b或凸塊9而與半導體記憶體3電性連接。
配線基板1中之搭載第1積層體之面、及第1積層體之周圍係由樹脂製之樹脂模製部2密封。金屬板1中之第1面1a係自樹脂模製部2露出。金屬板1之自第1面1a之外周邊連續之所有外周面1b~1e係由樹脂模製部2覆蓋。包含金屬板1、樹脂模製部2、及配線基板6而形成呈長方體形狀之長方體部。作為外部連接端子之凸塊19係形成於長方體部之1個面。再者,於以下之說明中,將第1底填充樹脂4、第2底填充樹脂5、及樹脂模製部2亦統稱為密封樹脂部。
再者,於第1底填充樹脂4、第2底填充樹脂5、及樹脂模製部2,以線膨脹係數之調整等為目的而含有氧化矽粒子。此處,第1底填充樹脂4及第2底填充樹脂5之氧化矽粒子之含量少於樹脂模製部2而富於流動性。因此,易於順利地向半導體記憶體3彼此之間隙、或第1積層體與配線基板6之間隙填充第1底填充樹脂4及第2底填充樹脂5。
根據上述半導體裝置10,金屬板1之第1面1a係自樹脂模製部2露出,因此可較第1面1a由樹脂模製部覆蓋之半導體裝置更謀求薄型化。又,金屬板1之第1面1a係自樹脂模製部2露出,因此可易於使自半導體記憶體3或邏輯LSI12產生之熱經由金屬板1而散熱。
又,金屬板1之自第1面1a之外周邊連續之所有外周面1b~1e係由樹脂模製部2覆蓋,因此可藉由樹脂模製部2而更牢固地固定金屬板1。又,若直接對金屬板1之外周面1b~1e施加力,則金屬板1變得易於剝離,但本實施形態係外周面1b~1e之全部由樹脂模製部2覆蓋,因此變得難以對外周面1b~1e施加剝離金屬板1之力。藉此,可謀求半導體裝置10之可靠性之提高。
其次,對半導體裝置10之製造方法進行說明。圖4係用以說明圖1所示之半導體裝置10之製造步驟之流程圖。圖5~圖13係表示圖1所示之半導體裝置10之製造步驟之一步驟的圖。
首先,使半導體記憶體3藉由接著劑15而接著至金屬板1之第2面1g上(步驟S1,參照圖5)。其次,使半導體記憶體3積層於接著至第2面1g上之半導體記憶體3上(步驟S2,參照圖6)。於積層半導體記憶體3時,使用凸塊8而將各個半導體記憶體3間電性連接。其次,使邏輯LSI12積層於最遠離金屬板1之半導體記憶體3上(步驟S3,參照圖6)。於積層邏輯LSI12時,使用凸塊8而將邏輯LSI12與半導體記憶體3間電性連接。其次,使第1底填充樹脂4填充至半導體記憶體3彼此之間隙、及半導體記憶體3與邏輯LSI12之間隙(步驟S4,參照圖7)。藉由至此為止之步驟而形成第1積層體。
其次,使積層於最上層之半導體晶片即邏輯LSI12對向而使複數個第1積層體搭載至配線基板6上(步驟S5,參照圖8)。於將第1積層體搭載至配線基板6上時,使用凸塊9而將第1積層體與配線基板6間電性連接。其次,使第2底填充樹脂5填充至第1積層體與配線基板6之間隙
(步驟S6,參照圖8)。藉由該步驟而形成第2積層體。
其次,於用以形成樹脂模製部2之模具20、21中之與金屬板1之第1面1a對向之面,配置膜22(步驟S7,參照圖9)。膜22係例如為了使半導體裝置10易於自模具20、21脫模而使用之脫模膜。
其次,於與金屬板1之第1面1a之間夾持膜22而將第2積層體配置於模具20、21之間,然後關閉模具20、21(步驟S8,參照圖10)。其次,向模具20、21之內部填充樹脂而形成樹脂模製部2(步驟S9,參照圖11)。其次,自模具20、21取出形成有樹脂模製部2之第2積層體(步驟S10,參照圖11),形成作為外部連接端子之凸塊19(步驟S11,參照圖12)。其次,於第1積層體間進行切割而將半導體裝置10單片化(步驟S12,參照圖13)。根據以上之步驟,製造半導體裝置10。再者,於上述步驟中,省略形成凸塊8、9或接著性樹脂11之步驟之詳細內容,但只要於製造半導體記憶體3時、或積層步驟前等適當之時點進行該等形成即可。
本實施形態係由樹脂模製部2覆蓋金屬板1之外周面1b~1e之全部,故步驟S12之切割步驟之切割線13係與金屬板1之第1面1a之外周邊平行,且通過成為金屬板1之外側之位置。
根據上述半導體裝置10之製造步驟,於金屬板1之第1面1a與模具20之間夾持有膜22,故樹脂變得難以侵入至第1面1a上,從而可使第1面1a更確實地自樹脂模製部2露出。
又,存在如下情形:因第2積層體或模具20、21之製造誤差等,而於模具20與第1面1a之間形成間隙。若於模具20與第1面1a之間形成間隙,則存在如下情形:於步驟S9中,樹脂侵入至模具20與第1面1a之間,從而第1面1a由樹脂模製部2覆蓋。本實施形態係夾持於模具20與第1面1a之膜22彈性變形,藉此可由膜22吸收模具20與第1面1a之距離之不均。因此,可由膜22覆蓋金屬板1之第1面1a,而更確實地防止
樹脂侵入至模具20與第1面1a之間。藉此,可謀求半導體裝置10之製造步驟之良率之提高。
其次,對第2實施形態之半導體裝置30進行說明。圖14係第2實施形態之半導體裝置30之俯視圖。圖15係沿著圖14所示之C-C線而觀察之箭視剖面圖。圖16係沿著圖14所示之D-D線而觀察之箭視剖面圖。圖17係用以說明製造圖14所示之半導體裝置30時之切割線之剖面圖。再者,對與上述實施形態相同之構成標示相同之符號而省略詳細之說明。
於本實施形態中,由樹脂模製部2覆蓋金屬板1之自外周邊連續之4個外周面1b~1e中之一對向的外周面1b、1c,另一對向之外周面1d、1e自樹脂模製部2露出。
由樹脂模製部2覆蓋一對向之外周面1b、1c,藉此難以剝離金屬板1,並且使另一對向之外周面1d、1e自樹脂模製部2露出,藉此可謀求樹脂模製部2之小型化、即俯視時之半導體裝置30之小型化。
尤其,本實施形態係由樹脂模製部2覆蓋金屬板1之自第1面1a之外周邊中之短邊連續的外周面1b、1c,使自長邊連續之外周面1d、1e自樹脂模製部2露出。對自短邊連續之外周面1b、1c施加力之情形較對自長邊連續之外周面1d、1e施加力的情形更具有易於剝離金屬板1之傾向,故由樹脂模製部2覆蓋保護自長邊連續之外周面1d、1e。又,與上述實施形態相同地,金屬板1之第1面1a自樹脂模製部2露出,因此可謀求散熱性之提高。
再者,於製造半導體裝置30之情形時,只要使平行於金屬板1之第1面1a之長邊之切割線13(亦參照圖17)通過與金屬板1重疊之位置,使平行於短邊之切割線13通過成為金屬板1之外側之位置即可(亦參照圖13)。又,於使半導體裝置30於金屬板1之第1面1a之長邊方向上小
型化之情形時,亦可使自短邊連續之外周面1b、1c自樹脂模製部2露出,由樹脂模製部2覆蓋自長邊連續之外周面1d、1e。
其次,對第3實施形態之半導體裝置50進行說明。圖18係第3實施形態之半導體裝置50之剖面圖。再者,對與上述實施形態相同之構成標示相同之符號而省略詳細之說明。
半導體裝置50係密封樹脂部(第1底填充樹脂4)較金屬板1之第1面1a更突出。例如,於捆包半導體裝置50時,可於密封樹脂部之突出部分承受自金屬板1之第1面1a側所施加之負重而防止對金屬板1施加負荷。藉此,金屬板1變得難以剝離,並且亦可抑制對積層於金屬板1之半導體記憶體3施加之負重,故可謀求可靠性之提高。
又,與上述實施形態相同地,金屬板1之第1面1a自密封樹脂部露出,因此可謀求散熱性之提高。再者,於俯視時,金屬板1變得小於半導體記憶體3。
其次,對半導體裝置50之製造步驟進行說明。圖19係用以說明圖18所示之半導體裝置50之製造步驟之流程圖。圖20~21係表示圖18所示之半導體裝置50之製造步驟之一步驟的圖。至圖4所示之步驟S11之前係與第1實施形態所示之製造步驟相同。
本實施形態係於步驟S11後,對金屬板1之第1面1a側進行蝕刻(步驟S22,參照圖20)。此處,將金屬板1蝕刻至形成於金屬板1之第2面1g之溝槽1f部分之金屬板1的厚度以上。
其次,進行切割而將半導體裝置50單片化(步驟S23,參照圖21)。此處,使進行切割時之切割線13通過與處於金屬板1之溝槽1f部分之部分重疊的位置。藉此,可使密封樹脂部較金屬板1之第1面1a更突出。又,可由密封樹脂部覆蓋金屬板1之外周面1b~1e之周圍而難以剝離金屬板1。又,可於處於金屬板1之溝槽1f部分之部分重疊切割
線13,因此於金屬板1之外周面1b~1e之周圍殘留密封樹脂部(樹脂模製部2),故與使切割線13通過未蝕刻之金屬板1之外側之情形(參照圖1或圖14)相比,可謀求俯視時之半導體裝置50之更進一步之小型化。又,由於蝕刻金屬板1,因此可謀求半導體裝置50之薄型化。
雖對本發明之幾個實施形態進行了說明,但該等實施形態係作為例而揭示者,並不意圖限定發明之範圍。該等新穎之實施形態可藉由其他各種形態而實施,且可於不脫離發明之主旨之範圍內,進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨,並且包含於專利申請範圍所記載之發明及其均等之範圍。
1‧‧‧金屬板
1a‧‧‧第1面
1b‧‧‧外周面
1c‧‧‧外周面
1f‧‧‧溝槽
1g‧‧‧第2面
2‧‧‧樹脂模製部(密封樹脂部)
3‧‧‧半導體記憶體(半導體晶片)
4‧‧‧第1底填充樹脂(密封樹脂部)
5‧‧‧第2底填充樹脂(密封樹脂部)
6‧‧‧配線基板(支持基板)
6a‧‧‧絕緣層
6b‧‧‧配線層
8、9‧‧‧凸塊
10‧‧‧半導體裝置
11‧‧‧接著性樹脂
12‧‧‧邏輯LSI(半導體晶片)
15‧‧‧接著劑
19‧‧‧凸塊(外部連接端子)
Claims (6)
- 一種半導體裝置,其包括:金屬板,其具有呈方形形狀之第1面;複數個半導體晶片,其等積層於上述金屬板之上述第1面之相反面即第2面上;絕緣層及配線層,其等相對於上述半導體晶片而設置於上述金屬板之相反側;外部連接端子,其相對於上述絕緣層及上述配線層而設置於上述半導體晶片之相反側;及密封樹脂部,其使上述金屬板之上述第1面露出,並且密封上述複數個半導體晶片;且上述金屬板之自上述第1面之外周邊連續之外周面中的至少1個對向之2個面由上述密封樹脂部覆蓋。
- 如請求項1之半導體裝置,其中上述外部連接端子係設置於呈長方體形狀之長方體部之1個面,於上述長方體部,包含上述金屬板及上述絕緣層。
- 如請求項1或2之半導體裝置,其中上述金屬板之上述第1面係呈長方形形狀,自其短邊連續之外周面係由上述密封樹脂部覆蓋,自其長邊連續之外周面係自上述密封樹脂部露出。
- 如請求項1或2之半導體裝置,其中上述密封樹脂部中之覆蓋上述金屬板之外周面之部分係較上述金屬板更向上述第1面側突出。
- 如請求項1或2之半導體裝置,其中上述外周面之4個面全部由上述密封樹脂部覆蓋,於俯視時,上述金屬板小於上述半導體晶片。
- 一種半導體裝置之製造方法,其包括如下步驟:於具有呈方形形狀之第1面之金屬板之上述第1面的相反面即第2面上,積層複數個半導體晶片而形成第1積層體;使積層於最上層之上述半導體晶片對向而將複數個上述第1積層體搭載於支持基板上,而形成第2積層體;於與上述第1面之間夾持膜而將上述第2積層體配置於模具之內部;將樹脂填充至上述模具之內部而形成密封上述複數個半導體晶片之密封樹脂部;及於上述第1積層體間進行切割而單片化;且進行上述切割時之切割線係與上述金屬板之上述第1面之外周邊平行,至少於外周邊中之1個對向之2邊通過上述金屬板之外側。
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