JPWO2014128796A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JPWO2014128796A1
JPWO2014128796A1 JP2015501087A JP2015501087A JPWO2014128796A1 JP WO2014128796 A1 JPWO2014128796 A1 JP WO2014128796A1 JP 2015501087 A JP2015501087 A JP 2015501087A JP 2015501087 A JP2015501087 A JP 2015501087A JP WO2014128796 A1 JPWO2014128796 A1 JP WO2014128796A1
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Prior art keywords
semiconductor device
semiconductor chip
extension
rewiring
die bond
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JP2015501087A
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JP6213554B2 (ja
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茂史 土肥
茂史 土肥
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Abstract

ダイボンドの這い上がりによるワイヤボンディング端子の汚染を防止しつつ、小型、薄型の半導体装置を提供する。半導体装置は、電極が形成された主面を有する第１の半導体チップと、第１の半導体チップの側端面から外方に拡張された拡張部と、第１の半導体チップの主面から拡張部の第１の面に亘って形成された再配線層と、拡張部の再配線層に設けられた接続端子と、第１の半導体チップおよび拡張部を基板に固定するダイボンドと、拡張部において、接続端子より外側に段差を有する。

Description

本開示は、半導体チップを積層して構成される半導体装置に関する。
デジタルテレビやレコーダ等のシステムでは、高機能化に伴い扱うデータ量が飛躍的に増加している。このため、システムに搭載される半導体メモリの容量も増加し、また高いデータ転送レートを有する半導体メモリが要求されている。
特許文献１は、側面から外方に拡張部を備えた第１の拡張型半導体チップ上に、第２の半導体チップを搭載した半導体装置を開示する。この構成では、再配線層により拡張部にワイヤボンディング端子を設けることができるため、サイズが大きい半導体チップを下側に配置する必要は無く、半導体チップの設計自由度の制約を回避することができる。
特許第５０６６３０２号公報
特許文献１において、下側の半導体チップはダイボンドによって基板と固定されている。このとき、ダイボンドは下側の半導体チップの側面を這い上がるため、チップの厚みやダイボンドの粘性によっては、拡張部に配置されたワイヤボンディング端子が汚染されるおそれがある。
特に、拡張部が樹脂材料で形成されている場合、シリコン基板の断面と比較して表面に微小な凹凸があるため、毛細管現象によってダイボンドの這い上がりが起こりやすい。また、一般的に同一や類似の材料同士のほうが濡れ性は良好であるため、主に樹脂で形成されたダイボンドは樹脂材料で形成された拡張部に対し、より顕著に這い上がる。
このようなワイヤボンディング端子のダイボンドによる汚染を回避する手段としては、ワイヤボンディング端子を半導体チップ側に近づけて配置することが考えられるが、そもそも下側の半導体チップが小さいために拡張部を形成しているため、配置領域に余裕があるわけではない。また、上側の半導体チップを固着するための接着剤（アンダーフィル等）のはみ出しなど、半導体チップ側からのワイヤボンディング端子の汚染も考慮する必要があるため、現実的でない。
ほかに、拡張部の領域を広くしてワイヤボンディング端子と拡張部の端部との距離を長くしたり、単に下側の半導体チップを厚くして側面の距離を長くしたりすることも、半導体装置の小型化、薄型化の観点から望ましくない。
本開示は、半導体装置の小型化、薄型化を阻害しない手段で、ダイボンドの這い上がりによるワイヤボンディング端子の汚染を防止するのに有効な半導体装置を提供する。
本開示における半導体装置は、複数の電極が形成された主面を有する第１の半導体チップと、第１の半導体チップの側端面から外方に拡張された拡張部と、第１の半導体チップの主面に搭載された第２の半導体チップと、第１の半導体チップの主面から拡張部の第１の面に亘って形成された再配線層と、拡張部の再配線層に設けられたワイヤボンディング端子と、第１の半導体チップおよび拡張部をパッケージ基板に固定するダイボンドと、拡張部の外縁領域において、ワイヤボンディング端子より外側に段差を備える。
本開示における半導体装置は、拡張部の外縁領域において段差を設けることによりダイボンドの這い上がりを防ぎ、小型化、薄型化を阻害せずにワイヤボンディング端子の汚染を防止するのに有効である。
図１Ａは、第１の実施形態に係る半導体装置の構成を示した断面図である。 図１Ｂは、図１Ａの破線Ａ枠内の拡大図である。 図２は、第１の実施形態に係る半導体装置の構成を示した平面図である。 図３は、第１の実施形態の変形例１に係る半導体装置の構成を示した断面図である。 図４は、第１の実施形態の変形例１に係る半導体装置の構成を示した断面図である。 図５は、第１の実施形態の変形例１に係る半導体装置の構成を示した断面図である。 図６は、第１の実施形態の変形例１に係る半導体装置の構成を示した断面図である。 図７は、第１の実施形態の変形例２に係る半導体装置の構成を示した断面図である。 図８は、第１の実施形態の変形例２に係る半導体装置の構成を示した断面図である。 図９は、第１の実施形態の変形例３に係る半導体装置の構成を示した断面図である。 図１０は、第１の実施形態の変形例３に係る半導体装置の構成を示した断面図である。 図１１Ａは、第１の実施形態に係る半導体装置の製造方法を示した断面図である。 図１１Ｂは、第１の実施形態に係る半導体装置の製造方法を示した平面図である。 図１２Ａは、第１の実施形態に係る半導体装置の製造方法を示した断面図である。 図１２Ｂは、第１の実施形態に係る半導体装置の製造方法を示した断面図である。 図１２Ｃは、第１の実施形態に係る半導体装置の製造方法を示した断面図である。 図１２Ｄは、第１の実施形態に係る半導体装置の製造方法を示した断面図である。 図１３Ａは、第１の実施形態に係る半導体装置の製造方法を示した断面図である。 図１３Ｂは、第１の実施形態に係る半導体装置の製造方法を示した断面図である。 図１３Ｃは、第１の実施形態に係る半導体装置の製造方法を示した断面図である。 図１４Ａは、第１の実施形態および変形例に係る半導体装置の製造方法を示した断面図である。 図１４Ｂは、第１の実施形態および変形例に係る半導体装置の製造方法を示した断面図である。 図１４Ｃは、第１の実施形態および変形例に係る半導体装置の製造方法を示した断面図である。 図１５は、第１の実施形態および変形例に係る半導体装置の製造方法を示した断面図である。 図１６は、第１の実施形態および変形例に係る半導体装置の製造方法を示した断面図である。 図１７は、他の態様に係る半導体装置の構成を示した断面図である。 図１８は、他の態様に係る半導体装置の構成を示した断面図である。
以下、本開示の半導体装置について適宜図面を参照しながら説明する。ただし、周知の事項の詳細説明や、実質的に同一の構成に対する重複説明などは省略する場合がある。これは、以下の説明が不必要に冗長になるのを避け、当業者の理解を容易にするためである。
なお、添付図面および以下の説明は、当業者が本開示を十分に理解するために提供するのであって、これらによって請求の範囲に記載の主題を限定することを意図するものではない。
（第１の実施形態）
図１Ａは、本実施形態にかかる半導体装置の構成を模式的に示す断面図であり、図１Ｂは、その一部の拡大図である。
図１Ａに示す半導体装置１００は、第１の半導体チップ１と、第１の半導体チップ１の側端面から外方に拡張した拡張部２と、第１の半導体チップ１上に搭載された第２の半導体チップ３と、第１の半導体チップ１および拡張部２が載置されたパッケージ基板４とを有する。拡張部２の材料は、例えば成型、加工が容易なエポキシ等の樹脂が適している。第１の半導体チップ１および拡張部２は、ダイボンド５によりパッケージ基板４に固着されている。ダイボンド５は、第１の半導体チップ１の裏面および拡張部２の裏面を覆い、かつ拡張部２の側面の少なくとも一部を覆う。
第１の半導体チップ１は、第２の半導体チップ３と対向する主面において複数の電極（図示せず）を有する。第１の半導体チップ１の主面から拡張部２の第１の面に亘って再配線層６が配置され、拡張部２の領域においてワイヤボンディング端子７を形成する。ワイヤボンディング端子７は、再配線層６を介して第１の半導体チップ１と電気的に接続されている。ワイヤボンディング端子７は、銅やニッケルにより形成されてもよいし、銅／はんだやニッケル／金などの積層構造であってもよい。はんだの組成は、例えば機械的特性に優れた錫−銀系、錫−銅系、錫−ビスマス系、錫−インジウム系の合金がある。また、ワイヤボンディング端子７は、ワイヤ８によりパッケージ基板４上の電極パッド９と接続されている。ワイヤ８は導電性の部材であり、例えば銅ワイヤや金ワイヤ、アルミワイヤである。
第２の半導体チップ３と第１の半導体チップ１は、バンプ１０を介して電気的に接合されており、接合部は接着材１１により固着されている。接着材１１は、例えば接着力強化剤であるアンダーフィル材であり、その材料としては、液状エポキシ樹脂、樹脂シート、異方性導電フィルム（ＡＣＦ：Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）等から採用できる。
パッケージ基板４の裏面には外部端子１２が配置され、この外部端子を介して半導体装置１００はマザー基板等と電気的に接続される。第１、第２の半導体チップおよびパッケージ基板の上面は、封止樹脂１３により封止されている。
図１Ｂは図１Ａの破線Ａ枠内を拡大した図である。
再配線層６は、再配線１４と絶縁層１５とを含む。再配線１４は、一般的にはフォトリソグラフィーを用いた電気めっきにより形成するため、配線厚みは約３〜５μｍ程度、幅は任意で作成可能である。第１の半導体チップ１内部の配線と比較して寸法が大きく、電気抵抗が小さいのが特徴である。再配線１４には、電気めっきなど簡易な工程で形成可能で、電気伝導性にも優れた銅が適している。絶縁層１５には、ポリイミド（ＰＩ：Ｐｏｌｙｉｍｉｄｅ）やポリベンゾオキサゾール（ＰＢＯ：ｐｏｌｙｂｅｎｚｏｘａｚｏｌｅ）等の樹脂を適用すると、加工が容易であり、高い保護効果を果たす。
第１の半導体チップ１の周縁部に設けられた電極１６は、再配線層６の再配線１４と接続され、第１の半導体チップ１が電気的に拡張部２の領域に引き出される。再配線１４は拡張部２の領域において、再配線層６に形成されたワイヤボンディング端子７と接続する。このように、第１の半導体チップ１は、再配線層６を介してワイヤボンディング端子７と電気的に接続されている。
断面図において、拡張部２の端部より内側に再配線層６の端部があり、拡張部２と再配線層６により段差を構成するように形成されている。より具体的には、ワイヤボンディング端子７よりも外側において、再配線層６の絶縁層１５が拡張部２の第１の面に対して段差を成している。この構成により、ダイボンド５が表面張力により拡張部２の側面から上面まで這い上がってきた場合も、段差によりダイボンド５の移動速度を低減でき、ワイヤボンディング端子７への這い上がりを阻止できる。
拡張部２の外縁領域における段差は、ワイヤボンディング端子７の配置に対応して形成するのが望ましい。例えば、図２に示すようにワイヤボンディング端子７が四方に配置された形態では、四方を囲むように拡張部２の外縁領域に設けるのが効果的である。
以上、本実施形態の半導体装置１００では、拡張部２の外縁領域に段差を備えることにより、拡張部２の再配線層６に配置されたワイヤボンディング端子７がダイボンド５の這い上がりにより汚染されることを防止できる。この構成によると、ダイボンド５の這い上がり対策のために拡張部２の厚みや平面サイズを大きくする必要も無いため、小型化、薄型化を阻害しない。また、ワイヤボンディング端子７を内側に寄せる必要もないため、接着材１１による汚染が生じない程度の距離を保って、ワイヤボンディング端子を配置することができる。
なお、本開示の効果は、第１の半導体チップ１が薄型化するとより顕著になる。一般的に、第１の半導体チップ１の厚みが約２００μｍ以下になるとダイボンド５の這い上がりによるワイヤボンディング端子７の汚染のリスクが高くなるためである。この際、２００μｍから第１の半導体チップ１の厚みを差し引いた長さ分、再配線層６を拡張部２の端部より内側に設けてもよい。つまり、第１の半導体チップ１の厚みが１５０μｍの場合に、再配線層６を拡張部２より５０μｍ以上内側に、第１の半導体チップ１の厚みが１００μｍの場合は、再配線層６を拡張部２より１００μｍ以上内側に設けることで、より確実に上記汚染リスクを抑制することが出来る。
なお、前述の半導体装置１００において、第１の半導体チップ１は半導体論理回路チップであり、第２の半導体チップ３は半導体メモリチップであってもよい。また、第２の半導体チップ３は、求められるメモリ容量によっては第１の半導体チップ１上に複数個積層してもよい。また、拡張部２と連結した第１の半導体チップ１についても、求められる機能に応じてパッケージ基板４上に複数個積層してもよい。
また、図１Ａでは、第１の半導体チップ１の端部は第２の半導体チップ３の端部よりも内側にあるが、第１の半導体チップ１の端部から外方に拡張部２を設けないとワイヤボンディング端子７の配置が困難な形態はこれに限らない。例えば、上下チップの端部が同じライン上にある構成でもよいし、第１の半導体チップ１の端部のほうが少し外側にあってもよい。
また、パッケージ基板４は主に樹脂基板を想定しているが、セラミック基板であってもよく、または基板の代わりにダイパッドとリードを用いてもよい。リードフレームを用いる構成では、全体として簡易で安価に製造することが可能となる。
また、拡張部２は、第１の半導体チップ１の側面だけでなく、電極１６を設けた主面とは反対側の裏面に拡張してもよい。拡張部２は第１の半導体チップ１の側面四方に設けてもよいが、対向する二方、または隣接する二方にのみ設けても構わない。たとえば、ワイヤボンディング端子７の配置領域が二方のみで間に合う場合などは、二方のみを拡張することで半導体装置１００としての小型化を図ることができる。
また、拡張部２のワイヤボンディング端子７は複数列形成してもよい。その場合、第１の半導体チップ１から拡張部２への電気的接続だけでなく、拡張部２内でワイヤボンディング端子間の電気的接続をとることもできる。
また、再配線層６は第１の半導体チップ１の全面に形成してもよいし、部分的に形成してもよい。具体的には、ワイヤボンディング端子７を、第１の半導体チップ１から拡張部２に引き出すだけであれば、第１の半導体チップ１の電極１６が配置された周縁部から拡張部２にかけてのみ配置してもよい。再配線層６を、第１の半導体チップ１および第２の半導体チップ３の中央部に電源を安定して供給するのに利用する場合は、さらにチップ中央部まで再配線層６を延伸して配置してもよい。
また、拡張部２の外縁領域における段差は、拡張部の外周に沿って連続的に設けてもよいし、断続的に設けてもよい。また、ワイヤボンディング端子７が二辺のみに配置された場合などは、段差もこの二辺のみに形成してもよい。
また、ダイボンド５は、拡張部２の側面から第１の面を覆い、再配線層６の端部まで至って止まるのがもっとも接続信頼性が高いが、拡張部２の第１の面の一部を覆うに留まり、再配線層６の端部に至らない場合もあり得る。
（第１の実施形態の変形例１）
図１Ａおよび図１Ｂに示した半導体装置１００では、拡張部２の外縁領域での段差は、再配線層６と拡張部２の第１の面とで形成されている。この構成では、ダイボンド５の這い上がりを抑制するための段差は、再配線層６の厚み分の一段のみである。
図３から図６は、第１の実施形態の変形例１にかかる半導体装置の一部を模式的に示す断面図である。一部とは、図１Ａの半導体装置１００における破線Ａ枠内に相当する箇所の構成を指す。
図３に示す例では、拡張部２ａの外縁領域における段差は、再配線層６によってではなく、拡張部２ａそのものの端部に形成されている。すなわち、拡張部２ａの第１の面とその上に形成された再配線層６とは段差を形成せず、端部が面一となっている。段差部は、拡張部２ａの裏面側が突出した形状である。段差は、図４に示す例のように、再配線層６の絶縁層１５および拡張部２ｂを斜め方向に切り出した形状で形成されてもよい。
図５に示す例でも、拡張部２ｃの外縁領域における段差は、再配線層６によってではなく、拡張部２ｃそのものの端部に形成されている。段差部は、拡張部２ｃの裏面側が窪んだ形状である。段差は、図６に示す例のように、拡張部２ｄを斜め方向に切り出した形状で形成されてもよい。
この構成において、ダイボンド５が表面張力により第１の半導体チップ１の裏面から主面の方向に這い上がる際、拡張部２ａ〜２ｄの段差で這い上がりの速度が低減されるため、拡張部２ａ〜２ｄの第１の面上の再配線層６まで至らせないことが可能になる。したがって、ダイボンド５が、ワイヤボンディング端子７まで浸入して汚染することを防止できる。
このように、拡張部２ａ〜２ｄの外縁領域に段差を設けることで、ダイボンド５の這い上がりを再配線層６に届く前に抑えることができ、ワイヤボンディング端子７の汚染を防止することが可能になる。
さらに、図５、６の構成は図３、４の構成に比してダイボンド５の這い上がりを抑制する効果が高いため、第１の半導体チップ１を薄くした場合も効果が期待でき、半導体装置の薄型化を可能にする。
（第１の実施形態の変形例２）
図１Ａおよび図１Ｂに示した半導体装置１００では、拡張部２の外縁領域での段差は、再配線層６と拡張部２の第１の面とで形成されている。この構成では、ダイボンド５の這い上がりを抑制するための段差は、再配線層６の厚み分の一段のみである。また、図３〜６に示した例では、再配線層６によってではなく、拡張部２そのものに段差を形成している。この構成でも、ダイボンド５の這い上がりを抑制するための段差は一段である。
図７および図８は、第１の実施形態の変形例１にかかる半導体装置の一部を模式的に示す断面図である。一部とは、図１Ａの半導体装置１００における破線Ａ枠内に相当する箇所の構成を指す。
図７に示す例では、拡張部２ａの外縁領域における段差は複数形成されている。一つは、再配線層６の絶縁層１５と拡張部２ａの第１の面で形成される第１の段差部で、もう一つは、拡張部２ａそのものの端部に形成された第２の段差部である。第２の段差部は第１の段差部より外側、かつ下方に形成されており、拡張部２ａの裏面側が突出した形状である。また、図８に示す例も、拡張部２ｃの外縁領域における段差は複数形成されている。図７との違いは、第２の段差部が、拡張部２ｃの第１の面側が突出した形状で成る点である。
この構成において、ダイボンド５が表面張力により第１の半導体チップ１の裏面から主面の方向に這い上がる際、まず拡張部２ａまたは２ｃの第２の段差で這い上がりの速度が低減され、さらに第１の段差があるためダイボンド５が再配線層６のワイヤボンディング端子まで浸入して汚染することを防止できる。
このように、拡張部２ａ、２ｃの外縁領域に複数の段差を設けることで、ダイボンド５の這い上がりをより抑えることができ、使用するダイボンド５の量や粘性にばらつきがあっても、ワイヤボンディング端子７の汚染をより確実に防止することが可能になる。また、第１の半導体チップ１を薄くした際にも効果が期待でき、半導体装置の薄型化に有効である。
（第１の実施形態の変形例３）
図１Ａおよび図１Ｂに示した半導体装置１００では、拡張部２の第１の面と段差を形成する再配線層６の端部において、再配線１４は絶縁層１５に被覆されていた。図３〜８に示した例でも同様である。
図９および図１０は、第１の実施形態の変形例３にかかる半導体装置の一部を模式的に示す断面図である。一部とは、図１Ａの半導体装置１００における破線Ａ枠内に相当する箇所の構成を指す。
図９に示す例では、拡張部２の第１の面と再配線層６ａによって段差が形成されている。また、再配線層６ａの端部において、再配線１４ａは絶縁層１５ａから露出している。すなわち、第１の半導体チップ１の電極１６と接続した再配線１４ａにより、再配線層６ａの端部まで第１の半導体チップ１が電気的に引き出されている。絶縁層１５ａと再配線１４ａの端部は面一である。
この構成において、導電性ペーストであるダイボンド５ａを用いると、再配線１４ａと、拡張部２の第１の面まで這い上がったダイボンド５ａが接触し、電気的に接続する。ここで、パッケージ基板４のダイボンド５ａを塗布する領域に電源供給用の電極（図示せず）を設ければ、ダイボンド５ａを介して第１の半導体チップ１に電源供給をすることができる。
この構成において、拡張部２の第１の面と再配線層６ａにより形成される段差によりダイボンド５ａの這い上がりが抑制され、ワイヤボンディング端子７の汚染が防止できるとともに、第１の半導体チップ１へのワイヤ８以外からの安定した電源供給が可能となる。その結果、ワイヤボンディング端子７の配置領域が減少し、拡張部２のサイズを小さくすることができるため、製造コストの低減や半導体装置の小型化を図ることが出来る。
図１０に示す例では、再配線層６ｂにおいて、再配線１４ｂ上の絶縁層１５ｂを一部形成せず、再配線１４ｂの側面と上面を露出させている。
この構成により、導電性ペーストであるダイボンド５ａとの接触面積を大きくすることができるため電源供給をさらに安定化することが可能である。
なお、本変形例で達成するのは電源供給に限らず、パッケージ基板４のＧＮＤ用の電極とダイボンド５ａを電気的に接続し、ＧＮＤをとる構成であってもよい。
（第１の実施形態およびその変形例にかかる製造方法）
図１１Ａ〜図１３Ｃは、第１の実施形態にかかる半導体装置１００の製造方法の一例を模式的に示す断面図と平面図である。
図１１Ａに示すように、キャリアウェハ（補強基板）１７上に接着層１８を形成し、その上に予め個片にした第１の半導体チップ１を載置する。複数の第１の半導体チップ１は、図１１Ｂのように接着層で覆われたキャリアウェハ１７上に所定の間隔をもって配列される。それぞれの第１の半導体チップ１は、主面を接着層１８と密着するように固定されている。
次に、図１２Ａに示すようにキャリアウェハ１７に固定した第１の半導体チップ１を封止するための拡張部材１９を流し込む。拡張部材１９は、主には樹脂である。図１２Ｂのように金型２０によって圧力と温度を加えて樹脂を硬化させる。このとき、第１の半導体チップ１の主面および主面に形成された複数の電極の表面は、接着層１８に密着している。そのため、拡張部材１９は第１の半導体チップの側面と裏面のみを覆い、主面および主面に形成された電極を汚染しない。樹脂の硬化が完了した後は、図１２Ｃのようにキャリアウェハ１７および接着層１８を除去する。さらに、図１２Ｄのように拡張部材１９の厚みを薄くするが、拡張部材１９は第１の半導体チップ１の裏面と面一になるまで削ってもよいし、裏面を覆う樹脂は残して薄化してもよい。拡張部材１９は、第１の半導体チップ１の側端面から外方に拡張するように構成されている。
次に、図１３Ａに示すように、第１の半導体チップ１の主面から拡張部材１９に亘って、再配線層６をフォトリソグラフィー法により形成する。図１３Ｂは図１３Ａの破線Ｂ枠内に相当する箇所を示す。再配線層６の再配線１４を第１の半導体チップ１の周縁部に形成された電極１６と接続し、拡張部材１９の領域まで引き出すように敷設する。さらに、拡張部材１９の領域において再配線１４上にワイヤボンディング端子７を形成し、第１の半導体チップ１からワイヤボンディング端子７までの電気的経路を構成する。再配線層６は、拡張部材１９の切断予定領域およびその内側、かつワイヤボンディング端子７より外側の部分において未形成にし、拡張部材１９を露出させる。このようにして、再配線層６の端面（本例では絶縁層１５）と拡張部材１９の露出面によって段差を形成する。
最後に、図１３Ｃに示すダイシングブレード２１によって拡張部材１９を切断し、拡張部２を備えた第１の半導体チップ１を個片にする。拡張部材１９の領域のうち、再配線層６が配置されていない部分を切断することで、拡張部材１９（拡張部２）の露出面と再配線層６の端部が成す段差を備えた個片チップを得る。個片にしたチップはパッケージ基板４に実装され、図１Ａに示した半導体装置１００を構成する。
以上、本実施形態の製造方法では、あらかじめ拡張部材１９上の再配線層６の一部を未形成とすることで、特別な加工方法を用いることなく、図１Ｂに示したような拡張部２の領域にダイボンド５の這い上がりを防止する段差を備えた半導体装置を得ることができる。
なお、図３〜１０に示した第１の実施形態の変形例１〜３についても、おおむね上述の製造方法により形成できるが、再配線層６形成の工程や拡張部材１９の領域を切断する工程において違いがある。差異について、幾つか例を挙げて説明する。
図１４Ａ〜図１４Ｃは、第１の実施形態の変形例１の製造方法で拡張部材１９の領域を切断する工程を示す。
図１４Ａは、ダイシングブレード２１ａを用いた加工で再配線層６および拡張部材１９の途中まで切断する工程を示す。切断面では再配線層６の端部と拡張部２の端部が面一になっている。このとき、再配線層６は拡張部材１９の上面全体に形成した状態でもよい。さらに、図１４Ｂのように、再配線層６を切断したダイシングブレード２１ａより幅の細いダイシングブレード２１ｂを用いて、拡張部材１９の裏面まで切断して個片にする。このように幅の異なるダイシングブレードを用いて段階的に切断する方法は、一般的にステップカットと呼ばれる。この切断工程により、図３に示した、拡張部２の第１の面側が突出した段差を形成可能である。
なお、図５のような拡張部の裏面側が突出した段差についても、ステップカットにより形成できる。裏面側を幅の広いダイシングブレード２１ａで切断し、第１の面側を幅の狭いダイシングブレード２１ｂで切断すればよい。
また、図１４Ａのダイシングブレード２１ａに代えて、図１４Ｃのようなテーパーを備えたダイシングブレード２１ｃを用いたステップカットを行ってもよい。この工程により、図４や図６に示した、斜め方向に切り出した段差を形成することができる。または、テーパーを備えたダイシングブレードにより再配線層６と拡張部材１９を一気に切断しても構わない。
拡張部２の領域の段差を形成する手段として、再配線層６の形成領域の調整や、ダイシング加工以外の方法を挙げる。
一つは、図１１Ａの第１の半導体チップ１を搭載する工程において、複数の第１の半導体チップの間にスペーサ２２をあらかじめ搭載しておく方法がある。図１５に示すように、ここに拡張部材１９を流し込み金型２０を用いて硬化させた後に、キャリアウェハ１７や接着層１８とともにスペーサ２２を除去することで段差を形成する。この方法によればスペーサ２２の形状を変化させることで段差形状を自由に制御することが出来る。また、ダイシングブレードを使用しないため、チッピング等により第１の半導体チップ１の回路形成面や再配線層６が損傷する恐れもない。
もう一つは、図１６に示すように、金型２０ａの拡張部材１９と接する面側において複数の突起形状を設け、この突起形状により拡張部材１９に段差を形成する方法である。これによれば、拡張部材１９の形成工程において金型２０ａの形状によって段差を得られるため、段差を形成するための工程の追加が不要であり効率がよい。また、突起形状を変化させることで、段差形状を自由に形成することが出来る。さらに、ダイシングブレードを使用しないため、チッピング等により第１の半導体チップ１の回路形成面や再配線層６が損傷する恐れもない。
（他の態様）
以上、本出願において開示する技術の例示として、第１の実施形態およびその変形例１〜３および製造方法等を説明した。しかしながら、本開示における技術は、これに限定されず、適宜、変更、置き換え、付加、省略などを行った実施の形態にも適用可能である。また、上記第１の実施の形態および変形例で説明した各構成要素を組み合わせて、新たな実施の形態とすることも可能である。
以下、他の態様の例を説明する。
第１の実施形態およびその変形例１〜３および製造方法において、第２の半導体チップ３は第１の半導体チップ１にバンプ１０を介してフリップチップ接続したが、両半導体チップの接続形態はこれ以外であってもよい。具体的には、図１７および１８に示すように、第２の半導体チップ３の回路形成面とは反対側の面を、第１の半導体チップの主面と固着してもよい。このとき、第１の半導体チップ１および第２の半導体チップ３の回路や電極等は各々の接続形態に適した設計がなされる。
図１７に示す半導体装置１１０では、第２の半導体チップ３ａの電極と、第１の半導体チップ１ａから再配線層６ｃで拡張部２に引き出したワイヤボンディング端子２３とを、ワイヤ２４によって接続することで、第１の半導体チップ１ａと第２の半導体チップ３ａの電気的接続を得る。ほかに、図１８に示す半導体装置１２０のように、第２の半導体チップ３ｂの回路面に形成された電極から裏面に向けて貫通電極２５を設け、第２の半導体チップ３ｂの裏面側において、第１の半導体チップ１ｂと電気的に接続する手段がある。このとき、第２の半導体チップ３ｂの裏面の電極と第１の半導体チップ１ｂの主面の電極は、例えばバンプ１０ａにより接続される。
また、封止樹脂１３は、第２の半導体チップ３を全て覆わなくてもよい。例えば、図１８のように、封止樹脂１３ａは第１の半導体チップ１ｂとの接続電極は封止するが、第２の半導体チップ３ｂの中央部分を露出してもよい。この構成は、特に第２の半導体チップ３ｂの回路面にセンサや発光機能を有する素子が形成される場合に採り得る。
以上のように、本開示における技術の例示として、添付図面および詳細な説明により実施の形態および変形例等を説明した。添付図面および詳細な説明に記載された構成要素の中には、課題解決のために必須な構成要素だけでなく、上記技術を例示するために、課題解決のためには必須でない構成要素も含まれ得る。そのため、それらの必須ではない構成要素が添付図面や詳細な説明に記載されていることをもって、直ちに、それらの必須ではない構成要素が必須であるとの認定をするべきではない。
また、上述の実施の形態および変形例は、本開示における技術を例示するためのものであるから、請求の範囲またはその均等の範囲において種々の変更、置き換え、付加、省略などを行うことができる。
本開示は、ワイヤボンディング端子が配置された拡張型半導体チップを備える半導体装置に適用可能である。
１，１ａ，１ｂ 第１の半導体チップ
２，２ａ，２ｂ，２ｃ，２ｄ 拡張部
３，３ａ，３ｂ 第２の半導体チップ
４ パッケージ基板
５，５ａ ダイボンド
６，６ａ，６ｂ，６ｃ 再配線層
７，２３ ワイヤボンディング端子
８，２４ ワイヤ
１４，１４ａ，１４ｂ 再配線
１５，１５ａ，１５ｂ 絶縁層
２０，２０ａ 金型
２２ スペーサ
１００，１１０，１２０ 半導体装置

Claims (17)

  1. 電極が形成された主面を有する第１の半導体チップと、
    前記第１の半導体チップの側端面から外方に拡張された拡張部と、
    前記第１の半導体チップの主面から前記拡張部の第１の面に亘って形成された再配線層と、
    前記拡張部の前記再配線層に設けられた接続端子と、
    前記第１の半導体チップおよび拡張部を基板に固定するダイボンドと、
    前記拡張部において、前記接続端子より外側に段差を備えることを特徴とする半導体装置。
  2. 前記段差は、前記拡張部の第１の面と、前記拡張部の端部より内側に形成された前記再配線層の端部により形成された第１の段差であることを特徴とする請求項１に記載の半導体装置。
  3. 前記再配線層は絶縁層と再配線とを有し、
    前記第１の段差を形成する前記再配線層の端部は、絶縁層のみで形成されていることを特徴とする請求項２に記載の半導体装置。
  4. 前記再配線層は絶縁層と再配線とを有し、
    前記第１の段差を形成する前記再配線層の端部では、絶縁層から再配線が露出していることを特徴とする請求項２に記載の半導体装置。
  5. 前記ダイボンドは導電性ペーストであり、
    前記ダイボンドは前記第１の段差を形成する前記再配線層の端部において、前記再配線と接触していることを特徴とする請求項４記載の半導体装置。
  6. 前記段差は、前記拡張部の端部の一部を突出させて階段状に形成される第２の段差を含むことを特徴とする請求項２〜５のいずれか１項に記載の半導体装置。
  7. 前記第２の段差は、前記拡張部の裏面側が突出して形成され、
    前記第１の段差と合わせて複数段の段差を形成することを特徴とする請求項６記載の半導体装置。
  8. 前記第２の段差は、前記拡張部の第１の面側が突出して形成され、
    前記第１の段差と合わせて複数段の段差を形成することを特徴とする請求項６記載の半導体装置。
  9. 前記ダイボンドは、前記再配線層の上面を避けて、前記拡張部の側面および第１の面の少なくとも一部を覆っていることを特徴とする請求項１〜８のいずれか１項に記載の半導体装置。
  10. 前記段差は、前記拡張部の端部の一部を突出させて階段状に形成される第２の段差であることを特徴とする請求項１記載の半導体装置。
  11. 前記第２の段差は、前記拡張部の第１の面側が突出して形成されることを特徴とする請求項１０記載の半導体装置。
  12. 前記ダイボンドは、前記再配線層の上面を避けて、前記拡張部の側面と前記第２の段差の少なくとも一部を覆っていることを特徴とする請求項１１記載の半導体装置。
  13. 前記第２の段差は、前記拡張部の裏面側が突出して形成されることを特徴とする請求項１０記載の半導体装置。
  14. 前記ダイボンドは、前記再配線層の上面および側面を避けて、少なくとも前記第２の段差を覆っていることを特徴とする請求項１３記載の半導体装置。
  15. 前記第２の段差の側面は、テーパーがついていることを特徴とする請求項１０〜１４のいずれか１項に記載の半導体装置。
  16. 前記第１の半導体チップの主面に、第２の半導体チップが搭載されていることを特徴とする請求項１〜１５のいずれか１項に記載の半導体装置。
  17. 前記接続端子は、ワイヤボンディング端子であり、
    前記接続端子は、前記基板の、前記第１の半導体チップの搭載面に設けられた電極パッドと、ワイヤによって接続されることを特徴とする請求項１〜１６のいずれか１項に記載の半導体装置。
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JP6560496B2 (ja) * 2015-01-26 2019-08-14 株式会社ジェイデバイス 半導体装置
CN113196465A (zh) 2018-11-21 2021-07-30 洛克利光子有限公司 具有凹槽的扇出型封装件
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US9709250B2 (en) * 2014-09-03 2017-07-18 Toshiba Lighting & Technology Corporation Lighting device for moving body
US10260909B2 (en) * 2015-07-30 2019-04-16 Dr. Johannes Heidenhain Gmbh Position measuring device

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