TWI719006B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TWI719006B
TWI719006B TW104144388A TW104144388A TWI719006B TW I719006 B TWI719006 B TW I719006B TW 104144388 A TW104144388 A TW 104144388A TW 104144388 A TW104144388 A TW 104144388A TW I719006 B TWI719006 B TW I719006B
Authority
TW
Taiwan
Prior art keywords
semiconductor
semiconductor chip
semiconductor device
back surface
chip
Prior art date
Application number
TW104144388A
Other languages
English (en)
Other versions
TW201628150A (zh
Inventor
茂田誠
Original Assignee
日商安靠科技日本公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商安靠科技日本公司 filed Critical 日商安靠科技日本公司
Publication of TW201628150A publication Critical patent/TW201628150A/zh
Application granted granted Critical
Publication of TWI719006B publication Critical patent/TWI719006B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/26145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/2939—Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H01L2224/49173—Radial fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83365—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Abstract

課題在於提供一種小型化、薄型化且品質提升之半導體裝置。半導體裝置包含封裝基板及堆疊於封裝基板上之多個半導體晶片。多個半導體晶片中之至少一者之背面之周緣部具有段差部。

Description

半導體裝置
本發明係關於一種半導體裝置。所揭示之發明之一實施型態有關於一種於封裝內堆疊有多個半導體晶片之半導體裝置。
半導體裝置之形成，為藉由晶圓切割而令行列狀排列於一枚矽晶圓上之多個半導體晶片切離，且藉由封裝而予以密封。
現有之半導體晶片於例如使用晶粒附著膜（die attach film）堆疊相同晶片之場合中，利用接合導線（bonding wire）等方式設置連結線至配置於晶片表面之電性連接用端子時，為了避開黏著於下側之晶片之連結線，會採取藉由間隔件（spacer）黏著下側元件及上側元件之方式，或者會採取黏著於上側之晶片之中心與黏著於下側之晶片之中心偏移設置之方式。
另外，於使用晶粒附著膠（die attach paste）進行封裝之場合中，溢出於晶片相互黏著部分之膠材會有攀爬晶片側面之特性，而攀爬之膠材到達晶片之表面時，膠材會有劣化半導體裝置品質之問題。
舉例而言，疊晶（chip on chip，CoC）連接構造之半導體裝置中，滴落至上側半導體晶片及下側半導體晶片之間之底部填充（underfill）樹脂若是流至設置於下側半導體晶片表面之電性連接用端子上，則有阻礙電性連接用端子及接合導線之電性接觸的可能性。對於如此之問題，例如於日本專利公開案2014-103198號公報，揭示有設置攔壩圖樣（dam pattern）圍繞電性連接用端子之技術。
此外，根據現有的方式，隨著進行堆疊之半導體晶片之增加，晶片於俯視時所佔據的面積變大，且於剖面時之高度增加，於妨礙封裝之小型化極薄型化之同時，還有間隔件之應用而導致成本增加之問題。
再者，於必須高度散熱之封裝之場合中，例如於覆晶（flip chip）構造之半導體晶片之上部黏著散熱板以企圖降低熱阻抗之方法中，雖然一般有組合高散熱規格之封裝樹脂等適用於半導體封裝之材料以降低熱阻抗之方法，但因需維持必要之材料特性而對於降低熱阻抗仍有其界限。
有鑑於上述之問題，本發明之一實施型態之一目的在於企圖達到半導體裝置之小型化及薄型化。再者，本發明之一實施型態之一目的在於企圖提升半導體裝置之品質。
根據本發明之一實施型態提供一種半導體裝置，其包含封裝基板及多個半導體晶片。多個半導體晶片堆疊於封裝基板上。多個半導體晶片中之至少一者之背面之周緣部具有段差部。
根據本發明之一實施型態提供一種半導體裝置，其包含封裝基板及第一半導體晶片。第一半導體晶片之背面具有多個溝槽，且第一半導體晶片之背面之端部具有段差部。第一半導體晶片之背面經由晶粒附著膠黏著於封裝基板。
根據本發明之一實施型態，藉由於半導體晶片之背面設置段差部，而能夠提供小型化及薄型化之半導體裝置。而且，藉由於半導體晶片之背面設置段差部，而能夠提升半導體裝置之品質。
以下，將一邊參照圖式一邊說明本發明之實施型態。然而，本發明能夠以多種相異的態樣予以實施，以下所例示之實施型態之記載內容並非用以限定解釋本發明。而且，為了使說明更加明確，圖式與實際的態樣相比，雖然圖式具有模式地表示關於各部位之幅寬、厚度、形狀等之場合，但此僅為一種範例，而並非用以限定本發明之解釋。再者，於本說明書及各圖式中，關於先前已出現且已描述之圖式，與其前述同樣之元件將附上相同的符號，且將適當省略詳細的說明。
於本說明書中，對於某部件或區域，於其他部件或區域之「上（或下）」之場合，除非另有限制，則不僅含有此部件或區域直接位於其他部件或區域之上（或直接位於其他部件或區域之下）之場合，還含有此部件或區域位於其他部件或區域之上方（或下方）之場合，亦即還含有此部件或區域於其他部件或區域之上方（或下方）之間亦可包含其他構成元件之場合。
＜第一實施型態＞
請參照圖1A及圖1B，將說明關於本實施型態之半導體裝置100。圖1A為關於本實施型態之半導體裝置100之俯視圖。圖1B為關於本實施型態之半導體裝置100之剖面圖。半導體裝置100具有堆疊於封裝基板105上之多個半導體晶片101。於各個半導體晶片101設置有多個電性連接用端子104。此外，於封裝基板105設置有用以電性連接於電性連接用端子104之端子。此端子雖可為任意形態，亦可例如為圖1A所示之多個引線框架（lead frame）106。使用接合導線108連接電性連接用端子104及引線框架106。如圖1B之剖面圖所示，堆疊之多個半導體晶片101之尺寸略為相同。此外，圖1B雖例示堆疊二層半導體晶片101之態樣，但並非限定於二層，亦能夠根據本實施型態而將半導體裝置100擴張成三層以上。
多個半導體晶片101可從矽晶圓切離。此時，矽晶圓可為大塊矽晶圓（bulk silicon wafer）亦可為絕緣體上矽（Silicon on Insulator，SOI）晶圓。或者，亦可從其他的半導體晶圓切離。各半導體晶片101雖未繪示但於表面形成有半導體積體電路。更進一步，於表面之端部附近形成有電性連接用端子104。多個半導體晶片101使用黏著劑110黏著而彼此堆疊。可使用接合膜（bonding film）做為黏著劑110，例如可使用晶粒附著膜。而且，於本說明書中，半導體晶片101形成有半導體積體電路處之面稱為「表面」，其相反處之面稱為「背面」。
於本實施型態中，多個半導體晶片101可於背面施予加工處理。具體而言，如圖1B所示，上層半導體晶片103可調整形狀為其背面之端部之厚度薄於其他部位。換句話說，半導體晶片101之背面之周緣部具有段差部，於此段差部之外側之厚度較薄，於內側較厚。設置於上層半導體晶片103之段差部之所在位置，位於比設置於下層半導體晶片102所設置之電性連接用端子104之區域更為內側之位置。由於具有此段差部，故上層半導體晶片103之端部未接觸於下層半導體晶片102，於俯視時此段差部之內側之區域為黏著於下層半導體晶片102之黏著面。換言之，黏著於下層半導體晶片102之黏著面小於半導體晶片102之表面積。於圖1A中，下層及上層半導體晶片102及103之黏著面之端部以虛線表示。
下層半導體晶片102黏著於上層半導體晶片103之黏著面之外側形成有空隙，且露出電性連接用端子104。而且，藉由形成此空隙，而能夠以接合導線108設置連結於電性連接用端子104之連結線。
設置於上層半導體晶片103之段差部，能夠以自晶片之背面處施予加工處理之方式設置。舉例而言，藉由對於半導體晶片103之背面選擇性地進行切削加工、蝕刻加工，而能夠形成段差部。形成段差部時之加工深度，以不會對形成於表面處之元件造成影響之程度之深度為佳。藉由如此之加工而形成之段差部之形狀，能夠例如為階梯狀、錐狀或具有曲率之錐狀之形態。若為階梯狀之段差，則能夠擴大用以連接接合導線108之空隙。另外，若段差部為錐狀，除了能夠對於下層半導體晶片102連接接合導線108，還能夠提升上層半導體晶片103之周緣部之機械強度，亦即提升半導體晶片103之設置有電性連接用端子104之區域之機械強度。
關於自半導體晶片101之背面處形成段差時之加工深度，為了必須要有能夠耐受以接合導線108設置連結線時之應力或封裝時之應力之機械強度，自半導體晶片101之背面至段差之最深部之深度及未黏著於因段差而薄板化之半導體晶片101之區域皆為能夠愈小愈好。另一方面，自段差之最深部至晶片表面之厚度為能夠愈大愈好。然而，要進行用以維持半導體裝置100品質之信賴性試驗後再決定這些尺寸之組合。
根據關於本實施型態之半導體裝置100，藉由設置於半導體晶片101之周緣部之段差部，而能夠避開對於黏著於下側之半導體晶片102設置連結線之接合導線108時之干涉，因此無需偏移設置配置於上側之半導體晶片103之中心與配置於下側之半導體晶片102之中心。換言之，相同尺寸或同等尺寸之多個半導體晶片101之中心能夠一致地堆疊，也不會增加所堆疊之多個半導體晶片101所佔據的面積，而不會對小型化造成妨礙。亦即於半導體晶片101形成有半導體積體電路之區域面積為相同的情況下堆疊多個半導體晶片101，也能夠於半導體晶片101之間以接合導線108設置連結線。於此場合中，因能夠以多個半導體晶片101之中心略為相同之方式堆疊，而沒有增加封裝基板105之面積之必要。因此，根據本實施型態能夠達到半導體裝置100之小型化。
更進一步，將如後所述，例如使用晶粒附著膠等膠狀之黏著劑做為黏著劑110之場合中，關於黏著劑110溢出於黏著部外且攀爬上層之基板之表面而造成半導體裝置品質低下之問題，能夠藉由設置段差部而避開此問題。
所謂半導體晶片101之中心，可為半導體晶片101例如為長方形時其對角線交點。根據本實施型態，多個半導體晶片101之中心位置於俯視時略為一致，而能夠配置於半徑約為0.005 mm之圓之區域內。
此外，雖然圖1A及圖1B例示僅於上側半導體晶片103設置段差部之態樣，亦可將段差部設置於下側。此場合中，使用膠狀黏著劑黏著封裝基板105及半導體晶片102之情況下，能夠避開此黏著劑攀爬的問題。
根據關於本實施型態之半導體裝置100，於半導體晶片101之端部設置段差時，由於能夠藉由此段差所造成之空隙而避開所設置之連結線，因此無需間隔件或間隔膜也能夠使用黏著劑110進行黏著。藉此，根據本實施型態，能夠不妨礙半導體裝置100之薄型化，也能夠提供低成本之半導體裝置100。
接合導線108之材料可為導電性優良之材料，雖例如可為金導線或銅導線，亦可為具備必要之導電性及連接性之材料。
＜變形例1-1＞
請參照圖2A及圖2B，將說明關於本變形例之半導體裝置200之結構。圖2A為關於本變形例之半導體裝置200之俯視圖。圖2B為關於本變形例之半導體裝置200之剖面圖。關於本變形例之半導體裝置200與前述之半導體裝置100相比，為上層半導體晶片103之段差部之配置相異。前述之半導體裝置100中，雖於上層半導體晶片103之完整外周之端部設置段差部，但並非限定於此，亦可如本變形例之周緣部中僅於周緣部之一邊設置段差部。或者，亦可設置於任意之二邊或三邊。
＜第二實施型態＞
請參照圖3A及圖3B，將說明關於本實施型態之半導體裝置300之結構。圖3A為關於本實施型態之半導體裝置300之俯視圖。圖3B為關於本實施型態之半導體裝置300之剖面圖。
關於本實施型態之半導體裝置300於本實施型態中，除了於半導體晶片101之背面設置有段差以外，更於半導體晶片101之背面設置有多個溝槽。而且，使用黏著劑112將具有此溝槽之半導體晶片101黏著於封裝基板105。於本實施型態中，可使用膠狀之黏著劑做為黏著劑112進行黏著，例如可使用晶粒附著膠等進行黏著。
因於半導體晶片101之背面設置溝槽，而增加背面之表面積。由於此背面之表面積增加，而能夠藉由黏著劑112之覆蓋面積之增加而提升黏著強度，藉此提升半導體裝置300之信賴性。
形成於半導體晶片101之背面之溝槽，可例如於晶圓切割時藉由切割刀片加工而形成，亦可使用光刻（photolithography）工程加工而形成。由於黏著劑112可無間隙地流入各個溝槽而能夠完整黏著溝槽表面，故能夠提升黏著強度。
另外，自多個半導體晶片101之接合部溢出之黏著劑112具有攀爬半導體晶片101之側面之特性。使用黏著劑112之半導體裝置300之場合中，攀爬之黏著劑112到達上層半導體晶片101之表面時，會有降低半導體裝置300品質之場合。
但關於本實施型態之半導體裝置300則因於半導體晶片101之端部具有段差部，而能夠抑制自半導體晶片101與下層之黏著部溢出之黏著劑112攀爬至半導體晶片101之表面。換言之，能夠避開黏著劑112到達半導體晶片101之表面而降低半導體裝置300之品質之問題，故能夠提供信賴性提升之半導體裝置300。
於本實施型態之段差之形狀，可為愈能夠抑制用以黏著半導體晶片101之黏著劑112攀爬上層半導體晶片101之形狀愈好。因此，自黏著部之端部至上層處之半導體晶片101之表面之距離圍愈長愈好。換言之，若例如為階梯狀之形狀，因能夠比錐狀或具有曲率之錐狀更能夠確保此距離，故能夠有效抑制黏著劑112之攀爬。
做為膠狀之黏著劑112，能夠例如使用晶粒附著膠，亦能夠例如使用銀系或樹脂系之膠，並無特別限制。
＜變形例2-1＞
請參照圖4，將說明關於本變形例之半導體裝置400之結構。圖4為關於本變形例之半導體裝置400之剖面圖。關於本變形例之半導體裝置400為組合根據前述第一實施型態之半導體裝置100及根據前述第二實施型態之半導體裝置300之態樣。具體而言，使用膠狀之黏著劑112黏著封裝基板105及下層半導體晶片102，使用膜狀之黏著劑110黏著下層半導體晶片102及上層半導體晶片103。
根據如此之構造，關於上層半導體晶片103於背面端部可僅設置段差，而無需藉由切割工程或光刻工程等工程形成溝槽。於本變形例中，雖例示半導體晶片101為二層，於三層以上之場合中，從第二層以上之半導體晶片中能夠省略形成溝槽之工程。
＜第三實施形態＞
請參照圖5，將說明關於本實施型態之半導體裝置500之結構。圖5為關於本實施型態之半導體裝置500之剖面圖。半導體裝置500具有半導體晶片102、半導體晶片103、散熱板114、電性連接用端子104、多個引線框架106及接合導線108。半導體晶片102配置於封裝基板105上。半導體晶片103配置於半導體晶片102之上層。散熱板114配置於半導體晶片103上。多個引線框架106設置於封裝基板105上。接合導線108連接電性連接用端子104及引線框架106。於圖5之剖面圖中，雖例示堆疊二層半導體晶片101之態樣，但並非限定於二層，亦能夠根據本實施型態而將半導體裝置500擴張成三層以上。
於本實施型態中，例示於下層半導體晶片102之背面形成有多個溝槽，且使用膠狀之黏著劑112黏著於封裝基板105之態樣。然而，並非限定於此，亦可不形成溝槽而使用膜狀之黏著劑110進行黏著。
上層半導體晶片103具有覆晶構造。換言之，上層半導體晶片103以形成有半導體積體電路之表面朝下之方式配置。於上層半導體晶片103之背面形成有多個溝槽。而且，使用黏著劑116黏著上層半導體晶片103之背面及散熱板114。黏著劑116能夠例如使用底部填充劑。
藉由於上層半導體晶片103之背面形成有溝槽，而增加背面之表面積。由於如此之半導體晶片103之背面之表面積增加，而能夠降低熱阻抗以提升散熱效果。
形成於半導體晶片101之背面之溝槽，可例如於晶圓切割時藉由切割刀片加工而形成，亦可使用光刻工程加工而形成。
以上，根據本發明之實施型態說明關於半導體裝置100至500。然而，此些僅不過為例示而非用以將本發明之技術範圍限定於此。實際上，只要不脫離申請專利範圍所請求之本發明之要旨，此領域之業者能夠進行各種變更。因此，此些變更理所當然地也應理解成屬於本發明之技術範圍。
100、200、300、400、500‧‧‧半導體裝置 101、102、103‧‧‧半導體晶片 104‧‧‧電性連接用端子 105‧‧‧封裝基板 106‧‧‧引線框架 108‧‧‧接合導線 110、112、116‧‧‧黏著劑 114‧‧‧散熱板
圖1A為繪示關於本發明之一實施型態之半導體裝置之概略結構之俯視圖。 圖1B為繪示關於本發明之一實施型態之半導體裝置之概略結構之剖面圖。 圖2A為繪示關於本發明之一實施型態之半導體裝置之概略結構之俯視圖。 圖2B為繪示關於本發明之一實施型態之半導體裝置之概略結構之剖面圖。 圖3A為繪示關於本發明之一實施型態之半導體裝置之概略結構之俯視圖。 圖3B為繪示關於本發明之一實施型態之半導體裝置之概略結構之剖面圖。 圖4為繪示關於本發明之一實施型態之半導體裝置之概略結構之剖面圖。 圖5為繪示關於本發明之一實施型態之半導體裝置之概略結構之剖面圖。
100‧‧‧半導體裝置
101、102、103‧‧‧半導體晶片
104‧‧‧電性連接用端子
105‧‧‧封裝基板
106‧‧‧引線框架
108‧‧‧接合導線
110‧‧‧黏著劑

Claims (12)

  1. 一種半導體裝置，包括：一封裝基板；以及多個半導體晶片，堆疊於該封裝基板上，所述多個半導體晶片包含設置於所述多個半導體晶片中之上層上的第一半導體晶片以及設置於所述多個半導體晶片中之下層上的第二半導體晶片，其中：該第一半導體晶片包含在一背面之一周緣部中的一段差部；該段差部露出該第二半導體晶片之一電性連接用端子；在朝向該封裝基板的俯視下，該第二半導體晶片之該電性連接用端子被設置在該第一半導體晶片的相鄰電性連接用端子之間；並且在前述俯視下，該第二半導體晶片之該電性連接用端子以及在該第一半導體晶片的相鄰電性連接用端子實質上是對齊的。
  2. 如請求項1所述之半導體裝置，其中該半導體晶片之除了該段差部的一背面經由一黏著劑黏著於該第二半導體晶片。
  3. 如請求項1所述之半導體裝置，其中該段差部設置於該第一半導體晶片之該背面之該周緣部之一部分，並且其中該段差部包括在橫截面圖中形成直角的階梯狀之形狀。
  4. 如請求項2或3所述之半導體裝置，其中該些半導體晶片之各個中心配置於半徑為0.005mm以內之區域內。
  5. 如請求項4所述之半導體裝置，其中該些半導體晶片中之至少一者之一背面具有多個溝槽，且經由一黏著劑黏著於下層。
  6. 如請求項1所述之半導體裝置，其中：該封裝基板包括一引線框架；以及該第一半導體晶片以及該第二半導體晶片的所述電性連接用端子藉由導線 而被電性連接到該引線框架；該引線框架包括引線；在前述俯視下，每個所述引線包括有角度部分；每個所述導線耦接到所述引線中的一個的該有角度部分。
  7. 如請求項1所述之半導體裝置，其中：該段差部被設置在該第一半導體晶片之該周緣部的每一側中。
  8. 如請求項1所述之半導體裝置，其中：該第二半導體晶片包含在該第二半導體晶片的一背面之一周緣部的一段差部；以及該第二半導體晶片的該背面被黏著到該封裝基板。
  9. 一種半導體裝置，包括：一封裝基板；以及多個半導體晶片，堆疊於該封裝基板上，所述多個半導體晶片包含設置於所述多個半導體晶片中之上層上的第一半導體晶片以及設置於所述多個半導體晶片中之下層上的第二半導體晶片，其中：該第一半導體晶片包含在該第一半導體晶片的一背面之一第一周緣部中的一第一段差部；該第二半導體晶片包含在該第二半導體晶片的一背面之一第二周緣部中的一第二段差部；該第二半導體晶片的該背面被黏著到該封裝基板；該第一段差部露出該第二半導體晶片之一電性連接用端子；在朝向該封裝基板的俯視下，該第二半導體晶片之該電性連接用端子被設置在該第一半導體晶片的相鄰電性連接用端子之間；該封裝基板包括一引線框架；以及 該第一半導體晶片以及該第二半導體晶片的所述電性連接用端子藉由導線而被電性連接到該引線框架。
  10. 如請求項9所述之半導體裝置，其中該第二半導體晶片之該背面藉由一第一黏著劑而被黏著。
  11. 如請求項9所述之半導體裝置，其中：該引線框架包括引線；在前述俯視下，每個所述引線包括有角度部分；每個所述導線耦接到所述引線中的一個的該有角度部分。
  12. 如請求項9所述之半導體裝置，其中：該第一段差部被設置在該第一半導體晶片的該第一周緣部的每一側中。
TW104144388A 2015-01-26 2015-12-30 半導體裝置 TWI719006B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-012379 2015-01-26
JP2015012379A JP6560496B2 (ja) 2015-01-26 2015-01-26 半導体装置

Publications (2)

Publication Number Publication Date
TW201628150A TW201628150A (zh) 2016-08-01
TWI719006B true TWI719006B (zh) 2021-02-21

Family

ID=56434221

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104144388A TWI719006B (zh) 2015-01-26 2015-12-30 半導體裝置

Country Status (5)

Country Link
US (1) US9905536B2 (zh)
JP (1) JP6560496B2 (zh)
KR (1) KR20160091810A (zh)
CN (1) CN105826308A (zh)
TW (1) TWI719006B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2704398T3 (es) 2015-07-14 2019-03-18 Boeing Co Método y sistema de generación autónoma de trayectorias laterales más cortas para sistemas aéreos no tripulados
KR102518803B1 (ko) 2018-10-24 2023-04-07 삼성전자주식회사 반도체 패키지

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001257307A (ja) * 2000-03-09 2001-09-21 Sharp Corp 半導体装置
US20020096754A1 (en) * 2001-01-24 2002-07-25 Chen Wen Chuan Stacked structure of integrated circuits
JP2003163313A (ja) * 2001-09-13 2003-06-06 Texas Instr Japan Ltd 半導体装置及びその製造方法
US20040080041A1 (en) * 2002-10-21 2004-04-29 Nec Electronics Corporation Semiconductor device with improved heatsink structure
JP2005340483A (ja) * 2004-05-27 2005-12-08 Matsushita Electric Ind Co Ltd 半導体チップ、半導体装置、およびその製造方法
US20060175697A1 (en) * 2005-02-02 2006-08-10 Tetsuya Kurosawa Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
US20070190691A1 (en) * 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level chip packaging
US20140319663A1 (en) * 2013-04-18 2014-10-30 Dai Nippon Printing Co., Ltd. Lead frame, method for manufacturing lead frame, semiconductor device, and method for manufacturing semiconductor device

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993023982A1 (en) * 1992-05-11 1993-11-25 Nchip, Inc. Stacked devices for multichip modules
US6225695B1 (en) * 1997-06-05 2001-05-01 Lsi Logic Corporation Grooved semiconductor die for flip-chip heat sink attachment
US6351028B1 (en) * 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
JP2001308220A (ja) * 2000-04-24 2001-11-02 Nec Corp 半導体パッケージ及びその製造方法
US6759745B2 (en) * 2001-09-13 2004-07-06 Texas Instruments Incorporated Semiconductor device and manufacturing method thereof
CN1497715A (zh) * 2002-10-21 2004-05-19 恩益禧电子股份有限公司 带有改进的散热器结构的半导体装置
JP4123027B2 (ja) * 2003-03-31 2008-07-23 セイコーエプソン株式会社 半導体装置の製造方法
US7575955B2 (en) * 2004-01-06 2009-08-18 Ismat Corporation Method for making electronic packages
JP2007142105A (ja) * 2005-11-17 2007-06-07 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
WO2008014633A1 (en) * 2006-06-29 2008-02-07 Intel Corporation Apparatus, system, and method for wireless connection in integrated circuit packages
TW200845339A (en) * 2007-05-07 2008-11-16 Sanyo Electric Co Semiconductor device and manufacturing method thereof
SG148054A1 (en) * 2007-05-17 2008-12-31 Micron Technology Inc Semiconductor packages and method for fabricating semiconductor packages with discrete components
SG149724A1 (en) * 2007-07-24 2009-02-27 Micron Technology Inc Semicoductor dies with recesses, associated leadframes, and associated systems and methods
JP2010062365A (ja) * 2008-09-04 2010-03-18 Hitachi Ltd 半導体装置およびその製造方法
JP2010182958A (ja) * 2009-02-06 2010-08-19 Seiko Instruments Inc 半導体装置および半導体装置の製造方法
US8970046B2 (en) * 2011-07-18 2015-03-03 Samsung Electronics Co., Ltd. Semiconductor packages and methods of forming the same
JP6125209B2 (ja) 2012-11-19 2017-05-10 株式会社ジェイデバイス 半導体装置及びその製造方法
JP6213554B2 (ja) * 2013-02-25 2017-10-18 パナソニック株式会社 半導体装置
TWI654722B (zh) * 2013-03-04 2019-03-21 愛爾蘭商經度授權有限公司 半導體裝置
JP2014203861A (ja) * 2013-04-02 2014-10-27 三菱電機株式会社 半導体装置および半導体モジュール

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001257307A (ja) * 2000-03-09 2001-09-21 Sharp Corp 半導体装置
US20020096754A1 (en) * 2001-01-24 2002-07-25 Chen Wen Chuan Stacked structure of integrated circuits
JP2003163313A (ja) * 2001-09-13 2003-06-06 Texas Instr Japan Ltd 半導体装置及びその製造方法
US20040080041A1 (en) * 2002-10-21 2004-04-29 Nec Electronics Corporation Semiconductor device with improved heatsink structure
JP2005340483A (ja) * 2004-05-27 2005-12-08 Matsushita Electric Ind Co Ltd 半導体チップ、半導体装置、およびその製造方法
US20060175697A1 (en) * 2005-02-02 2006-08-10 Tetsuya Kurosawa Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
US20070190691A1 (en) * 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level chip packaging
US20140319663A1 (en) * 2013-04-18 2014-10-30 Dai Nippon Printing Co., Ltd. Lead frame, method for manufacturing lead frame, semiconductor device, and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
US20160218086A1 (en) 2016-07-28
JP2016139654A (ja) 2016-08-04
KR20160091810A (ko) 2016-08-03
CN105826308A (zh) 2016-08-03
TW201628150A (zh) 2016-08-01
US9905536B2 (en) 2018-02-27
JP6560496B2 (ja) 2019-08-14

Similar Documents

Publication Publication Date Title
TWI567897B (zh) 薄型扇出式多晶片堆疊封裝構造與製造方法
JP2012069585A (ja) 半導体装置およびその製造方法
TWI430425B (zh) 採用凸塊技術之積體電路封裝件系統
US9842794B2 (en) Semiconductor package with integrated heatsink
US20100140801A1 (en) Device
US20160148876A1 (en) Flat no-leads package with improved contact pins
TWI630699B (zh) Semiconductor device
US9337172B2 (en) Semiconductor device
TWI445468B (zh) 具有小厚度之電腦模組及其製造方法
JP2010232471A (ja) 半導体装置の製造方法および半導体装置
US8975739B2 (en) Package structure and method for manufacturing thereof
US8810047B2 (en) Semiconductor device and method of manufacturing the same
TWI719006B (zh) 半導體裝置
US11721654B2 (en) Ultra-thin multichip power devices
JP5547703B2 (ja) 半導体装置の製造方法
TWI556383B (zh) 封裝結構及其製法
US20220044989A1 (en) Semiconductor package having die pad with cooling fins
TW202008529A (zh) 半導體裝置及其製造方法
US8878070B2 (en) Wiring board and method of manufacturing a semiconductor device
TWI466199B (zh) 具有晶圓尺寸貼片的封裝方法
JP2008192660A (ja) 半導体装置およびその製造方法
US20090289347A1 (en) Circuit board, lead frame, semiconductor device, and method for fabricating the same
JP2019102599A (ja) 半導体装置の製造方法
JP4862991B2 (ja) 半導体装置の製造方法
JP5223231B2 (ja) 半導体装置