JP2015176958A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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JP2015176958A
JP2015176958A JP2014051238A JP2014051238A JP2015176958A JP 2015176958 A JP2015176958 A JP 2015176958A JP 2014051238 A JP2014051238 A JP 2014051238A JP 2014051238 A JP2014051238 A JP 2014051238A JP 2015176958 A JP2015176958 A JP 2015176958A
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Prior art keywords
chip
wiring layer
circuit surface
electrode
wafer
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JP2014051238A
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Inventor
一茂 河崎
Kazushige Kawasaki
一茂 河崎
栗田　洋一郎
Yoichiro Kurita
洋一郎 栗田
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Toshiba Corp
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Toshiba Corp
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Priority to JP2014051238A priority Critical patent/JP2015176958A/ja
Priority to TW103123336A priority patent/TWI550824B/zh
Priority to US14/475,298 priority patent/US9721935B2/en
Priority to CN201410444601.1A priority patent/CN104916619B/zh
Publication of JP2015176958A publication Critical patent/JP2015176958A/ja
Priority to US15/630,496 priority patent/US10128223B2/en
Pending legal-status Critical Current

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Abstract

【課題】貫通電極部分の寄生容量低減が可能な半導体装置及びその製造方法を提供する。【解決手段】第２チップは、第１チップの第１配線層側に積層されている。第２チップは、第１配線層に対向した第２回路面と、第２回路面の反対側の第２裏面とを有する第２半導体層と、第２回路面に設けられ第１チップの第１配線層と接続された第２配線層と、第２半導体層を貫通して設けられ、第２配線層に接続された第２貫通電極と、を有する。第３チップは、第２チップの第２裏面側に積層されている。第３チップは、第３回路面と、第２チップに対向した第３裏面とを有する第３半導体層と、第３回路面に設けられた第３配線層と、第３半導体層を貫通して設けられ、第３配線層に接続されるとともに第２チップの第２貫通電極にバンプ接続された第３貫通電極とを有する。【選択図】図１

Description

本発明の実施形態は、半導体装置及びその製造方法に関する。
ＴＳＶ（Through-Silicon Via）を使った構造において、チップの積層数が多くなるなどＴＳＶの数が増えると、ＴＳＶとシリコン基板との間の寄生容量の増大をまねく。
米国特許第７１１９４２８号明細書
本発明の実施形態は、貫通電極部分の寄生容量低減が可能な半導体装置及びその製造方法を提供する。
実施形態によれば、半導体装置は、第１チップと、第２チップと、第３チップと、を備えている。前記第１チップは、第１回路面と、前記第１回路面の反対側の第１裏面とを有する第１半導体層と、前記第１回路面に設けられた第１配線層と、前記第１半導体層を貫通して設けられ、前記第１配線層に接続された第１貫通電極と、を有する。前記第２チップは、前記第１チップの前記第１配線層側に積層されている。前記第２チップは、前記第１配線層に対向した第２回路面と、前記第２回路面の反対側の第２裏面とを有する第２半導体層と、前記第２回路面に設けられ、前記第１チップの前記第１配線層と接続された第２配線層と、前記第２半導体層を貫通して設けられ、前記第２配線層に接続された第２貫通電極と、を有する。前記第３チップは、前記第２チップの前記第２裏面側に積層されている。前記第３チップは、第３回路面と、前記第３回路面の反対側に位置し、前記第２チップに対向した第３裏面とを有する第３半導体層と、前記第３回路面に設けられた第３配線層と、前記第３半導体層を貫通して設けられ、前記第３配線層に接続されるとともに、バンプを介して前記第２チップの前記第２貫通電極と接続された第３貫通電極と、を有する。
実施形態の半導体装置の模式断面図。 実施形態の半導体装置の模式断面図。 実施形態の半導体装置の模式断面図。 実施形態の半導体装置の製造方法を示す模式断面図。 実施形態の半導体装置の製造方法を示す模式断面図。 実施形態の半導体装置の製造方法を示す模式断面図。 実施形態の半導体装置の製造方法を示す模式断面図。 実施形態の半導体装置の製造方法を示す模式断面図。 実施形態の半導体装置の製造方法を示す模式断面図。 実施形態の半導体装置における複数のチップの接続関係を示す模式図。 実施形態の半導体装置の模式断面図。
以下、図面を参照し、実施形態について説明する。なお、各図面中、同じ要素には同じ符号を付している。
図１（ａ）は、実施形態の半導体装置の模式断面図である。
実施形態の半導体装置は、複数の半導体チップ（以下、単にチップともいう）１１の積層体が、実装基板（インターポーザ）５１上に実装され、封止樹脂８０に覆われている。
図１（ａ）には、例えば８個のチップ１１が積層された構造を例示するが、チップ１１の積層数は任意である。複数のチップ１１は、厚さ、平面サイズ、厚み方向の層構造および材料などが同じ、例えばメモリチップである。
実施形態によれば、２つのチップ１１が回路面１２ａどうしをフェイストゥフェイスで対向させてボンディングされた構成の２チップ積層体１０が複数積層されている。
２チップ積層体１０における１対のチップ１１は、後述するようにウェーハトゥウェーハボンディングにより接合される。複数の２チップ積層体１０どうしは、バンプ接続している。
図１（ｂ）は、図１におけるＡ部の拡大模式断面図であり、２チップ積層体１０の部分断面を表す。
それぞれのチップ１１は、半導体層１２と、配線層１３と、貫通電極１８と、接合金属（または中間電極）２１とを有する。
半導体層１２には、例えばシリコン基板を用いる。あるいは、半導体層１２には、ＳＯＩ（Silicon On Insulator）構造におけるシリコン層を用いる。また、半導体層１２には、シリコン以外の例えばＳｉＣ、ＧａＮなどの層（基板）を用いてもよい。以下の説明では、半導体層１２をシリコン基板として説明する。
シリコン基板１２は、回路面１２ａとその反対側の裏面１２ｂとを有する。ここでの裏面１２ｂとは、回路面１２ａに対する裏面を表す。
回路面１２ａには、図示しないトランジスタなどを含む半導体集積回路が形成されている。例えば、メモリチップの場合、回路面１２ａ上に電荷蓄積層、制御電極などが形成されている。
回路面１２ａ上には、半導体集積回路、制御電極と接続された配線層１３が設けられている。図には、多層配線を例示するが、配線層１３は単層であってもよい。配線層１３と回路面１２ａとの間、配線層１３どうしの間、および最上層の配線層１３の上には、層間絶縁層１４が設けられている。
層間絶縁層１４は、例えば、酸化シリコン（ＳｉＯ）、窒化シリコン（ＳｉＮ）、酸窒化シリコン（ＳｉＯＮ）、炭化窒化シリコン（ＳｉＣＮ）、酸化炭化シリコン（ＳｉＯＣ）の少なくともいずれかを含む。
配線層１３は、いわゆるオンチップ配線層であり、樹脂中に設けられた再配線層（RDL:Redistribution Layer）とは異なる。
層間絶縁層１４の表面上には、樹脂層１５が設けられている。樹脂層１５には、例えばベンゾシクロブテン（ＢＣＢ）樹脂を用いる。あるいは、樹脂層１５には、ポリイミド樹脂、またはエポキシ樹脂を用いる。
シリコン基板１２には貫通電極１８が設けられている。また、シリコン基板１２の裏面１２ｂには、裏面電極１９が設けられている。貫通電極１８は、裏面電極１９が形成された位置でシリコン基板１２を貫通し、裏面電極１９と配線層１３とを接続している。貫通電極１８は、例えば、銅を主成分として含む金属を用いる。
貫通電極１８とシリコン基板１２との間には、貫通電極１８とシリコン基板１２との直接的な導通を防ぐ絶縁膜１７が設けられている。絶縁膜１７には、例えば、シリコン酸化膜、シリコン窒化膜、またはシリコン酸窒化膜を用いる。
樹脂層１５には、接合金属（または中間電極）２１が埋め込まれている。接合金属２１は、樹脂層１５、および層間絶縁層１４の一部を貫通して、配線層１３に接続している。接合金属２１には、例えば銅を主成分として含む金属を用いる。
以上説明した構造を有するチップ１１どうしが回路面１２ａ（配線層１３）側を対向させて接合され、２チップ積層体１０が形成されている。
互いのチップ１１の接合金属２１どうしが接合され、且つ樹脂層１５どうしが接合（接着）されている。
図１（ａ）において、例えば最下層の２チップ積層体１０における上側のチップ１１の裏面電極１９と、その上の２チップ積層体１０における下側のチップ１１の裏面電極１９との間にはバンプ３１が設けられている。バンプ３１は、例えば、はんだボール、または金属バンプであり、上下のチップ１１の裏面電極１９どうしを接続している。すなわち、複数の２チップ積層体１０どうしはバンプ接続されている。
図１（ａ）において、最下層の２チップ積層体１０における下側のチップ１１の裏面１２ｂには、再配線層４１が設けられている。最下層のチップ１１の裏面電極１９は、再配線層４１と接続されている。再配線層４１は、樹脂中に設けられ、チップ１１の配線層（オンチップ配線層）１３と、実装基板５１の配線層との接続を担う。
再配線層４１の下面にはバンプ（例えば、はんだボール、金属バンプ）３２が設けられ、そのバンプ３２を介して複数のチップ１１を含む積層体は、実装基板５１上にマウントされている。実装基板５１の裏面には、外部端子（例えば、はんだボール、金属バンプ）５２が設けられている。
実装基板５１上の積層体は、封止樹脂８０で覆われている。また、樹脂８５が、２チップ積層体１０と２チップ積層体１０との間に充填されている。すなわち、バンプ３１の接合部は樹脂８５で覆われ保護されている。
２チップ積層体１０における回路面１２ａどうしを対向させて接合された２つのチップ１１間の樹脂層１５のフィラー含有量は、バンプ３１を介して接続された２つのチップ１１間の樹脂８５のフィラー含有量よりも少ない。あるいは、樹脂層１５はフィラーを含まない。ウェーハ同士の接合では、バンプを介した接合に比較してチップ間の距離が短く、樹脂の熱膨張による信頼性への影響が小さいため、熱膨張を抑制するフィラー量は樹脂８５よりも少なくてもよい（あるいはフィラーが無くてもよい）。
複数のチップ１１のそれぞれの半導体集積回路（メモリ素子も含む）は、配線層１３、接合金属２１、貫通電極１８、裏面電極１９、バンプ３１、再配線層４１、およびバンプ３２を介して、実装基板５１の配線層と電気的に接続されている。そして、実装基板５１の配線層は、外部端子５２を介して、外部回路と接続される。
複数のチップ１１は、メモリチップであり、図１０に示すように、共通のデータ入出力端子９０に対して並列接続（バス接続）される。
すなわち、貫通電極１８、接合金属２１およびバンプ３１によってチップ積層方向に形成される共通のデータバス９１に対して、複数のチップ１１のデータ入出力線が並列接続している。
図１１は、図１（ａ）に示す半導体装置から、複数のチップ１１（複数の２チップ積層体１０）の積層体を抽出した模式断面図である。
図１１に示すように、互いの回路面１２ａどうしを対向させて積層された２つのチップ１１の回路面間ピッチをａ、互いの裏面どうしを対向させて積層された２つのチップ１１の回路面間ピッチをｂとすると、ａ＜ｂであり、また、ピッチａとピッチｂが複数チップの積層方向に交互に周期的に繰り返されている。
次に、図４〜図９を参照して、２チップ積層体１０の製造方法について説明する。図４〜図９に示す工程はウェーハ状態で進められ、図４〜図９にはウェーハＷ１、Ｗ２の一部断面を示している。
まず、ウェーハプロセスで、シリコン基板１２上に、前述した要素を形成する。そして、２枚のウェーハＷ１、Ｗ２を回路面１２ａ側を対向させて貼り合わせる。
図４には、貼り合わせ前の第１ウェーハＷ１と第２ウェーハＷ２を示す。第１ウェーハＷ１と第２ウェーハＷ２は、構造は同じで、貼り合わせ面を挟んで各要素が鏡像対称になっている。
第１ウェーハＷ１と第２ウェーハＷ２は、互いの対応する接合金属２１の位置を合わせて、図５に示すように貼り合わされる。加圧及び加熱下で２枚のウェーハＷ１、Ｗ２は貼り合わされ、接合金属２１どうしが接合されるとともに、樹脂層１５どうしが接着（ウェーハボンディング）される。
ウェーハボンディング後、図６に示すように、第１ウェーハＷ１のシリコン基板１２を裏面１２ｂ側から研削して薄化する。第１ウェーハＷ１のシリコン基板１２が薄くなっても、第２ウェーハＷ２のシリコン基板１２が支持体となる。あるいは、第１ウェーハＷ１のシリコン基板１２を支持体にして、先に第２ウェーハＷ２のシリコン基板１２を研削して薄化してもよい。
研削前のシリコン基板１２は例えば７００μｍ以上であり、研削により、シリコン基板１２は、貫通電極を形成する場合は例えば３０〜５０μｍ程度に、貫通電極を形成しない場合は例えば１００〜５００μｍ程度に薄化される。
第１ウェーハＷ１のシリコン基板１２を薄化した後、図６に示すように、シリコン基板１２を貫通して第１ウェーハＷ１の配線層１３に達するビア１６を形成する。例えば、ＲＩＥ（Reactive Ion Etching）などのエッチングによりビア１６が形成される。
図７に示すように、ビア１６の内壁、およびビア１６周囲のシリコン基板１２の裏面１２ｂには絶縁膜１７が形成される。そして、絶縁膜１７を介してビア１６内に貫通電極１８が埋め込まれる。また、シリコン基板１２の裏面１２ｂには貫通電極１８と接続した裏面電極１９が形成される。裏面電極１９とシリコン基板１２の裏面１２ｂとの間にも絶縁膜１７が介在される。
次に、図８に示すように、貫通電極１８が形成された第１ウェーハＷ１のシリコン基板１２の裏面１２ｂ側に支持体１００を貼り付ける。図８において、図７と上下を逆にして第１ウェーハＷ１及び第２ウェーハＷ２を示している。
支持体１００は、例えばガラス基板などの剛体である。支持体１００は接着層１０１を介して第１ウェーハＷ１のシリコン基板１２に貼り付けられる。
支持体１００によって第１ウェーハＷ１および第２ウェーハＷ２が支持された状態で、第２ウェーハＷ２のシリコン基板１２を裏面１２ｂ側から研削して薄化する。
第２ウェーハＷ２のシリコン基板１２を薄化した後、第１ウェーハＷ１に対するプロセスと同様に、シリコン基板１２を貫通して第２ウェーハＷ２の配線層１３に達するビアを形成する。
そして、図９に示すように、第２ウェーハＷ２のビア１６の内壁、およびビア１６周囲のシリコン基板１２の裏面１２ｂに絶縁膜１７が形成される。そして、絶縁膜１７を介してビア１６内に貫通電極１８が埋め込まれる。また、シリコン基板１２の裏面１２ｂには貫通電極１８と接続した裏面電極１９が形成される。裏面電極１９とシリコン基板１２の裏面１２ｂとの間にも絶縁膜１７が介在される。また、必要に応じて、裏面電極１９上にバンプ３１が形成される。
その後、第１ウェーハＷ１および第２ウェーハＷ２の接合体をダイシングし、支持体１００を除去（剥離）することで、個片化された２チップ積層体１０が得られる。
例えば、支持体１００がダイシングテープに貼り付けられた状態で、第２ウェーハＷ２および第１ウェーハＷ１がダイシングされる。あるいは、支持体１００を剥離してから第１ウェーハＷ１および第２ウェーハＷ２をダイシングしてもよい。
実施形態の２チップ積層体１０は、個片化した２チップのチップトゥチップボンディングではなく、ウェーハトゥウェーハボンディングの後のダイシングにより得られる。したがって、２チップ積層体１０は、連続した側面を有する直方体形状に形成される。
個片化された複数の２チップ積層体１０は、図１（ａ）に示すように、実装基板５１上に積層され、複数の２チップ積層体１０どうしの間には樹脂８５が充填される。あるいは、複数の２チップ積層体１０を、樹脂フィルムを介して貼り合わせて積層してもよい。
また、図２（ａ）、図２（ｂ）、図３（ａ）に示すように、２チップ積層体１０に対して、１つのチップ１１がバンプ３１を介して積層された構造でもよい。
ＴＳＶ（Through-Silicon Via）構造において、基板を薄くすれば貫通電極の表面積が小さくなり、絶縁膜を挟んで対向する貫通電極と基板との間の寄生容量を低減できる。しかしながら、基板が薄くなると、チップどうしのボンディング、チップと実装基板とのボンディングなどの組み立てプロセスにおいてハンドリングが困難になる問題が生じる。
そこで、以上説明した実施形態によれば、２枚のウェーハＷ１、Ｗ２を回路面１２ａ側を対向させてウェーハトゥウェーハボンディングした後、一方のウェーハＷ２のシリコン基板１２を支持体として、他方のウェーハＷ１のシリコン基板１２を薄化して貫通電極１８を形成する。その後、一方のウェーハＷ１のシリコン基板１２側に支持体（剛体）１００を貼り付けた後、他方のウェーハＷ２のシリコン基板１２を薄化して、ウェーハＷ２にも貫通電極１８を形成する。
そのため、ハンドリングの困難性をきたすことなく、２チップ積層体１０のそれぞれの基板１２を薄化した上でＴＳＶ構造を形成することができる。参照例として、チップトゥチップで２チップを積層した構造に比べて、実施形態の２チップ積層体１０によれば基板１２の厚さを約１／２にすることができる。
したがって、絶縁膜１７を挟んでシリコン基板１２に対向する貫通電極１８の表面積を参照例に比べて約１／２にすることが可能となり、貫通電極１８と基板１２間の寄生容量を約１／２に低減することができる。
特に、記憶容量の大容量化にともないチップ１１の積層数が増大すると、ＴＳＶの数も増え、その寄生容量の影響も大きくなる傾向にあるが、実施形態によれば、基板１２の薄化によりＴＳＶの寄生容量を低減することで、結果として消費電力の低減を図れる。
また、２チップ積層体１０は、接合面を挟んで断面構造が鏡像対称にある同じチップ１１どうしがボンディングされた構造であるため、それぞれのチップ１１に発生する反りが相殺されて、２チップ積層体１０としては反りの小さいものが得られる。
図１（ａ）には、例えば、４組の２チップ積層体１０の積層構造を例示したが、２組または３組の２チップ積層体１０の積層構造でもよく、また、５組以上の２チップ積層体１０を積層させてもよい。
また、図２（ａ）に示すように、再配線層４１を上に向けて複数チップ１１の積層体を実装基板５１にボンディングし、最上層の再配線層４１と、実装基板５１とをワイヤ６１によってボンディングしてもよい。
また、図２（ｂ）に示すように、実装基板５１を用いずに、複数のチップ１１の積層体を再配線層４１を介して直接外部端子５２に接続させてもよい。
また、図３（ａ）に示すように、最下層のチップ１１の下の再配線層４１の下にロジックチップ７１を搭載してもよい。ロジックチップ７１はバンプ（例えば、はんだボール、金属バンプ）７２を介して再配線層４１に接合している。ロジックチップ７１は、再配線層４１を介して、例えば最下層のチップ１１（貫通電極、配線層）に電気的に接続している。
ロジックチップ７１は、各メモリチップ１１を制御するＩＦ（interface）／コントローラチップである。
また、図３（ｂ）に示すように、貫通電極１８がないチップ１１と、貫通電極１８を持つチップ１１とが接合金属２１及び樹脂層１５を介して接合された２チップ積層体１０’が含まれていてもよい。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１０…２チップ積層体、１１…チップ、１２…シリコン基板、１２ａ…回路面、１２ｂ…裏面、１３…配線層、１５…樹脂層、１６…ビア、１７…絶縁膜、１８…貫通電極、１９…裏面電極、２１…接合金属、３１…バンプ、５１…実装基板、７１…ロジックチップ、８０…樹脂、１００…支持体

Claims (8)

  1. 第１回路面と、前記第１回路面の反対側の第１裏面とを有する第１半導体層と、前記第１回路面に設けられた第１配線層と、前記第１半導体層を貫通して設けられ、前記第１配線層に接続された第１貫通電極と、を有する第１チップと、
    前記第１チップの前記第１配線層側に積層された第２チップであって、前記第１配線層に対向した第２回路面と、前記第２回路面の反対側の第２裏面とを有する第２半導体層と、前記第２回路面に設けられ、前記第１チップの前記第１配線層と接続された第２配線層と、前記第２半導体層を貫通して設けられ、前記第２配線層に接続された第２貫通電極と、を有する第２チップと、
    前記第２チップの前記第２裏面側に積層された第３チップであって、第３回路面と、前記第３回路面の反対側に位置し、前記第２チップに対向した第３裏面とを有する第３半導体層と、前記第３回路面に設けられた第３配線層と、前記第３半導体層を貫通して設けられ、前記第３配線層に接続されるとともに、バンプを介して前記第２チップの前記第２貫通電極と接続された第３貫通電極と、を有する第３チップと、
    を備えた半導体装置。
  2. 前記第１チップ、前記第２チップおよび前記第３チップのデータ入出力線は、共通のデータ入出力端子に対して並列接続されるメモリチップである請求項１記載の半導体装置。
  3. 前記第１チップの前記第１裏面側に設けられ、前記第１貫通電極に接続され、前記第１チップ、前記第２チップおよび前記第３チップを制御するロジックチップをさらに備えた請求項１または２に記載の半導体装置。
  4. 前記第１チップと前記第２チップとの積層体は、連続した側面を有する直方体形状である請求項１〜３のいずれか１つに記載の半導体装置。
  5. 前記第３チップの前記第３配線層側に積層された第４チップであって、前記第３配線層に対向した第４回路面を有する第４半導体層と、前記第４回路面に設けられ、前記第３配線層と接続された第４配線層と、を有する第４チップをさらに備えた請求項１〜４のいずれか１つに記載の半導体装置。
  6. 前記第４チップは、前記第４半導体層を貫通して設けられ、前記第４配線層と接続された第４貫通電極をさらに有し、
    前記第３チップと前記第４チップとの積層体は、連続した側面を有する直方体形状である請求項５記載の半導体装置。
  7. 前記第１チップと前記第２チップとの間に設けられた樹脂層と、
    前記第２チップと前記第３チップとの間に設けられた封止樹脂と、をさらに備え、
    前記第１チップと前記第２チップとの間の前記樹脂層のフィラー含有量は、前記第２チップと前記第３チップとの間の前記封止樹脂のフィラー含有量よりも少ない請求項１〜６のいずれか１つに記載の半導体装置。
  8. 第１回路面と前記第１回路面の反対側の第１裏面とを有する第１基板と、前記第１回路面に設けられた第１配線層と、前記第１配線層上に設けられ、前記第１配線層と接続された第１接合金属と、を有する第１ウェーハの前記第１回路面と、
    第２回路面と前記第２回路面の反対側の第２裏面とを有する第２基板と、前記第２回路面に設けられた第２配線層と、前記第２配線層上に設けられ、前記第２配線層と接続された第２接合金属と、を有する第２ウェーハの前記第２回路面と、
    を対向させ、前記第１接合金属と前記第２接合金属とを接合させて、前記第１ウェーハと前記第２ウェーハとを貼り合わせ、
    前記第１ウェーハと前記第２ウェーハとが貼り合わされた状態で、前記第１基板を前記第１裏面側から研削し、
    前記研削により薄化された前記第１基板に、前記第１基板を貫通して前記第１配線層に達する第１貫通電極を形成し、
    前記第１貫通電極が形成された前記第１基板の前記第１裏面側に支持体を貼り付けた状態で、前記第２基板を前記第２裏面側から研削し、
    前記研削により薄化された前記第２基板に、前記第２基板を貫通して前記第２配線層に達する第２貫通電極を形成し、
    前記第２貫通電極を形成した後、前記支持体を除去、および前記第１ウェーハと前記第２ウェーハとの接合体を複数のチップに個片化し、
    個片化された複数のチップを積層する
    半導体装置の製造方法。
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017120914A (ja) * 2015-12-29 2017-07-06 台湾積體電路製造股▲ふん▼有限公司Ｔａｉｗａｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｍｐａｎｙ，Ｌｔｄ． インターティア相互接続を有するスタック基板構造
WO2018168198A1 (ja) * 2017-03-15 2018-09-20 東芝メモリ株式会社 半導体記憶装置
JP2019169556A (ja) * 2018-03-22 2019-10-03 東芝メモリ株式会社 半導体装置およびその製造方法
US10510725B2 (en) 2017-09-15 2019-12-17 Toshiba Memory Corporation Semiconductor device
WO2020035898A1 (ja) * 2018-08-13 2020-02-20 ウルトラメモリ株式会社 半導体モジュール及びその製造方法
WO2020085259A1 (ja) * 2018-10-23 2020-04-30 株式会社ダイセル 半導体装置製造方法
WO2020085251A1 (ja) * 2018-10-23 2020-04-30 株式会社ダイセル 半導体装置製造方法
WO2020085257A1 (ja) * 2018-10-23 2020-04-30 株式会社ダイセル 半導体装置製造方法
WO2020188719A1 (ja) * 2019-03-18 2020-09-24 キオクシア株式会社 半導体装置およびその製造方法
JPWO2022014022A1 (ja) * 2020-07-16 2022-01-20
WO2023105688A1 (ja) * 2021-12-08 2023-06-15 株式会社レゾナック 積層体の作製方法、及び、積層体
WO2023203765A1 (ja) * 2022-04-22 2023-10-26 株式会社レゾナック 半導体装置の製造方法、及び、半導体装置
JP7548455B2 (ja) 2021-12-08 2024-09-10 株式会社レゾナック 積層体の作製方法、及び、積層体

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170044919A (ko) * 2015-10-16 2017-04-26 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR102423813B1 (ko) * 2015-11-27 2022-07-22 삼성전자주식회사 반도체 소자
CN105470237B (zh) * 2015-12-09 2018-04-17 西安交通大学 基于穿硅电容的三维容性耦合立体集成互连结构
JP2018117102A (ja) * 2017-01-20 2018-07-26 ソニーセミコンダクタソリューションズ株式会社 半導体装置
JP6649308B2 (ja) * 2017-03-22 2020-02-19 キオクシア株式会社 半導体装置およびその製造方法
JP2019054199A (ja) * 2017-09-19 2019-04-04 東芝メモリ株式会社 半導体装置
US10790262B2 (en) * 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10622321B2 (en) * 2018-05-30 2020-04-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structures and methods of forming the same
CN108987425B (zh) * 2018-07-19 2020-09-18 豪威半导体（上海）有限责任公司 微led显示器及其制造方法
DE102019119708A1 (de) * 2018-07-31 2020-02-06 Taiwan Semiconductor Manufacturing Co., Ltd. 3d-ic-energienetz
US11081426B2 (en) 2018-07-31 2021-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC power grid
JP2020155485A (ja) * 2019-03-18 2020-09-24 キオクシア株式会社 半導体装置およびその製造方法
JP2020178010A (ja) 2019-04-17 2020-10-29 キオクシア株式会社 半導体記憶装置
US10840190B1 (en) * 2019-05-16 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US10886245B2 (en) * 2019-05-30 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure, 3DIC structure and method of fabricating the same
JP2021044347A (ja) * 2019-09-10 2021-03-18 キオクシア株式会社 半導体装置
KR102673730B1 (ko) * 2019-11-07 2024-06-10 삼성전자주식회사 반도체 소자 및 이를 구비한 반도체 패키지
CN111106022A (zh) * 2019-12-30 2020-05-05 武汉新芯集成电路制造有限公司 一种键合结构及其制造方法
JP2022141179A (ja) * 2021-03-15 2022-09-29 キオクシア株式会社 半導体装置の製造方法、及び半導体装置
TW202324523A (zh) * 2021-11-30 2023-06-16 群創光電股份有限公司 電子裝置的製造方法
TWI821835B (zh) * 2021-12-23 2023-11-11 大陸商青島新核芯科技有限公司 基板結構及其製造方法
CN115719736B (zh) * 2022-11-30 2024-07-12 无锡芯光互连技术研究院有限公司 一种芯片堆叠结构及其制作方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299432A (ja) * 1999-04-15 2000-10-24 Rohm Co Ltd 半導体装置の製造方法
JP2001291803A (ja) * 2000-04-04 2001-10-19 Rohm Co Ltd 半導体装置
JP2002198487A (ja) * 2000-12-26 2002-07-12 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2004327474A (ja) * 2003-04-21 2004-11-18 Elpida Memory Inc メモリモジュール及びメモリシステム
JP2009010312A (ja) * 2007-06-26 2009-01-15 Hynix Semiconductor Inc スタックパッケージ及びその製造方法
JP2009188400A (ja) * 2008-02-01 2009-08-20 Promos Technologies Inc 積層構造を有する半導体素子及び該半導体素子の製造方法
WO2011115041A1 (ja) * 2010-03-17 2011-09-22 東京エレクトロン株式会社 半導体装置の製造方法及び半導体装置
JP2012004383A (ja) * 2010-06-17 2012-01-05 Hamamatsu Photonics Kk 半導体集積回路装置の検査方法及び半導体集積回路装置
JP2012243973A (ja) * 2011-05-20 2012-12-10 Panasonic Corp 半導体装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0476946A (ja) 1990-07-19 1992-03-11 Fujitsu Ltd ウエーハ集積回路装置
JP4205613B2 (ja) 2004-03-01 2009-01-07 エルピーダメモリ株式会社 半導体装置
JP4353330B2 (ja) * 2006-11-22 2009-10-28 エルピーダメモリ株式会社 半導体装置および半導体チップ
JP2008135553A (ja) 2006-11-28 2008-06-12 Fujitsu Ltd 基板積層方法及び基板が積層された半導体装置
US7791175B2 (en) * 2007-12-20 2010-09-07 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
JP5192930B2 (ja) 2008-07-14 2013-05-08 パナソニック株式会社 接合方法
US7993976B2 (en) * 2009-06-12 2011-08-09 Stats Chippac, Ltd. Semiconductor device and method of forming conductive vias with trench in saw street
KR101078744B1 (ko) * 2010-05-06 2011-11-02 주식회사 하이닉스반도체 적층 반도체 패키지
US9263314B2 (en) * 2010-08-06 2016-02-16 Brewer Science Inc. Multiple bonding layers for thin-wafer handling
US9018730B2 (en) * 2011-04-05 2015-04-28 Stmicroelectronics S.R.L. Microstructure device comprising a face to face electromagnetic near field coupling between stacked device portions and method of forming the device
JP5646758B2 (ja) * 2011-08-11 2014-12-24 東京エレクトロン株式会社 半導体装置の製造方法、半導体装置及び配線形成用治具
JP2013219319A (ja) * 2012-03-16 2013-10-24 Sony Corp 半導体装置、半導体装置の製造方法、半導体ウエハ、及び、電子機器
JP2013214556A (ja) 2012-03-30 2013-10-17 Olympus Corp ウェハ積層体、半導体装置およびその製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299432A (ja) * 1999-04-15 2000-10-24 Rohm Co Ltd 半導体装置の製造方法
JP2001291803A (ja) * 2000-04-04 2001-10-19 Rohm Co Ltd 半導体装置
JP2002198487A (ja) * 2000-12-26 2002-07-12 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2004327474A (ja) * 2003-04-21 2004-11-18 Elpida Memory Inc メモリモジュール及びメモリシステム
JP2009010312A (ja) * 2007-06-26 2009-01-15 Hynix Semiconductor Inc スタックパッケージ及びその製造方法
JP2009188400A (ja) * 2008-02-01 2009-08-20 Promos Technologies Inc 積層構造を有する半導体素子及び該半導体素子の製造方法
WO2011115041A1 (ja) * 2010-03-17 2011-09-22 東京エレクトロン株式会社 半導体装置の製造方法及び半導体装置
JP2012004383A (ja) * 2010-06-17 2012-01-05 Hamamatsu Photonics Kk 半導体集積回路装置の検査方法及び半導体集積回路装置
JP2012243973A (ja) * 2011-05-20 2012-12-10 Panasonic Corp 半導体装置

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017120914A (ja) * 2015-12-29 2017-07-06 台湾積體電路製造股▲ふん▼有限公司Ｔａｉｗａｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｍｐａｎｙ，Ｌｔｄ． インターティア相互接続を有するスタック基板構造
WO2018168198A1 (ja) * 2017-03-15 2018-09-20 東芝メモリ株式会社 半導体記憶装置
JP2018156968A (ja) * 2017-03-15 2018-10-04 東芝メモリ株式会社 半導体記憶装置
US11594523B2 (en) 2017-03-15 2023-02-28 Kioxia Corporation Semiconductor memory device
US11145625B2 (en) 2017-03-15 2021-10-12 Toshiba Memory Corporation Semiconductor memory device
EP3598493A4 (en) * 2017-03-15 2021-01-20 Toshiba Memory Corporation SEMI-CONDUCTOR STORAGE DEVICE
US10510725B2 (en) 2017-09-15 2019-12-17 Toshiba Memory Corporation Semiconductor device
US10777529B2 (en) 2018-03-22 2020-09-15 Toshiba Memory Corporation Semiconductor device and method for manufacturing same
JP2019169556A (ja) * 2018-03-22 2019-10-03 東芝メモリ株式会社 半導体装置およびその製造方法
WO2020035898A1 (ja) * 2018-08-13 2020-02-20 ウルトラメモリ株式会社 半導体モジュール及びその製造方法
WO2020085251A1 (ja) * 2018-10-23 2020-04-30 株式会社ダイセル 半導体装置製造方法
JP7201387B2 (ja) 2018-10-23 2023-01-10 株式会社ダイセル 半導体装置製造方法
KR102609475B1 (ko) 2018-10-23 2023-12-06 주식회사 다이셀 반도체 장치 제조 방법
WO2020085257A1 (ja) * 2018-10-23 2020-04-30 株式会社ダイセル 半導体装置製造方法
KR20210081380A (ko) * 2018-10-23 2021-07-01 주식회사 다이셀 반도체 장치 제조 방법
JPWO2020085257A1 (ja) * 2018-10-23 2021-09-16 株式会社ダイセル 半導体装置製造方法
JP2020068254A (ja) * 2018-10-23 2020-04-30 株式会社ダイセル 半導体装置製造方法
US11791284B2 (en) 2018-10-23 2023-10-17 Daicel Corporation Semiconductor device manufacturing method
JP7350006B2 (ja) 2018-10-23 2023-09-25 株式会社ダイセル 半導体装置製造方法
JP2020068252A (ja) * 2018-10-23 2020-04-30 株式会社ダイセル 半導体装置製造方法
JP7211758B2 (ja) 2018-10-23 2023-01-24 株式会社ダイセル 半導体装置製造方法
WO2020085259A1 (ja) * 2018-10-23 2020-04-30 株式会社ダイセル 半導体装置製造方法
WO2020188719A1 (ja) * 2019-03-18 2020-09-24 キオクシア株式会社 半導体装置およびその製造方法
WO2022014022A1 (ja) * 2020-07-16 2022-01-20 ウルトラメモリ株式会社 半導体装置及びその製造方法
JPWO2022014022A1 (ja) * 2020-07-16 2022-01-20
WO2023105688A1 (ja) * 2021-12-08 2023-06-15 株式会社レゾナック 積層体の作製方法、及び、積層体
JP7548455B2 (ja) 2021-12-08 2024-09-10 株式会社レゾナック 積層体の作製方法、及び、積層体
WO2023203765A1 (ja) * 2022-04-22 2023-10-26 株式会社レゾナック 半導体装置の製造方法、及び、半導体装置

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