TW201438185A - 半導體裝置及積層型半導體裝置之製造方法 - Google Patents

半導體裝置及積層型半導體裝置之製造方法 Download PDF

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TW201438185A
TW201438185A TW102129171A TW102129171A TW201438185A TW 201438185 A TW201438185 A TW 201438185A TW 102129171 A TW102129171 A TW 102129171A TW 102129171 A TW102129171 A TW 102129171A TW 201438185 A TW201438185 A TW 201438185A
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Taiwan
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substrate
wafer
semiconductor
resin
laminated body
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TW102129171A
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English (en)
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TWI545723B (zh
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Takao Sato
Masatoshi Fukuda
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Toshiba Kk
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Abstract

本發明之目的在於提供一種切斷面良好且容易安裝並可小型化之積層型半導體裝置。本發明之積層型半導體裝置之製造方法其特徵在於包含：於第1基板20上，將第一層半導體晶片11a複數排列於同一平面上且接著之步驟；於上述半導體晶片11a上分別積層至少一層以上之半導體晶片11b~11h之步驟；將上述第1基板20切斷而分離成各晶片積層體10之步驟；以形成於晶片積層體10之表面之電極焊墊部與第2基板30之電極焊墊部一致之方式使其對位並對向而暫時連接之步驟；將第2基板30及晶片積層體10整體回焊，而將電極焊墊部間電性連接之步驟；自晶片積層體10之第1基板側沿著積層體供給液態樹脂(密封樹脂40)，而將各半導體晶片間及晶片積層體10與第2基板30間樹脂密封之步驟；及自晶片積層體10之第2基板30側以切割刀片切斷而單片化之步驟。

Description

半導體裝置及積層型半導體裝置之製造方法 [相關申請]
本申請案享有以日本專利申請案第2013-58303號(申請日：2013年3月21日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於半導體裝置及積層型半導體裝置之製造方法。
在形成對NAND型快閃記憶體等之高容量有所需求之元件時，有人提出有將經薄厚度加工之半導體晶片複數積層且樹脂密封之方法，或將預先樹脂密封半導體晶片者複數積層之方法。各半導體晶片之信號之取出一般採用打線接合法，為使信號傳遞速度進而高速化，有人提出有採用TSV(Through Silicon VIA：矽穿孔)方式之積層方式(例如，日本專利公開公報第2010-251408號)。在該積層方式中，於設有密封材料流出防止體之金屬製之搬送基板上，按序積層晶片且以樹脂密封晶片間。此時，以露出最上層之介面晶片之凸塊之方式填充樹脂。且，將單片之配線基板連接於最上層之介面晶片之連接端子。又，揭示有在對周邊進行鑄模密封後，統一切割搬送基板與鑄模樹脂之技術。此方法係極為高效之安裝方法。然而，由於密封材料流出防止體之部分而不得不增大搬送基板，故致使封裝大型化。此外，在藉由刀片進行切斷時，具有切斷面完成不足之問題。
本發明之一實施形態之目的在於提供一種可實現小型化且切斷面完成良好之半導體裝置。
根據本發明之一實施形態，其特徵在於具備：於第1基板上，將第一層半導體晶片複數排列於同一平面上且接著之步驟；於上述半導體晶片上分別積層至少一層以上之半導體晶片之步驟；將上述第1基板切斷而分離成各積層體之步驟；以形成於上述積層體之表面之電極焊墊部與第2基板之電極焊墊部一致之方式使其對位並對向而暫時連接之步驟；將上述第2基板及積層體整體回焊，而將電極焊墊部間電性連接之步驟；自上述積層體之上述第1基板側沿著上述積層體供給樹脂，而將各半導體晶片間及上述積層體與上述第2基板間樹脂密封之步驟；及將經樹脂密封之積層體與上述第1基板及第2基板同時以切割刀片切斷而單片化之步驟。
1‧‧‧積層型半導體裝置
2‧‧‧積層型半導體裝置
10‧‧‧晶片積層體
11a~11h‧‧‧半導體晶片
11p‧‧‧焊墊電極
12‧‧‧貫通電極
13‧‧‧焊墊電極
14‧‧‧接著劑
15‧‧‧重配線
15a‧‧‧絕緣膜
15b‧‧‧配線層
16‧‧‧保護膜
17‧‧‧電極焊墊
18‧‧‧IF晶片
20‧‧‧第1基板
21‧‧‧樹脂薄膜
22‧‧‧接著劑
30‧‧‧第2基板
31‧‧‧樹脂基板
31A‧‧‧樹脂基板之第1面
31B‧‧‧樹脂基板之第2面
32‧‧‧外部連接端子
33‧‧‧內部連接端子
34‧‧‧焊錫球
35‧‧‧焊錫球
40‧‧‧密封樹脂
40a‧‧‧第1密封樹脂
40b‧‧‧第2密封樹脂
115‧‧‧配線基板
120‧‧‧搬送基板
135‧‧‧外部連接用之焊錫球
140a‧‧‧樹脂
140b‧‧‧鑄模樹脂
210‧‧‧晶片積層體
B1‧‧‧刀片
B2‧‧‧刀片
T1‧‧‧切割膠帶
T2‧‧‧切割膠帶
圖1-1係模式性顯示第1實施形態之半導體裝置之剖面圖。
圖1-2係相同半導體裝置之主要部分放大剖面圖。
圖1-3係相同半導體裝置之主要部分放大剖面圖。
圖2-1係顯示相同半導體裝置之製造步驟之步驟剖面圖。
圖2-2係顯示相同半導體裝置之製造步驟之步驟剖面圖。
圖2-3係顯示相同半導體裝置之製造步驟之步驟剖面圖。
圖2-4係顯示相同半導體裝置之製造步驟之步驟剖面圖。
圖2-5係顯示相同半導體裝置之製造步驟之步驟剖面圖。
圖2-6係顯示相同半導體裝置之製造步驟之步驟剖面圖。
圖2-7係顯示相同半導體裝置之製造步驟之步驟剖面圖。
圖2-8係顯示相同半導體裝置之製造步驟之步驟剖面圖。
圖3係模式性顯示第2實施形態之半導體裝置之構成之剖面圖。
圖4-1係顯示相同半導體裝置之製造步驟之步驟剖面圖。
圖4-2係顯示相同半導體裝置之製造步驟之步驟剖面圖。
圖4-3係顯示相同半導體裝置之製造步驟之步驟剖面圖。
圖5係模式性顯示比較例之半導體裝置之構成之一例之剖面圖。
以下，參照附加圖式，詳細說明實施形態之積層型半導體裝置及其製造方法。另，在本實施形態中，雖對使用NAND型快閃記憶體等之記憶體晶片來作為半導體晶片之半導體記憶裝置進行說明，但並非藉由該等之實施形態而限定本發明。又，於以下所示之圖式中，為便於理解而存在各構件之縮尺與實際不同之情形。此外，表示上下等方向之情形係表示將圖2之圖式符號為正方向之情形作為基準之相對性方向，有時與以實際之重力加速度方向作為基準之情形不同。
(第1實施形態)
圖1-1係模式性顯示第1實施形態之半導體記憶裝置之剖面圖，圖1-2及圖1-3係同圖之主要部分放大剖面圖。圖2-1至圖2-8係顯示相同半導體裝置之製造步驟之步驟剖面圖。本實施形態之半導體裝置1具備：第1及第2基板20、30，該等係相對向而配置，且尺寸相同；複數層之半導體晶片11a~11h之晶片積層體10，其係被夾持於第1及第2基板20、30間，且至少與一者電性連接；及密封樹脂40。該密封樹脂40之特徵在於：將第1及第2基板20、30之間、構成晶片積層體10之半導體晶片11a~11h之間、及第1及第2基板20、30與上述晶片積層體10之間加以密封，且該密封樹脂40之外緣位於連結第1及第2基板20、30之外緣之線上。
在本實施形態中，使用容易切斷之樹脂基板等作為第1基板20，且於第1基板20上，在積層半導體晶片11a~11h後，連同切斷第1基板 20而形成晶片積層體10。接著，將該晶片積層體10連接於第2基板30(配線基板)上，且供給液態之密封樹脂40使其硬化。如此，藉由對各半導體晶片11a~11h之間、及晶片積層體10與上述第2基板30之間進行樹脂密封，繼而以切割刀片B1切斷且單片化而形成。
第2基板30具有樹脂基板31，且於該樹脂基板31之第1面31A上形成有外部連接端子32。在將半導體記憶裝置作為BGA(ball grid array：球柵格陣列)封裝而使用之情形時，外部連接端子32係以具有焊錫球、鍍錫、鍍Au(金)等之突起端子而構成。在將半導體記憶裝置作為LGA(land grid array：平面柵格陣列)封裝而使用之情形時，設置金屬焊盤以作為外部連接端子32。內部連接端子33設置於樹脂基板31之第2面31B，且介隔焊錫球34而與晶片積層體10之電極焊墊17連接。內部連接端子33係在與晶片積層體10連接時作為連接部(連接焊墊)而發揮功能者，且經由第2基板30之配線網(未圖示)與外部連接端子32電性連接。於樹脂基板31之第2面31B上，固定具有複數之半導體晶片11(11a~11h)之晶片積層體10。
其次，對本實施形態之半導體裝置之製造方法進行說明。首先，作為第1基板20，準備將PI(聚醯亞胺)等之具有耐熱性之樹脂薄膜21黏附且保持於例如金屬框架上者，且使之可搬送。此處，使用在樹脂薄膜21上形成有熱硬化性之接著劑22者作為第1基板20。於該第1基板20上之特定之位置，接著作為積層體之第一層之半導體晶片11a。第一層之半導體晶片11a以特定之間隔複數排列而搭載於樹脂薄膜21之一平面上(圖2-1)。實際係預先於樹脂薄膜上形成銅箔等之圖案，且將其作為記號而搭載半導體晶片。該圖案亦可於切割時使用。
其後，於各半導體晶片11a上，按序積層特定層數之半導體晶片(11b~11h)，而形成各晶片積層體10。此時半導體晶片11a~11h係以使相互間之連接為分別形成於(矽)貫通電極12之兩面之焊墊電極11p 與凸塊電極13抵接之方式對位且積層，而形成晶片積層體10。接著，於積層之半導體晶片11a~11h之一面上，接著劑14以複數而散佈之方式形成於電性連接之焊墊電極11p以外之部位，且在積層半導體晶片11a~11h時，與另一側之半導體晶片之對應之面接著並固定(圖2-2)。
其次，在位於晶片積層體10之最上層之記憶體晶片11h上，於表面形成有重配線15，且搭載介面晶片(IF晶片)18。重配線15係如圖1-3中主要部分放大剖面圖所示，以形成於最上層之半導體晶片11h表面之絕緣膜15a與配線層15b構成，且在與IF晶片18之連接位置、及與第2基板20即配線基板之連接位置形成有電極焊墊17。該IF晶片18具備用以於構成晶片積層體10之複數之記憶體晶片即半導體晶片11a~11h與外部元件之間進行資料通訊之介面(IF)電路。IF晶片18相對晶片積層體10而覆晶連接(FC(Flip Chip)連接)，且在與晶片積層體10之間填充液態樹脂，而構成密封樹脂40之一部分(圖2-3)。
繼而，在較各積層體之晶片更大之位置，切斷積層體周邊之樹脂薄膜而形成個別之積層體(圖2-4)。切斷之方法亦可為使用模具之方法、使用刀具之方法、及藉由刀片切割而進行之方法等中任一者。亦可預先準備在比晶片更大之形狀之位置設置有狹縫等之形狀，且於該位置進行切斷。
其次，將個別之晶片積層體10，以相對於配線基板即第2基板30可見到晶片側之內部連接端子(電極焊墊)33之朝向，即以使黏著有晶片積層體10之第1基板(樹脂薄膜)20側成為距第2基板30較遠側之方式，進行晶片積層體10與第2基板30之對應之內部連接端子33之對位後，藉由預先塗佈之暫時固定材料而進行暫時接著。其後，藉由在甲酸氛圍等之還原氛圍中進行加熱(回焊)，使晶片積層體10與第2基板30電性連接(圖2-5)。電極焊墊17(內部連接端子33)同時進行以焊錫材料或Au作為主成分之積層體之半導體晶片11a~11h相互間、與晶片積 層體10之最上層之半導體晶片11h~第2基板30間之電性連接。又，晶片積層體10之最上層之半導體晶片11h~第2基板30間之電性連接亦可另外進行。此處，使用還原氛圍之原因在於，為確實地進行電性連接，而還原且去除形成於表面之氧化膜等。積層之各半導體晶片11a~11h間，使用將以Cu(銅)作為主要成分之貫通電極12形成於與各電極焊墊(內部連接端子33)對應之位置上者。又，根據需要，所謂積層之複數之半導體晶片亦可應用搭載尺寸不同之半導體晶片之構造。
繼而，於晶片積層體10之各半導體晶片11a~11h間、及積層體最上層之半導體晶片11h與第2基板30之間，批次填充液態樹脂而形成密封樹脂40(圖2-6)。
最後，黏著於切割膠帶T1，且自晶片積層體10之第1基板20(樹脂薄膜)側，以基板上之辨識標記為基準進行對位，並以使用刀片B1之刀片切割進行單片之封裝化(圖2-7)。此時，於作為第1基板20之樹脂薄膜之下側，存在密封各半導體晶片11a~11h間之密封樹脂40。接著，在進行刀片切割時，預先黏著於切割膠帶T1以不使其分散，且藉由同時切斷包含樹脂薄膜之第1基板20、密封樹脂40、及第2基板30，可最大限度地實現小型化並可取得切斷面整齊之構造(圖2-8)。接著，向配線基板搭載時，係自切割膠帶T1以夾頭(未圖示)等抓持已成單片之積層型半導體裝置1，且收納於托盤等。如此完成圖1-1所示之積層型半導體裝置1。
如上所示，可自薄板即第1基板20之下方塗佈液態樹脂，而進行半導體晶片11a~11h間、及晶片積層體10之最上層之半導體晶片11h~第2基板30(配線基板)間之密封。又，此時，因於尺寸較半導體晶片更大之第1基板20之下方存在密封樹脂40，故可於接近半導體晶片之位置進行刀片切割。因此，藉由穩定之切斷步驟，可製作出接近晶片級之封裝。又，因可以此種方式切斷，而不必再次將整體進行鑄模密 封，故可使用1種樹脂，從而提高製造作業性。又，由於回焊之步驟亦1次完成，故可削減製造步驟中之熱應力，從而提高可靠性。即，可實現封裝之小型化、成本下降、步驟之合理化、及可靠性之提高。密封樹脂40係使液態樹脂硬化而獲得者。再者，由於在對基板進行暫時連接後，進行晶片積層體部之凸塊連接，故不會因晶片積層體搭載於基板時之應力等而使凸塊連接部破裂。
另，第2基板30係例如於絕緣樹脂基板之表面及內部設置有配線網(未圖示)者，具體而言，係應用使用玻璃環氧樹脂或BT樹脂(雙馬來醯亞胺．三嗪樹脂)等之絕緣樹脂之印刷配線板(多層印刷基板等)。
晶片積層體10係藉由將最下層之半導體晶片11a之下表面(非電路面)以熱硬化性之接著劑22接著於構成第1基板20之樹脂薄膜21，而安裝於第1基板20上。晶片積層體10之積層順序中最下層之半導體晶片11a，係僅以包含絕緣性樹脂等之接著劑22進行接著，而未與第1基板20直接電性連接。最下層之半導體晶片11a經由複數之半導體晶片11b~11h，而與設置於第2基板30之配線電性連接。
晶片積層體10經由分別設置於第2層至最上層之半導體晶片11b~11h之內部之貫通電極(Through Silicon Via：TSV：矽穿孔)12、與連接該等貫通電極12間之凸塊電極13，而使各自鄰接之半導體晶片11a~11h間電性連接。半導體晶片11b~11h按序積層於接著於第1基板20之記憶體晶片即半導體晶片11a上。最下層之半導體晶片11a僅以接著劑22與第1基板20接著，且僅與第2層半導體晶片11b電性連接。因此，最下層之半導體晶片11a不具有貫通電極。亦可根據需要令貫通電極形成於最下層之半導體晶片11a，而用於配線之佈設。
如上所示，複數之半導體晶片11a~11h係經由設置於除最下層之半導體晶片11a外之半導體晶片11b~11h之貫通電極12與凸塊電極13而電性連接。在圖1-1中簡化而顯示有鄰接之半導體晶片間之電性連接 構造。具體而言，藉由使以與貫通電極12電性連接之方式而形成於下層側之半導體晶片之上表面(電路面)之凸塊電極11p、與以與貫通電極12電性連接之方式而形成於上層側之半導體晶片之下表面(非電路面)之凸塊電極13接觸，且熔融至少一者之電極端子而一體化，而使鄰接之半導體晶片11a~11h間電性連接。如圖1-2中主要部分放大圖所示，凸塊電極13係在圖1-1中記載作為與凸塊電極11p之連接體。半導體晶片11b~11h係經由凸塊電極11p之連接體即凸塊電極13而使鄰接之半導體晶片11間電性連接，且在接著於第1基板20之半導體晶片11a上按序積層。
作為凸塊電極11p之形成材料，例舉有使用在Sn(錫)中添加Cu(銅)、Ag(銀)、Bi(鉍)、In(銦)等之Sn合金之焊錫材料、或Au(金)、Cu、Ni(鎳)、Sn、Pd(鈀)、Ag等之金屬材料。作為焊錫材料(無鉛焊錫)之具體例，例舉有Sn-Cu合金、Sn-Ag合金、Sn-Ag-Cu合金等。金屬材料並非限定於單層膜，亦可為Ni/Au或Ni/Pd/Au等之複數層金屬膜之積層膜。再者，金屬材料亦可為包含上述金屬之合金。作為焊墊電極與凸塊電極之組合，例舉有焊錫/焊錫、金屬/焊錫、焊錫/金屬、金屬/金屬等。作為焊墊電極11p與凸塊電極13之形狀，例舉有半球狀或柱狀等之突起形狀彼此之組合、及突起形狀與如焊墊般之平坦形狀之組合。
焊墊電極11p與凸塊電極13之至少一者較佳係以焊錫材料構成。再者，若考慮到製作晶片積層體10時之半導體晶片之操作性等，則較佳係於半導體晶片之上表面(電路面)形成使用Ni/Au或Ni/Pd/Au等之金屬材料之焊墊電極，且於半導體晶片之下表面(非電路面)形成使用Sn-Cu合金、Sn-Ag合金、Sn-Ag-Cu合金等之焊錫材料之焊墊電極11p及凸塊電極13之積層體。另，正反面之凸塊材料亦可相反。此情形時，較佳係將使用金屬材料之焊墊電極11p設計成平坦形狀，且將使用焊 錫材料之凸塊電極13設計成突起形狀。藉由保持具有平坦之焊墊電極11p之面，而提高半導體晶片之操作性，藉此可提高半導體晶片間之對位精度或凸塊電極13之連接性。
構成晶片積層體10之半導體晶片11a~11h之外形係採用相同之矩形狀。關於半導體晶片11a~11h之厚度，雖各自採用相同之厚度亦可，但較佳係使最下層之半導體晶片11a之厚度較其他半導體晶片11b~11h之厚度更厚。藉由加厚最下層之半導體晶片11a之厚度，可抑制因配線基板即第2基板30與半導體晶片之熱膨脹係數之差而產生之應力、半導體晶片之翹曲、及基於該等之半導體晶片間之連接不良(因凸塊電極引起之連接不良)。
除最下層之半導體晶片11a外之半導體晶片11b~11h，較佳係在減低晶片積層體10之厚度、進而減低積層型半導體裝置1之厚度後，進行薄厚度化加工者。具體而言，較佳係使用厚度50μm以下之半導體晶片11b~11h。若最下層之半導體晶片11a之厚度過厚，則晶片積層體10之厚度變厚，進而使積層型半導體裝置1之尺寸過大。半導體晶片11a之厚度較佳為300μm以下。由於最下層之半導體晶片11a無需貫通電極，故可容易地加厚晶片厚度。
於最上層之半導體晶片11h之表面，如圖1-3中主要部分放大圖所示，形成有重配線15。重配線15係以形成於最上層之半導體晶片11h表面之絕緣膜15a與配線層15b構成，且於與IF晶片18之連接位置及與第2基板20即配線基板之連接位置形成有電極焊墊17。半導體晶片11h表面係被覆蓋重配線15表面之保護膜16所覆蓋。
本實施形態中，雖已就在晶片積層體10上搭載有具備IF電路之IF晶片18之例加以說明，但搭載於晶片積層體10上之半導體晶片並未限定於僅搭載IF電路之IF晶片18。用以在晶片積層體10與外部元件之間進行資料通訊之IF晶片18，亦可為除IF電路外搭載有控制器電路者。 於晶片積層體10上，亦可搭載IF電路與控制器電路之混載晶片、即控制器兼IF晶片。又可搭載控制器與IF電路兩者之晶片。該等係基於積層型半導體裝置1之使用用途或外部元件之構成等而進行適當地選擇。
於構成晶片積層體10之半導體晶片間、進而最上層之半導體晶片11h與IF晶片18之間之間隙中，填充有密封樹脂(底膠填充)40。
在第1實施形態之積層型半導體裝置1中，係將IF電路設置於與半導體晶片不同之晶片(IF晶片18)，且將此晶片搭載於晶片積層體10上。因此，由於可使複數之半導體晶片11a~11h之外形形狀相同，故與例如於最下層之記憶體晶片搭載有IF電路之情形相比，可使積層有複數之半導體晶片11a~11h之晶片積層體10、進而使具備晶片積層體10之積層型半導體裝置1之封裝尺寸小型化。再者，因複數之半導體晶片11a~11h中，除最下層之半導體晶片11a不具有貫通電極12外，使用相同構造之半導體晶片，故可謀求開發效率之提高或製造成本之降低等。
晶片積層體10經由內部之電極焊墊17、內部連接端子33、及焊錫球34而與第2基板30電性連接。換言之，由於晶片積層體10係僅對於第2基板30之第2面31B而接著，故可降低晶片積層體10之安裝所需之成本。此外，因不必於最下層之半導體晶片11a形成貫通電極，故可容易地加厚最下層之半導體晶片11a之厚度。因此，在將晶片積層體10與第2基板30接著時，可抑制基於最下層之半導體晶片11a與構成第2基板30之樹脂基板31之熱膨脹差之應力之影響、或半導體晶片11a之翹曲。藉此，可提高半導體晶片間之電性連接可靠性，尤其可提高最下層之半導體晶片11a與第2層之半導體晶片11b之電性連接可靠性。
再者，在晶片積層體10與外部元件之間進行資料通訊之IF晶片18 係經由形成於最上層之半導體晶片11h上之重配線15與內部連接端子33，且藉由覆晶連接而與第2基板30電性連接。如此，由於簡化了IF晶片18與第2基板30之連接構造，故與在記憶體晶片內設置用以連接IF晶片18與第2基板30之貫通電極等之情形相比，可降低包含IF晶片18之晶片積層體10之製造工時或製造成本。即，可以低成本提供小型化且可靠性優良之半導體記憶裝置。此外，藉由簡化IF晶片18與第2基板30之連接構造，可謀求晶片積層體10與外部元件之資料通訊速度之提高等。
對比較例之半導體裝置進行說明。圖5係模式性顯示比較例之半導體裝置之構成之一例之剖面圖。在該例中，係於設有密封材料流出防止體之金屬製之搬送基板120上，依序積層晶片而形成晶片積層體210。接著，以樹脂140a密封晶片間。預先露出最上層之介面晶片之凸塊。其後，將單片之具備重配線之配線基板115連接於最上層晶片上。且，在以鑄模樹脂140b密封周邊後，切割鑄模樹脂140b。135係外部連接用之焊錫球。根據圖5與圖1-1之比較亦可知，根據本實施形態之積層型半導體裝置，其製造極其容易，且謀求大幅之小型化。
如上所示，根據上述構成而具有多種效果，尤其，因使用容易切斷之樹脂基板，而將第1及第2基板與密封樹脂一起統一切斷，故切斷面良好且呈現所謂之可小型化之極有效之效果。
(第2實施形態)
圖3係模式性顯示構成第2實施形態之半導體記憶裝置之積層型半導體裝置之構成之剖面圖。圖4-1~圖4-3係顯示相同積層型半導體裝置之製造步驟之步驟剖面圖。本實施形態之積層型半導體裝置2，係於切割步驟中進行單片分割前，即至圖2-6所示之步驟為止，與上述第1實施形態之積層型半導體裝置1相同而形成。接著，於單片分割前，對晶片積層體10側，以加入填料之環氧樹脂等之第2密封樹脂 40b，且使用模具(未圖示)進行成型、密封。其後，於配線基板即第2基板30之背面側搭載焊錫球35，其後藉由自第2基板30側使用刀片B2之刀片切割，而形成單片之封裝(半導體裝置)。
對第2實施形態之積層型半導體裝置之製造方法進行說明。在第1實施形態中，其特徵簡言之，係可統一進行晶片-晶片間及晶片-第2基板間之電極連接或樹脂密封。本實施形態中，圖2-1~圖2-6之步驟為止亦與第1實施形態相同，但不實施分割成圖2-7之單片之切割步驟，而是如圖4-1所示以第2密封樹脂40b進行樹脂密封。
其後，將焊錫球35搭載於第2基板(配線基板)30之背面側之外部連接端子32(圖4-2)。
接著，其後黏著於切割膠帶T2，且自第2基板30之背面側，藉由使用刀片B2之刀片切割(圖4-3)進行分割，而形成單片之封裝。
關於其他之構成係與上述第1實施形態之積層型半導體裝置1相同。該積層型半導體裝置2係包含：第1及第2基板20、30，該等係相對向而配置，且尺寸相同；複數層半導體晶片11a~11h之晶片積層體10，其被夾持於第1及第2基板20、30間，且至少與一者電性連接；及第1及第2密封樹脂40a、40b。該第1密封樹脂40a係將第1及第2基板間、構成積層體之半導體晶片間、及第1及第2基板與上述積層體間進行密封，且該第1及第2密封樹脂40a、40b之外緣位於連結第1及第2基板20、30之外緣之線上。
根據此方法，雖然步驟增加，且密封樹脂必須使用使液態樹脂硬化之第1密封樹脂40a、與成型之第2密封樹脂40b之2種，但具有可形成焊錫球35以作為外部連接端子之優點。又，如圖3所示，由於使用樹脂薄膜之第1基板20上被包含加入填料之鑄模樹脂之第2密封樹脂40b所被覆，故耐濕性提高。又，雖於包含樹脂薄膜之第1基板20表面存在無法雷射標記之問題，但由於表面被加入填料之鑄模樹脂所被 覆，因而可輕易地進行標記。
雖已說明本發明之多個實施形態，但該等實施形態係作為例示而加以提示者，並非意圖限定發明之範圍。該等新穎之實施形態可以其他各種形態予以實施，且在未脫離發明之主旨之範圍內，可進行各種省略、替換、及變更。該等實施形態或其變化係包含於發明之範圍或主旨，且包含於專利申請範圍所記載之發明及其均等之範圍內。
1‧‧‧積層型半導體裝置
10‧‧‧晶片積層體
11a~11h‧‧‧半導體晶片
12‧‧‧貫通電極
13‧‧‧焊墊電極
14‧‧‧接著劑
15‧‧‧重配線
16‧‧‧保護膜
17‧‧‧電極焊墊
18‧‧‧IF晶片
20‧‧‧第1基板
21‧‧‧樹脂薄膜
22‧‧‧接著劑
30‧‧‧第2基板
31‧‧‧樹脂基板
31A‧‧‧樹脂基板之第1面
31B‧‧‧樹脂基板之第2面
32‧‧‧外部連接端子
33‧‧‧內部連接端子
34‧‧‧焊錫球
40‧‧‧密封樹脂

Claims (6)

  1. 一種積層型半導體裝置之製造方法，其特徵在於包含：於使用樹脂基板之第1基板上，將第一層之半導體晶片複數排列於同一平面上且接著之步驟；藉由於上述半導體晶片正面或背面，介隔經圖案化成期望之圖案之感光性接著薄膜，分別進行至少一層以上之半導體晶片之對位、加熱，一面形成液態樹脂之滲透通道一面局部地接著，而於上述半導體晶片上分別積層至少一層以上之半導體晶片之步驟；將上述第1基板切斷而分離成各積層體之步驟；以形成於上述積層體之表面之電極焊墊部與第2基板之電極焊墊部一致之方式使其對位並對向而暫時連接之步驟；將上述第2基板及積層體整體回焊，而將電極焊墊部間電性連接之步驟；自上述積層體之上述第1基板側沿著上述積層體供給液態樹脂，而將各半導體晶片間及上述積層體與上述第2基板間樹脂密封之步驟；及將上述積層體以切割刀片切斷而單片化之步驟。
  2. 一種積層型半導體裝置之製造方法，其特徵在於包含：於第1基板上，將第一層之半導體晶片複數排列於同一平面上且接著之步驟；於上述半導體晶片上分別積層至少一層以上之半導體晶片之步驟；切斷上述第1基板而分離成各積層體之步驟；以形成於上述積層體之表面之電極焊墊部與第2基板之電極焊 墊部一致之方式使其對位並對向而暫時連接之步驟；將上述第2基板及積層體整體回焊，而將電極焊墊部間電性連接之步驟；自上述積層體之上述第1基板側沿著上述積層體供給液態樹脂，而將各半導體晶片間及上述積層體與上述第2基板間樹脂密封之步驟；及將經上述樹脂密封之積層體與上述第1基板及第2基板一起以切割刀片切斷而單片化之步驟。
  3. 如請求項2之積層型半導體裝置之製造方法，其中上述單片化之步驟係自上述第1基板側以切割刀片切斷之步驟。
  4. 如請求項2之積層型半導體裝置之製造方法，其係在進行上述單片化之步驟之前，包含供給含有填料之密封樹脂而將上述積層體之外側進行樹脂密封之後密封步驟；且上述單片化之步驟係自上述第2基板側以切割刀片切斷而單片化之步驟。
  5. 如請求項2至4中任一項之積層型半導體裝置之製造方法，其中上述第1基板中使用樹脂基板。
  6. 一種半導體裝置，其特徵在於：其係積層型半導體裝置，該積層型半導體裝置包含：第1及第2基板，該等係相對向而配置，且尺寸相同；複數層之半導體晶片之積層體，該等係被夾持於上述第1及第2基板間，且至少與一者電性連接；及密封樹脂，其係將上述第1及第2基板間、構成上述積層體之上述半導體晶片間、及上述第1及第2基板與上述積層體間密封；且上述密封樹脂之外緣位於連結上述第1及第2基板之外緣之線上。
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