CN104064486B - 半导体装置以及层叠型半导体装置的制造方法 - Google Patents

半导体装置以及层叠型半导体装置的制造方法 Download PDF

Info

Publication number
CN104064486B
CN104064486B CN201310361600.6A CN201310361600A CN104064486B CN 104064486 B CN104064486 B CN 104064486B CN 201310361600 A CN201310361600 A CN 201310361600A CN 104064486 B CN104064486 B CN 104064486B
Authority
CN
China
Prior art keywords
substrate
semiconductor chip
duplexer
resin
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310361600.6A
Other languages
English (en)
Other versions
CN104064486A (zh
Inventor
佐藤隆夫
福田昌利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japanese Businessman Panjaya Co ltd
Kioxia Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN104064486A publication Critical patent/CN104064486A/zh
Application granted granted Critical
Publication of CN104064486B publication Critical patent/CN104064486B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81054—Composition of the atmosphere
    • H01L2224/81065—Composition of the atmosphere being reducing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
    • H01L2224/81907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明提供切断面良好且安装容易并能够实现小型化的层叠型半导体装置及其制造方法。该方法特征是，包括：在第一基板上在同一平面上排列并粘接多个第一层的半导体芯片的工序；在所述半导体芯片上分别层叠至少一层以上的半导体芯片的工序；将所述第一基板切断而分离成各芯片层叠体的工序；进行对位以使在芯片层叠体的表面形成的电极焊盘部与第二基板的电极焊盘部互相对准，而对置地暂时连接的工序；将第二基板以及芯片层叠体整体回流焊以将电极焊盘部间电连接的工序；从芯片层叠体的第一基板侧沿层叠体供给液状树脂以对各半导体芯片间以及芯片层叠体与第二基板间进行树脂密封的工序；和从芯片层叠体的第二基板侧用切割刀片进行切断而个片化的工序。

Description

半导体装置以及层叠型半导体装置的制造方法
关联申请
本申请以日本专利申请2013-58303号（申请日：2013年3月21日）为基础并享受其优先权。本申请通过参照该在先申请而包括其全部内容。
技术领域
本发明的实施方式涉及半导体装置以及层叠型半导体装置的制造方法。
背景技术
在形成NAND型闪存等要求高容量的设备时，提出了将被薄厚加工了的半导体芯片多片层叠并进行树脂密封的方法、或者、将预先对半导体芯片进行了树脂密封所成的部件多个层叠的方法。各半导体芯片的信号提取，通常基于线接合法进行，但是为了使信号传输速度更高速化，提出了基于TSV方式（Through Silicon Via，硅穿孔）的层叠方式（例如日本专利公开公报2010-251408号）。就该层叠方式而言，在设有密封材料流出防止体的金属制运送基板上依次层叠芯片并将芯片之间用树脂密封。此时填充树脂使得最上层的接口芯片的凸起（バンプ，bump）露出。而且，在最上层的接口芯片的连接端子连接个片（单片）的布线基板。而且公开了在对周边进行了模铸密封后，将运送基板和模铸树脂统一切割（ダイシング，dicing）的技术。该方法是极为高效的安装方法。但是，不得不按密封材料流出防止体的量增大运送基板，所以封装大型化。而且，在通过刀具进行切断时，存在切断面的精加工不够这一问题。
发明内容
本发明的一个实施方式，其目的在于提供可小型化且切断面的精加工良好的半导体装置。
根据本发明的一个实施方式，其特征在于，包括：在采用树脂基板的第一基板上在同一平面上排列并粘接多个第一层的半导体芯片的工序；在所述半导体芯片表面或背面隔着图形化为所期望的图形的感光性粘接膜分别进行至少一层以上的半导体芯片的对位并加热，从而一边形成液状树脂的浸透通路一边局部粘接，在所述半导体芯片上分别层叠至少一层以上的半导体芯片的工序；将所述第一基板切断而分离成各层叠体的工序；进行对位以使在所述层叠体表面形成的电极焊盘部与第二基板的电极焊盘部互相对准，而对置地暂时连接的工序；将所述第二基板以及层叠体整体回流焊以将电极焊盘部间电连接的工序；从所述层叠体的所述第一基板侧沿所述层叠体供给液状树脂而对各半导体芯片间以及所述层叠体与所述第二基板间进行树脂密封的工序；和用切割刀片将所述层叠体切断而个片化的工序。
附图说明
图1-1是示意性地表示第一实施方式的半导体装置的剖视图。
图1-2是该半导体装置的要部放大剖视图。
图1-3是该半导体装置的要部放大剖视图。
图2-1是表示该半导体装置的制造工序的工序剖视图。
图2-2是表示该半导体装置的制造工序的工序剖视图。
图2-3是表示该半导体装置的制造工序的工序剖视图。
图2-4是表示该半导体装置的制造工序的工序剖视图。
图2-5是表示该半导体装置的制造工序的工序剖视图。
图2-6是表示该半导体装置的制造工序的工序剖视图。
图2-7是表示该半导体装置的制造工序的工序剖视图。
图2-8是表示该半导体装置的制造工序的工序剖视图。
图3是示意性地表示第二实施方式的半导体装置的结构的剖视图。
图4-1是表示该半导体装置的制造工序的工序剖视图。
图4-2是表示该半导体装置的制造工序的工序剖视图。
图4-3是表示该半导体装置的制造工序的工序剖视图。
图5是示意性地表示比较例的半导体装置的结构的一例的剖视图。
附图标记说明
1、2 层叠型半导体装置；10 芯片层叠体；11a～11h 半导体芯片；
12 贯穿电极；13 凸起电极；14 粘接剂；15 再布线；
16 保护薄膜；17 电极焊盘部；18 IF芯片；20 第一基板；
21 树脂膜；22 粘接剂；30 第二基板；31 树脂基板；
32 外部连接端子；33 内部连接端子；34、35 焊料球；
40 密封树脂；40a 第一密封树脂；40b 第二密封树脂。
具体实施方式
下面参照附图，详细地说明实施方式涉及的层叠型半导体装置及其制造方法。此外，本实施方式中，作为半导体芯片，就NAND型闪存等使用存储芯片的半导体存储装置进行说明，本发明不由这些实施方式限定。另外，在以下所示的附图中，为了容易理解，有时各部材的比例尺与实际不同。另外，在表示上下等方向时，示出图2中的附图标记为正方向的情况为基准的相对的方向，有时与以施加的重力加速度方向为基准的情况不同。
（第一实施方式）
图1-1是示意性地表示第一实施方式的半导体存储装置的剖视图，图1-2以及图1-3是该要部放大剖视图。从图2-1到图2-8是表示该半导体装置的制造工序的工序剖视图。本实施方式的半导体装置1具备：相对地配置的同一大小（尺寸）的第一以及第二基板20、30；在第一以及第二基板20、30之间、且电连接于至少一方的多层半导体芯片11a～11h的芯片层叠体10；和密封树脂40。该密封树脂40密封了第一以及第二基板20、30之间、构成芯片层叠体10的半导体芯片11a～11h之间、第一以及第二基板20、30与所述芯片层叠体10之间，该半导体装置1的特征在于，该密封树脂40的外缘位 于连结第一以及第二基板20、30的外缘的线上。
本实施方式中，作为第一基板20使用容易切断的树脂基板等，在第一基板20上层叠了半导体芯片11a～11h后，按每个第一基板20进行切断而形成芯片层叠体10。而且，将该芯片层叠体10连接到第二基板30（布线基板）上，并供给液状的密封树脂40、使其硬化。这样一来，将各半导体芯片11a～11h之间以及芯片层叠体10与所述第二基板30之间树脂密封，接着用切割刀具B1进行切断使其个片化，从而形成。
第二基板30具有树脂基板31，在该树脂基板31的第一面31Ａ形成有外部连接端子32。在作为BGA封装使用半导体存储装置的情况下，外部连接端子32包括焊料球、具有焊料镀敷、Au镀敷等的突起端子。在作为LGA封装使用半导体存储装置的情况下，作为外部连接端子32设有金属焊台（ランド）。在树脂基板31的第二面31B上设有内部连接端子33，经由焊料球34连接于芯片层叠体10的电极焊盘部17。内部连接端子33在与芯片层叠体10连接时作为连接部（连接块）发挥作用，经由第二基板30的布线网（未图示）与外部连接端子32电连接。在树脂基板31的第二面31B上固定有具有多个半导体芯片11（11a～11h）的芯片层叠体10。
接下来，关于本实施方式的半导体装置的制造方法进行说明。首先，作为第一基板20，准备将PI（聚酰亚胺）等有耐热性的树脂膜21贴附并保持于例如金属框架所得的基板，以能够运送。在此，将在树脂膜21上形成由热硬化性的粘接剂22所得的基板用作第一基板20。在该第一基板20上的预定位置粘接成为层叠体的第一层的半导体芯片11a。第一层半导体芯片11a在树脂膜21的一个平面上按预定间隔排列多个地搭载（图2-1）。实际上在树脂膜上形成有铜箔等的图形，以此为记号地搭载半导体芯片。该图形也能够在切割时使用。
此后，在各半导体芯片11a上依次层叠预定层数的半导体芯片（11b～11h）而形成各芯片层叠体10。此时半导体芯片11a～11h对位层叠，使得相互间的连接通过在（硅）贯穿电极12两面分别形成的焊盘电极11p与凸起电极13抵接来实现，形成了芯片层叠体10。接着，在层叠的半导体芯片11a ～11h的单面在电连接的焊盘电极(パッド電極)11p以外的场所以多点存在的方式形成有粘接剂14，在层叠半导体芯片11a～11h时，与对象侧的半导体芯片的对应的面粘接而固定(图2-2)。
接下来，在位于芯片层叠体10的最上层的存储芯片11h上，在表面上形成有再布线15，搭载接口芯片(IF芯片)18。再布线15如图1-3中要部放大剖视图所示，包括在最上层的半导体芯片11h的表面形成的绝缘薄膜15a和布线层15b，在与IF芯片18的连接位置以及与第二基板20即布线基板的连接位置形成有电极焊盘部17。该IF芯片18具备用于在构成芯片层叠体10的多个存储芯片即半导体芯片11a～11h与外部设备之间进行数据通信的接口(IF)电路。IF芯片18相对于芯片层叠体10进行倒装芯片连接(FC连接)，在与芯片层叠体10之间填充液状树脂并构成密封树脂40的一部分(图2-3)。
接着，在各层叠体的比芯片大的位置，将层叠体周边的树脂膜切断而形成单个的层叠体(图2-4)。切断的方法可以采用使用模具的方法、使用刀具(刃物)的方法、通过刀片切割进行的方法等任何方法。也可以预先准备在比芯片大的形状的位置设有狭槽等的形状，在该位置进行切断。
接下来，以单个的芯片层叠体10相对于布线基板即第二基板30能看到芯片侧的内部连接端子(电极焊盘部)33的朝向、即以芯片层叠体10的粘有第一基板(树脂膜)20的一侧变为远离第二基板30的一侧的方式，进行芯片层叠体10与第二基板30的对应的内部连接端子33的对位，接着通过预先涂敷的暂时固定材料进行暂时粘接。之后，通过在蚁酸环境气体(雰囲気)等还原环境气体中进行加热(回流焊(リフロー，reflow))，芯片层叠体10与第二基板30电连接(图2-5)。电极焊盘部17(内部连接端子33)以焊料和/或Au为主成分，同时进行层叠体的半导体芯片11a～11h相互间和芯片层叠体10的最上层的半导体芯片11h～第二基板30间的电连接。另外，芯片层叠体10的最上层的半导体芯片11h～第二基板30之间的电连接也可以另行进行。在此使用还原环境气体是因为：为了可靠地进行电连接而将在表面形成的氧化薄膜等还原并去除。层叠的各半导体芯片11a～11h之间，使用在与各电极焊盘部(内部连接端子33)相对应的位置形成有以Cu为主成分的贯穿电极12的结构。另外，根据需要，层叠的多个半导体芯片也能够应用于搭载大小不同的半导体芯片的结构。
接下来，统一地在芯片层叠体10的各半导体芯片11a～11h间和层叠体最上层的半导体芯片11h与第二基板30之间填充液状树脂并形成密封树脂40（图2-6）。
最后，粘接在切割带T1上，从芯片层叠体10的第一基板20（树脂膜）侧以基板上的识别标记为基准进行对位，通过使用刀片B1的刀片切割进行个片的封装化（图2-7）。此时在作为第一基板20的树脂膜的下侧存在将各半导体芯片11a～11h之间密封了的密封树脂40。而且，进行刀片切割时，事先粘接到切割带T1上免得杂乱，通过同时切断包括树脂膜的第一基板20、密封树脂40、第二基板30，能够最大限度地实现小型化并且得到切断面整齐的结构（图2-8）。而且，在向布线基板进行搭载时，用开口夹（コレット）（未图示）等从切割带T1上抓取成为个片的层叠型半导体装置1并收置于托盘等中。这样一来，图1-1所示的层叠型半导体装置1完成。
以上那样，能够从薄板即第一基板20之下涂敷液状树脂以进行半导体芯片11a～11h之间以及芯片层叠体10的最上层的半导体芯片11h～第二基板30（布线基板）间的密封。另外，此时在大小比半导体芯片大的第一基板20之下存在密封树脂40，所以能够在接近半导体芯片的位置进行刀片切割。因此，通过稳定的切断工序，能够制造接近芯片尺寸的封装。另外，能够如上述那样切断，没有必要再度对整体进行模铸密封，所以能够将树脂设为1种，提高制造生产率。另外，回流焊的工序也是一次即可，所以能够消减制造工序中的热应力，可靠性提高。即，能够实现封装的小型化、成本降低、工序合理化和可靠性的提升。密封树脂40是使液状树脂硬化所得的。而且，芯片层叠体部的凸起连接在向基板的暂时接之后，所以不会因将芯片层叠体搭载到基板上时的应力等而使凸起连接部破裂。
此外，第二基板30是例如在绝缘树脂基板的表面以及内部设有布线网（未图示）的基板，具体而言，适用采用了玻璃-环氧树脂和/或BT树脂（bismaleimide triazine resin，双马来酰亚胺三嗪树脂）等绝缘树脂的印刷 布线板（多层印刷基板等）。
用热硬化性的粘接剂22将最下层的半导体芯片11a的下面（非电路面）粘接于构成第一基板20的树脂膜21，从而将芯片层叠体10安装到第一基板20上。芯片层叠体10的层叠顺序中的最下层的半导体芯片11a仅通过包含绝缘性树脂等的粘接剂22粘接，不直接与第一基板20电连接。最下层的半导体芯片11a经由多个半导体芯片11b～11h与在第二基板30上设置的布线电连接。
芯片层叠体10经由在从第二层到最上层的半导体芯片11b～11h内部分别设置的贯穿电极（Through Silicon Via：TSV，硅穿孔）12和将这些贯穿电极12之间连接的凸起电极13，而将分别相邻的半导体芯片11a～11h间电连接。半导体芯片11b～11h，在粘接于第一基板20的存储芯片即半导体芯片11a上依次层叠。最下层的半导体芯片11a仅通过粘接剂22与第一基板20粘接，仅与第二层半导体芯片11b电连接。因此，最下层的半导体芯片11a没有贯穿电极。根据需要也能够在最下层的半导体芯片11a上形成贯穿电极并将该贯穿电极用于布线的引回。
以上那样，多个半导体芯片11a～11h经由在除了最下层的半导体芯片11a外的半导体芯片11b～11h设置的贯穿电极12和凸起电极13而电连接。图1-1中简化示出相邻的半导体芯片间的电连接结构。具体而言，通过使在下层侧的半导体芯片的上面（电路面）以与贯穿电极12电连接的方式形成的焊盘电极11p与在上层侧的半导体芯片的下面（非电路面）以与贯穿电极12电连接的方式形成的凸起电极13接触、并将至少一方的电极端子熔融而一体化，从而将相邻的半导体芯片11a～11h间电连接。凸起电极13在图1-1中作为与焊盘电极11p的连接体示出，使得在图1-2中示出要部放大图。半导体芯片11b～11h，一边经由焊盘电极11p的连接体即凸起电极13将相邻的半导体芯片11间电连接，一边在粘接在第一基板20上的半导体芯片11a上依次层叠。
作为焊盘电极11p的形成材料，可以举出使用在Sn中添加有Cu、Ag、Bi、In等的Sn合金的焊料和/或Au、Cu、Ni、Sn、Pd、Ag等金属材料。作 为焊料（无Pb焊料（Pbフリー半田））的具体例子，可以举出Sn-Cu合金、Sn-Ag合金、Sn-Ag-Cu合金等。金属材料不限于单层薄膜，也可以是Ni／Au和/或Ni／Pd／Au等的多个金属薄膜的层叠薄膜。而且，金属材料也可以是含上述那样的金属的合金。作为焊盘电极与凸起电极的组合，可以举出焊料／焊料、金属／焊料、焊料／金属、金属／金属等。作为焊盘电极11p与凸起电极13的形状，可以举出半球状和/或柱状等突起形状彼此的组合、突起形状与焊盘那样的平坦形状的组合。
焊盘电极11p与凸起电极13的至少一方，优选，由焊料制成。而且，如果考虑制造芯片层叠体10时的半导体芯片的操作（ハンドリング）性等，则优选，在半导体芯片的上面（电路面）形成采用了Ni／AuやNi／Pd／Au等金属材料的焊盘电极，并在半导体芯片的下面（非电路面）形成采用了Sn-Cu合金、Sn-Ag合金、Sn-Ag-Cu合金等焊料的焊盘电极11p以及凸起电极13的层叠体。此外，表面背面的凸起材料相反也没有问题。此时，优选，采用了金属材料的焊盘电极11p成为平坦形状，采用了焊料的凸起电极13成为突起形状。通过保持具有平坦的焊盘电极11p的面，半导体芯片的操作性提高，由此能够提高半导体芯片间的对位精度和/或凸起电极13的连接性。
构成芯片层叠体10的半导体芯片11a～11h的外形为相同的矩形状。关于半导体芯片11a～11h的厚度，可以分别设为相同的厚度，但优选，使最下层的半导体芯片11a的厚度比其他半导体芯片11b～11h的厚度厚。通过使最下层的半导体芯片11a的厚度变厚，能够抑制由于布线基板即第二基板30与半导体芯片的热膨胀系数的差而产生的应力、半导体芯片的翻翘（弯曲）、基于这些的半导体芯片间的连接不良（凸起电极的连接不良）。
除最下层的半导体芯片11a外的半导体芯片11b～11h，为了降低芯片层叠体10的厚度乃至层叠型半导体装置1的厚度，优选为薄厚化加工了的芯片。具体而言，优选，使用厚度50μm以下的半导体芯片11b～11h。如果最下层的半导体芯片11a的厚度过厚，则芯片层叠体10的厚度变厚，进而层叠型半导体装置1的大小变得过大。优选，半导体芯片11a的厚度设为300μm 以下。最下层的半导体存储芯片11a不需要贯穿电极，所以能够容易地增厚芯片厚。
在最上层的半导体芯片11h的表面形成有再布线15，使得图1-3中示出要部方式图。再布线15包括在最上层的半导体芯片11h表面形成的绝缘薄膜15a和布线层15b，在与IF芯片18的连接位置以及与第二基板20即布线基板的连接位置形成有电极焊盘部17。半导体芯片11h表面被保护薄膜16覆盖，该保护薄膜覆盖再布线15表面。
本实施方式中关于在芯片层叠体10上搭载具有IF电路的IF芯片18的例子进行了说明，但在芯片层叠体10上搭载的半导体芯片不限定于仅担载了IF电路的IF芯片18。用于在芯片层叠体10与外部设备之间进行数据通信的IF芯片18，也可以是除IF电路外还搭载有控制电路。在芯片层叠体10上也可以搭载IF电路与控制电路的混载芯片、即控制兼IF芯片。另外，也可以搭载控制器和IF电路这两个芯片。这些基于层叠型半导体装置1的使用用途和外部设备的结构等适当地选择。
在构成芯片层叠体10的半导体芯片间、而且在最上层的半导体芯片11h与IF芯片18之间的间隙中，填充有密封树脂（底部填充）40。
第一实施方式的层叠型半导体装置1中，在与半导体芯片不同的其他芯片（IF芯片18）上设置IF电路，该芯片搭载在芯片层叠体10上。因此，能够使多个半导体芯片11a～11h的外形形状相同，所以与例如在最下层的存储芯片上搭载了IF电路的情况相比较，能够使层叠了多个半导体芯片11a～11h而成的芯片层叠体10、乃至具备芯片层叠体10的层叠型半导体装置1的封装尺寸小型化。进而，多个半导体芯片11a～11h中，除最下层的半导体芯片11a没有贯穿电极12外，使用相同结构的半导体芯片，所以能够实现开发效率的提高和/或制造成本的降低等。
芯片层叠体10经由内部的电极焊盘部17、内部连接端子33、焊料球34与第二基板30电连接。如果换言之，则芯片层叠体10仅相对于第二基板30的第二面31B粘接，所以能够降低芯片层叠体10的安装所需的成本。而且，不需要在最下层的半导体芯片11a上形成贯穿电极，所以能够容易地使最下 层的半导体芯片11a的厚度变厚。因此，在将芯片层叠体10粘接于第二基板30时，抑制基于最下层的半导体芯片11a和构成第二基板30的树脂基板31的热膨胀差的应力的影响和半导体芯片11a的翻翘。由于这些，能够提高半导体芯片间的电连接可靠性、特别是能够提高最下层的半导体芯片11a与第二层半导体芯片11b的电连接可靠性。
而且，在芯片层叠体10与外部设备之间进行数据通信的IF芯片18，经由在最上层的半导体芯片11h上形成的再布线15和内部连接端子33与第二基板30通过倒装芯片连接而电连接。这样，IF芯片18与第二基板30的连接结构简化，因此与在存储芯片内设置用于连接IF芯片18和第二基板30的贯穿电极等的情况相比，能够降低包括IF芯片18的芯片层叠体10的制造工时和制造成本。即，能够以低成本提供小型且可靠性优异的半导体存储装置。而且，通过使IF芯片18与第二基板30的连接结构简化，能够实现芯片层叠体10与外部设备的数据通信速度的提高等。
关于比较例的半导体装置进行说明。图5是示意性地表示比较例的半导体装置的结构的一例的剖视图。该例子中，在设有密封材料流出防止体的金属制的运送基板120上按顺序层叠芯片而形成了芯片层叠体210。而且，通过树脂140ａ将芯片间密封。最上层的接口芯片的凸起预先露出。此后，在最上层芯片上连接个片的具备再布线的布线基板115。而且在通过模铸树脂140b将周边密封了后，切割模铸树脂140b。标记135是外部连接用的焊料球。从图5与图1-1的比较，也可以根据本实施方式的层叠型半导体装置，制造变得极为容易，能够大幅实现小型化。
以上那样，根据上述结构具有众多效果，特别是用容易切断的树脂基板并将第一以及第二基板与密封树脂一并统一地切断，所以呈现切断面良好且能够小型化则样的极为有效的效果。
（第二实施方式）
图3是示意性地表示构成第二实施方式的半导体存储装置的、层叠型半导体装置的结构的剖视图。图4-1～图4-3是表示该层叠型半导体装置的制造工序的工序剖视图。本实施方式的层叠型半导体装置2，在即将通过切割 工序进行个片分割前即直到图2-6所示的工序，与所述第一实施方式的层叠型半导体装置1同样地形成。而且，在个片分割前，通过含填充剂（填料）的环氧树脂等第二密封树脂40b用模具（未图示）在芯片层叠体10侧进行成型并密封。此后，在布线基板即第二基板30的背面侧搭载焊料球35，此后从第二基板30侧通过采用刀片B2的刀片切割，形成个片的封装（半导体装置）。
关于第二实施方式的层叠型半导体装置的制造方法进行说明。第一实施方式中，最为简略而言，其特征在于，能够统一地进行芯片-芯片间以及芯片-第二基板间的电极连接和树脂密封。本实施方式中，到图2-1～图2-6的工序为止，也与第一实施方式相同，但是不实施图2-7的分割成个片的切割工序，而是如图4-1所示通过第二密封树脂40b进行树脂密封。
此后，在第二基板（布线基板）30的背面侧的外部连接端子32搭载焊料球35（图4-2）。
而且，此后粘接于切割带Ｔ2并从第二基板30的背面侧通过采用刀片B2的刀片切割（图4-3）进行分割，形成个片的封装。
关于其他结构与所述第一实施方式的层叠型半导体装置1相同。该层叠型半导体装置2包括：对置配置且大小相同的第一以及第二基板20、30；夹持在第一以及第二基板20、30之间且电连接于至少一方的多层半导体芯片11a～11h的芯片层叠体10；和第一以及第二密封树脂40a、40b。该第一密封树脂40a将第一与第二基板之间、构成层叠体的半导体芯片之间、第一以及第二基板与所述层叠体之间密封起来，该第一以及第二密封树脂40a、40b的外缘处于连结第一以及第二基板20、30的外缘的线上。
根据该方法，如果工序增加，则密封树脂需要使液状树脂硬化而成的第一密封树脂40a和成型所得的第二密封树脂40b这两种，但具有作为外部连接端子能够形成焊料球35这一优点。另外，如图3所示，用了树脂膜的第一基板20上由包括含填充剂模铸树脂的第二密封树脂40b覆盖，所以耐湿性提高。另外，包含树脂膜的第一基板20表面，存在无法进行激光打标（marking）这样的问题，然而由于表面由含填充剂的模铸树脂覆盖，所 以能够容易地进行打标。
以上说明了与本发明相关的实施方式，但是该实施方式是作为例子提出的，无意于限定发明的范围。该实施方式能够以其他各种各样的形态来实施，能够在不脱离发明的主旨的范围内进行各种省略、置换、变更。该实施方式等包含于发明的范围和/或主旨，同样地也包含在技术方案所记载的发明及其等同范围。

Claims (6)

1.一种层叠型半导体装置的制造方法，其特征在于，包括：
在采用树脂基板的第一基板上在同一平面上排列并粘接多个第一层的半导体芯片的工序；
在所述半导体芯片表面或背面隔着图形化为所期望的图形的感光性粘接膜分别进行至少一层以上的半导体芯片的对位并加热，从而一边形成液状树脂的浸透通路一边局部粘接，在所述半导体芯片上分别层叠至少一层以上的半导体芯片的工序；
将所述第一基板切断而分离成各层叠体的工序；
进行对位以使在所述层叠体表面形成的电极焊盘部与第二基板的电极焊盘部互相对准，而对置地暂时连接的工序；
将所述第二基板及层叠体整体回流焊以将电极焊盘部间电连接的工序；
从所述层叠体的所述第一基板侧沿所述层叠体供给液状树脂而对各半导体芯片间以及所述层叠体与所述第二基板间进行树脂密封的工序；和
用切割刀片将所述层叠体切断而个片化的工序。
2.一种层叠型半导体装置的制造方法，其特征在于，包括：
在第一基板上在同一平面上排列并粘接多个第一层的半导体芯片的工序；
在所述半导体芯片上分别层叠至少一层以上的半导体芯片的工序；
将所述第一基板切断而分离成各层叠体的工序；
进行对位以使在所述层叠体表面形成的电极焊盘部与第二基板的电极焊盘部互相对准，而对置地暂时连接的工序；
将所述第二基板以及层叠体整体回流焊以将电极焊盘部间电连接的工序；
从所述层叠体的所述第一基板侧沿所述层叠体供给液状树脂而对各半导体芯片间以及所述层叠体与所述第二基板间进行树脂密封的工序；和
用切割刀片将所述树脂密封了的层叠体与所述第一基板以及第二基板一并切断而个片化的工序。
3.根据权利要求2所述的层叠型半导体装置的制造方法，其特征在于，所述个片化工序是从所述第一基板侧用切割刀片进行切断的工序。
4.根据权利要求2所述的层叠型半导体装置的制造方法，其特征在于，在所述个片化工序之前，
包括供给含有填充剂的密封树脂以对所述层叠体的外侧进行树脂密封的后密封工序，
所述个片化工序是从所述第二基板侧用切割刀片进行切断而个片化的工序。
5.根据权利要求2到4中任一项所述的层叠型半导体装置的制造方法，其特征在于，
所述第一基板采用树脂基板。
6.一种半导体装置，包括：
第一以及第二基板，其对置配置且为同一尺寸；
多层半导体芯片的层叠体，其被夹持在所述第一与第二基板间且电连接于至少一方；和
密封树脂，其将所述第一与第二基板间、构成所述层叠体的所述半导体芯片间、所述第一以及第二基板与所述层叠体间密封，
该半导体装置的特征在于，
所述密封树脂的外缘处于连结所述第一以及第二基板的外缘的线上。
CN201310361600.6A 2013-03-21 2013-08-19 半导体装置以及层叠型半导体装置的制造方法 Active CN104064486B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013058303A JP5847749B2 (ja) 2013-03-21 2013-03-21 積層型半導体装置の製造方法
JP058303/2013 2013-03-21

Publications (2)

Publication Number Publication Date
CN104064486A CN104064486A (zh) 2014-09-24
CN104064486B true CN104064486B (zh) 2017-01-18

Family

ID=51552144

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310361600.6A Active CN104064486B (zh) 2013-03-21 2013-08-19 半导体装置以及层叠型半导体装置的制造方法

Country Status (4)

Country Link
US (1) US9099459B2 (zh)
JP (1) JP5847749B2 (zh)
CN (1) CN104064486B (zh)
TW (1) TWI545723B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015053406A (ja) * 2013-09-09 2015-03-19 株式会社東芝 半導体装置
JP2015173144A (ja) * 2014-03-11 2015-10-01 株式会社東芝 配線基板とそれを用いた半導体装置
JP2015177062A (ja) 2014-03-14 2015-10-05 株式会社東芝 半導体装置の製造方法および半導体装置
JP6495692B2 (ja) 2015-03-11 2019-04-03 東芝メモリ株式会社 半導体装置及びその製造方法
JP6479577B2 (ja) 2015-05-29 2019-03-06 東芝メモリ株式会社 半導体装置
US9373605B1 (en) * 2015-07-16 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. DIE packages and methods of manufacture thereof
JP6515047B2 (ja) * 2016-03-11 2019-05-15 東芝メモリ株式会社 半導体装置及びその製造方法
JP6523999B2 (ja) * 2016-03-14 2019-06-05 東芝メモリ株式会社 半導体装置およびその製造方法
JP6753743B2 (ja) 2016-09-09 2020-09-09 キオクシア株式会社 半導体装置の製造方法
JP6680712B2 (ja) * 2017-03-10 2020-04-15 キオクシア株式会社 半導体装置
TWI649839B (zh) * 2017-03-15 2019-02-01 矽品精密工業股份有限公司 電子封裝件及其基板構造
JP6649308B2 (ja) * 2017-03-22 2020-02-19 キオクシア株式会社 半導体装置およびその製造方法
JP7304335B2 (ja) 2017-08-21 2023-07-06 長江存儲科技有限責任公司 Ｎａｎｄメモリデバイスおよびｎａｎｄメモリデバイスを形成するための方法
JP6892360B2 (ja) 2017-09-19 2021-06-23 キオクシア株式会社 半導体装置
JP6989426B2 (ja) * 2018-03-22 2022-01-05 キオクシア株式会社 半導体装置およびその製造方法
US11004477B2 (en) * 2018-07-31 2021-05-11 Micron Technology, Inc. Bank and channel structure of stacked semiconductor device
US11495565B2 (en) * 2018-11-21 2022-11-08 Tohoku-Microtec Co., Ltd. Stacked semiconductor device and multiple chips used therein
JP6689420B2 (ja) * 2019-01-17 2020-04-28 キオクシア株式会社 半導体装置および半導体装置の製造方法
US11069661B1 (en) * 2020-06-23 2021-07-20 Siliconware Precision Industries Co., Ltd. Electronic package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6235554B1 (en) * 1995-11-27 2001-05-22 Micron Technology, Inc. Method for fabricating stackable chip scale semiconductor package
US6271056B1 (en) * 1998-06-05 2001-08-07 Micron Technology, Inc. Stacked semiconductor package and method of fabrication
TW200913218A (en) * 2007-05-22 2009-03-16 United Test & Assembly Ct Lt Method of assembling a silicon stacked semiconductor package

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030183943A1 (en) * 2002-03-28 2003-10-02 Swan Johanna M. Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
JP4191167B2 (ja) * 2005-05-16 2008-12-03 エルピーダメモリ株式会社 メモリモジュールの製造方法
JP4553813B2 (ja) * 2005-08-29 2010-09-29 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
EP1997138B1 (en) * 2006-03-21 2011-09-14 Promerus LLC Methods and materials useful for chip stacking, chip and wafer bonding
US20080023805A1 (en) * 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
US8647924B2 (en) * 2009-04-13 2014-02-11 United Test And Assembly Center Ltd. Semiconductor package and method of packaging semiconductor devices
JP5579402B2 (ja) 2009-04-13 2014-08-27 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法並びに電子装置
KR101195462B1 (ko) * 2010-09-27 2012-10-30 에스케이하이닉스 주식회사 반도체 패키지 및 이의 제조방법
JP2012146853A (ja) * 2011-01-13 2012-08-02 Elpida Memory Inc 半導体装置の製造方法
JP2012231096A (ja) * 2011-04-27 2012-11-22 Elpida Memory Inc 半導体装置及びその製造方法
US8710654B2 (en) * 2011-05-26 2014-04-29 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6235554B1 (en) * 1995-11-27 2001-05-22 Micron Technology, Inc. Method for fabricating stackable chip scale semiconductor package
US6271056B1 (en) * 1998-06-05 2001-08-07 Micron Technology, Inc. Stacked semiconductor package and method of fabrication
TW200913218A (en) * 2007-05-22 2009-03-16 United Test & Assembly Ct Lt Method of assembling a silicon stacked semiconductor package

Also Published As

Publication number Publication date
JP5847749B2 (ja) 2016-01-27
JP2014183278A (ja) 2014-09-29
US9099459B2 (en) 2015-08-04
CN104064486A (zh) 2014-09-24
TW201438185A (zh) 2014-10-01
US20140284817A1 (en) 2014-09-25
TWI545723B (zh) 2016-08-11

Similar Documents

Publication Publication Date Title
CN104064486B (zh) 半导体装置以及层叠型半导体装置的制造方法
US8575763B2 (en) Semiconductor device and method of manufacturing the same
CN105374693B (zh) 半导体封装件及其形成方法
CN102067310B (zh) 带有边缘触头的晶片级芯片规模封装的堆叠及其制造方法
TWI529851B (zh) Manufacturing method of semiconductor device
US8829686B2 (en) Package-on-package assembly including adhesive containment element
US9177936B2 (en) Method of manufacturing semiconductor device
US9230942B2 (en) Semiconductor device including alternating stepped semiconductor die stacks
KR101190920B1 (ko) 적층 반도체 패키지 및 그 제조 방법
CN103022021A (zh) 半导体装置及其制造方法
US10903200B2 (en) Semiconductor device manufacturing method
CN104051395A (zh) 芯片堆叠封装及其方法
CN102136434A (zh) 在引线键合的芯片上叠置倒装芯片的方法
CN103633076A (zh) 包封件上芯片型封装件
CN102110672B (zh) 芯片堆叠封装结构及其制造方法
KR20160135688A (ko) 박형 샌드위치 임베디드 패키지
CN103594447A (zh) 封装密度大高频性能好的ic芯片堆叠封装件及制造方法
CN109801883A (zh) 一种扇出型堆叠封装方法及结构
US20120264257A1 (en) Mold array process method to prevent exposure of substrate peripheries
CN108630626A (zh) 无基板封装结构
CN110993517A (zh) 一种芯片堆叠封装方法及封装结构
CN110634856A (zh) 一种倒装加打线混合型封装结构及其封装方法
JP2015222837A (ja) 半導体装置
CN110299328A (zh) 一种堆叠封装器件及其封装方法
CN106920789A (zh) 一种半导体堆叠封装结构及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170803

Address after: Tokyo, Japan

Patentee after: TOSHIBA MEMORY Corp.

Address before: Tokyo, Japan

Patentee before: Toshiba Corp.

CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Tokyo, Japan

Patentee after: Kaixia Co.,Ltd.

Address before: Tokyo, Japan

Patentee before: TOSHIBA MEMORY Corp.

Address after: Tokyo, Japan

Patentee after: TOSHIBA MEMORY Corp.

Address before: Tokyo, Japan

Patentee before: Japanese businessman Panjaya Co.,Ltd.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20220110

Address after: Tokyo, Japan

Patentee after: Japanese businessman Panjaya Co.,Ltd.

Address before: Tokyo, Japan

Patentee before: TOSHIBA MEMORY Corp.