CN106920789A - 一种半导体堆叠封装结构及其制造方法 - Google Patents

一种半导体堆叠封装结构及其制造方法 Download PDF

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CN106920789A
CN106920789A CN201710192547.XA CN201710192547A CN106920789A CN 106920789 A CN106920789 A CN 106920789A CN 201710192547 A CN201710192547 A CN 201710192547A CN 106920789 A CN106920789 A CN 106920789A
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chip
encapsulating structure
semiconductor stack
substrate
stack encapsulating
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陈峥嵘
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Abstract

本发明提供了一种半导体堆叠封装结构及其制造方法。所述半导体堆叠封装结构包括：基板；第二芯片，表面形成有多个焊料凸起；以及第一芯片，位于所述第二芯片上方，其中，所述第二芯片以倒装的方式通过所述多个焊料凸起与所述基板连接，所述第一芯片通过焊线与所述第二芯片连接。根据本发明的示例性实施例的半导体堆叠封装结构及其制造方法能够确保半导体堆叠封装结构中的每个芯片均为良好的芯片，可以减小封装结构的尺寸，可以改善半导体堆叠封装结构的散热性，并且可以提高信号传输的效率。

Description

一种半导体堆叠封装结构及其制造方法
本申请是申请日为2015年7月31日、申请号为201510464260.9、题为“一种半导体堆叠封装结构及其制造方法”的专利申请的分案申请。
技术领域
本发明属于半导体封装领域，具体地讲，涉及一种具有倒装芯片(flip chip)和芯片到芯片(chip to chip)的引线键合(wire bonding)的半导体堆叠封装结构及其制造方法。
背景技术
现有的对诸如逻辑芯片和存储芯片等的多个芯片的一体封装通常采用层叠封装(POP，package on package)技术。通常，层叠封装技术包括多个芯片借助于各自的封装件以相互堆叠，其中，逻辑芯片和存储芯片等分别通过焊线或倒装芯片的焊点与对应的基板连接，再将各基板彼此连接。
层叠封装技术的成本低廉，但是封装结构具有额外的基板，多个芯片之间的通信路径长，整个封装结构的体积难以大幅缩小，散热、信号速率方面受到限制。
另一种多个芯片的封装技术是通过硅通孔技术实现多个芯片的彼此连接的3D封装技术。在该3D封装技术中，多个芯片通过硅通孔技术彼此连接，然后可通过焊点或焊线来实现芯片与基板的连接。
传统的3D封装技术具有信号速率高、功耗低和散热好的优点。但是，硅通孔技术难以实现芯片测量，无法确保封装采用的芯片均为具有良好的电路功能的芯片，因此导致最终良率低。为了实现硅通孔技术，芯片的通孔区域无法设计电路，而需要绕开通孔区域，耗费了芯片的面积。另外，传统的3D封装技术因价格昂贵且良率受限而仍然无法实现大规模的商业应用。
发明内容
本发明的一个或多个方面提供了一种半导体堆叠封装结构及其制造方法，所述半导体堆叠封装结构能够确保每个芯片的质量并减小半导体堆叠封装结构的尺寸。
根据本发明的一方面，提供了一种半导体堆叠封装结构，所述半导体堆叠封装结构包括：基板；第二芯片，表面形成有多个焊料凸起；第一芯片，位于所述第二芯片上方，其中，所述第二芯片以倒装的方式通过所述多个焊料凸起与所述基板连接，所述第一芯片通过焊线与所述第二芯片连接。
所述焊线可以与所述基板分隔开。
所述第二芯片可以为具有高速信号需求的芯片。优选地，所述第二芯片可以为逻辑芯片，所述第一芯片可以为存储芯片。
所述半导体堆叠封装结构还可以包括用于保护所述第一芯片、所述第二芯片和所述基板的塑封体。
所述半导体堆叠封装结构还可以包括设置于所述基板的下端的焊球。
所述半导体堆叠封装结构还可以包括位于所述第二芯片上的至少一个芯片，不同的芯片之间通过焊线彼此连接。
根据本发明的另一方面，提供了一种制造半导体堆叠封装结构的方法，所述方法包括：在载板上形成第一芯片；在所述第一芯片上形成第二芯片，所述第二芯片的上表面形成有多个焊料凸起；通过焊线连接所述第一芯片和所述第二芯片；以倒装的方式通过所述多个焊料凸起将所述第二芯片和所述基板彼此连接；去除所述载板。
在去除所述载板之后，可以对所述第一芯片、所述第二芯片和所述基板进行模封以形成塑封体，可以在所述基板的下端形成焊球。
根据本发明的另一方面，提供了一种制造半导体堆叠封装结构的方法，所述方法包括：在载板上形成至少一个芯片；在所述至少一个芯片上形成倒装芯片，所述倒装芯片的上表面形成有多个焊料凸起；通过焊线使不同的芯片彼此连接；以倒装的方式通过所述多个焊料凸起将所述倒装芯片和所述基板彼此连接；去除所述载板。
根据本发明的示例性实施例的半导体堆叠封装结构及其制造方法能够确保半导体堆叠封装结构中的每个芯片均为良好的芯片，可以减小封装结构的尺寸，可以改善半导体堆叠封装结构的散热性，并且可以提高信号传输的效率。另外，不需要对逻辑芯片进行重新设计或额外地占用逻辑芯片的面积，从而可以降低成本。
附图说明
通过参照附图详细描述示例性实施例，特征对于本领域技术人员来讲将变得明显，在附图中：
图1是示出根据本发明的示例性实施例的半导体堆叠封装结构的剖视图；
图2至图8是用于描述根据本发明的示例性实施例的制造半导体堆叠封装结构的方法的剖视图；
图9是示出根据本发明的另一示例性实施例的半导体堆叠封装结构的剖视图；
图10是示出根据本发明的另一示例性实施例的半导体堆叠封装结构的剖视图。
具体实施方式
以下，参照附图来详细说明本发明的示例性实施例。然而，本发明可以以许多不同的方式来实施，而不应被理解为限于下面的实施例。在附图中，为了清晰起见，夸大尺寸进行表示，并且不同的附图中使用相同的附图标记表示相同的部件。
图1是示出根据本发明的示例性实施例的半导体堆叠封装结构1的剖视图。
参照图1，根据本发明的示例性实施例的半导体堆叠封装结构1包括：基板10；第二芯片12，表面形成有多个焊料凸起14；第一芯片11，位于第二芯片12上方，其中，第二芯片12以倒装的方式通过多个焊料凸起14与基板10连接，第一芯片11通过焊线15与第二芯片12连接。
基板10可以包括印刷电路板、硅基板、蓝宝石基板等，但是本发明不限于此。在本发明的教导下，本领域技术人员可以选用由合适的材料制成的基板。
根据示例性实施例，第二芯片12可以为具有高速信号需求的芯片。例如，第二芯片12可以为具有高速信号需求和较多输入引脚、输出引脚需求的逻辑芯片(logic chip)。多个焊料凸起14可以形成在第二芯片12的下表面上。根据示例性实施例，第一芯片11可以为存储芯片(memory chip)。虽然在图1中未示出，但第一芯片11可以通过诸如热固性粘结剂、热塑性粘结剂、芯片粘结薄膜、导电银浆等的粘结剂附着到第二芯片12上。可以通过与形成倒装芯片的焊点的工艺相同或基本相同的工艺来形成多个焊料凸起14，多个焊料凸起14可以包括焊料成分、铜柱、金凸块等。
根据示例性实施例，第二芯片12可以作为倒装芯片，以通过多个焊料凸起14与基板10连接。在第二芯片12为逻辑芯片的情况下，具有较多输入引脚、输出引脚的逻辑芯片可以以倒装的方式与基板10连接。由于不需要制作硅通孔，因此不需要对逻辑芯片进行重新设计或额外地占用逻辑芯片的面积。根据示例性实施例，第一芯片11可以比第二芯片12大，即，如图1所示，第一芯片11的宽度可以大于第二芯片12的宽度，第一芯片11的在水平方向上的面积可以大于第二芯片12的在水平方向上的面积，但是本发明不限于此。第一芯片11不必须比第二芯片12大，只要当粘结它们时将需要形成互联的焊盘暴露在外以能够实现焊线连接即可。
第一芯片11和第二芯片12通过它们之间的焊线15彼此连接，从而实现不同芯片之间的通信。如图1所示，焊线15可以与基板10分隔开，即，焊线15不与基板10电互联。
根据示例性实施例，半导体堆叠封装结构1还可以包括用于保护第一芯片11、第二芯片12和基板10等的塑封体16。可以通过对芯片和基板进行模封(molding)来形成塑封体16。
根据示例性实施例，半导体堆叠封装结构1还可以包括设置于基板10的下端的焊球17。例如，可以通过值球工艺在基板10的下端形成多个焊球17，使得芯片可以与其他电路连接。
根据本发明的示例性实施例，各种类型的芯片之间通过焊线进行互联，能够实现信号的相互传递，而且具有高速信号要求的第二芯片通过其焊料凸起与基板进行互联，能够实现信号的快速传递，而不会对信号造成延误。
根据本发明的示例性实施例，通过芯片到芯片的引线键合来实现不同芯片之间的连接，并且仅作为倒装芯片的芯片通过倒装的方式与基板连接，从而可以确保半导体堆叠封装结构中的每个芯片均为良好的芯片。与传统的层叠封装技术相比，半导体堆叠封装结构仅包含一个基板，从而可以减小封装结构的尺寸；多个芯片通过焊线彼此连接，从而不需要例如空气层的其他中间介质层，以改善半导体堆叠封装结构的散热性；由于通过焊线实现芯片之间的连接，因此信号通过的界面减少，从而提高信号传输的效率。与传统的3D封装技术相比，不需要对逻辑芯片进行重新设计或额外地占用逻辑芯片的面积，从而降低成本。
在下文中，结合图2至图8详细说明根据本发明的示例性实施例的制造图1中示出的半导体堆叠封装结构1的方法。
图2至图8是用于描述根据本发明的示例性实施例的制造半导体堆叠封装结构1的方法的剖视图。
参照图2，在载板18上形成第一芯片11。虽然在图2中未示出，但可以通过在载板18的上表面上涂敷可剥离的粘结剂使第一芯片11附着到载板18上。可剥离的粘结剂的示例可以包括光敏材料(例如，可通过紫外光照射降低粘性的薄膜材料)、热熔胶等。作为示例，第一芯片11可以为存储芯片。载板18可以由玻璃板、导热金属板等形成，但是本发明不限于此。载板18的选择与粘结剂的选择相关，例如，玻璃载板可以配合UV敏感材料使用。
参照图3，在第一芯片11上形成第二芯片12，第二芯片12的上表面形成有多个焊料凸起14。可以通过在第一芯片11的上表面上涂敷诸如热固性粘结剂、热塑性粘结剂、芯片粘结薄膜、导电银浆等的粘结剂(未示出)将第二芯片12附着到第一芯片11上。作为示例，第二芯片12可以为具有高速信号需求的芯片。例如，第二芯片12可以为具有高速信号需求和较多输入引脚、输出引脚需求的逻辑芯片。
参照图4，通过焊线15连接第一芯片11和第二芯片12。如图4所示，焊线15的弧线的最高点的高度可以低于第二芯片12上的多个焊料凸起14的高度，以避免在随后的倒装过程中焊线15与基板10接触。由于多个芯片通过焊线彼此连接，因此不需要例如空气层的其他中间介质层，从而可以改善半导体堆叠封装结构的散热性，并且减少信号通过的界面，以提高信号传输的效率。
参照图5，以倒装的方式通过多个焊料凸起14将第二芯片12和基板10彼此连接。焊线15可以与基板10分隔开。在第二芯片12为逻辑芯片的情况下，具有较多输入引脚、输出引脚的逻辑芯片可以以倒装的方式与基板10连接。不需要对逻辑芯片进行重新设计或额外地占用逻辑芯片的面积。
参照图6，去除载板18。例如，可以通过加热使热熔胶融化，以去除载板18；或者可以通过紫外光照射由光敏材料形成的光敏粘结层来降低光敏粘结层的粘性，以去除载板18。然而，本发明不限于此。
参照图7，对第一芯片11、第二芯片12和基板10进行模封，以形成塑封体16。塑封体16可以用于保护第一芯片11、第二芯片12、焊线15和基板10等。
参照图8，在基板10的下端形成焊球17。例如，可以通过值球工艺在基板10的下端形成多个焊球17，使得芯片可以与其他电路连接。
在下文中，将参照图9描述根据本发明的另一示例性实施例的半导体堆叠封装结构2。
图9是示出根据本发明的另一示例性实施例的半导体堆叠封装结构2的剖视图。将省略图9中示出的半导体堆叠封装结构2与图1中示出的半导体堆叠封装结构1的重复部件的描述，而着重于它们之间的区别。
如图9所示，根据本发明的另一示例性实施例的半导体堆叠封装结构2包括：基板10；第二芯片12，表面形成有多个焊料凸起14；第一芯片11，位于第二芯片12上方；第三芯片13，位于第一芯片11上方，其中，第二芯片12以倒装的方式通过多个焊料凸起14与基板10连接，第三芯片13通过焊线25与第一芯片11连接，第一芯片11通过焊线25与第二芯片12连接。
根据示例性实施例，第二芯片12可以为具有高速信号需求和较多输入引脚、输出引脚需求的逻辑芯片。第一芯片11可以为存储芯片。第三芯片13可以为存储芯片或具有其他功能的芯片，例如微机电传感器芯片等。
第二芯片12可以作为倒装芯片，以通过多个焊料凸起14与基板10连接。
第一芯片11和第二芯片12之间以及第一芯片11和第三芯片13之间可以分别通过对应的焊线25进行互联，从而实现多个芯片之间的通信。
根据示例性实施例，半导体堆叠封装结构2还可以包括塑封体16和设置于基板10的下端的焊球17。
在下文中，将参照图10描述根据本发明的另一示例性实施例的半导体堆叠封装结构3。
图10是示出根据本发明的另一示例性实施例的半导体堆叠封装结构3的剖视图。将省略图10中示出的半导体堆叠封装结构3与图1中示出的半导体堆叠封装结构1的重复部件的描述，而着重于它们之间的区别。
如图10所示，根据本发明的另一示例性实施例的半导体堆叠封装结构3包括：基板10；第二芯片12，表面形成有多个焊料凸起14；第一芯片11，位于第二芯片12上方；第三芯片13，位于第一芯片11上方，其中，第二芯片12以倒装的方式通过多个焊料凸起14与基板10连接，第一芯片11通过焊线35与第二芯片12连接，第三芯片13通过焊线35与第二芯片12连接。
根据示例性实施例，第二芯片12可以为具有高速信号需求和较多输入引脚、输出引脚需求的逻辑芯片。第一芯片11可以为存储芯片。第三芯片13可以为存储芯片或具有其他功能的芯片，例如微机电传感器芯片等。
第二芯片12可以作为倒装芯片，以通过多个焊料凸起14与基板10连接。
第一芯片11和第三芯片13可以分别通过对应的焊线35与第二芯片12进行互联，从而实现多个芯片之间的通信。
根据示例性实施例，半导体堆叠封装结构3还可以包括塑封体16和设置于基板10的下端的焊球17。
虽然在图9和图10中仅示出了包含第一芯片11、第二芯片12和第三芯片13的情况，但是根据本发明的半导体堆叠封装结构还可以包括更多个芯片，不同的芯片之间通过焊线进行互联。根据示例性实施例的半导体堆叠封装结构还可以包括位于第一芯片11上的至少一个芯片，不同的芯片之间通过焊线彼此连接。
在根据本发明的示例性实施例的半导体堆叠封装结构包括多个芯片的情况下，根据本发明的示例性实施例的制造半导体堆叠封装结构的方法包括：在载板上形成至少一个芯片；在所述至少一个芯片上形成倒装芯片，倒装芯片的上表面形成有多个焊料凸起；通过焊线使不同的芯片彼此连接；以倒装的方式通过所述多个焊料凸起将所述倒装芯片和所述基板彼此连接；去除所述载板。根据示例性实施例，不同的芯片之间的彼此连接可以是相邻的芯片通过焊线互联，或者各芯片通过焊线与倒装芯片互联。
根据本发明的示例性实施例的半导体堆叠封装结构及其制造方法通过芯片到芯片的引线键合来实现不同芯片之间的连接，并且仅作为倒装芯片的芯片通过倒装的方式与基板连接，从而可以确保半导体堆叠封装结构中的每个芯片均为良好的芯片。与传统的层叠封装技术相比，半导体堆叠封装结构仅包含一个基板，从而可以减小封装结构的尺寸；多个芯片通过焊线彼此连接，从而不需要例如空气层的其他中间介质层，以改善半导体堆叠封装结构的散热性；由于通过焊线实现芯片之间的连接，因此信号通过的界面减少，从而提高信号传输的效率。与传统的3D封装技术相比，不需要对逻辑芯片进行重新设计或额外地占用逻辑芯片的面积，从而降低成本。
尽管已经参照示例性实施例具体描述了本发明，但是本领域的技术人员应该理解，在不脱离权利要求所限定的本发明的精神和范围的情况下，可以对其进行形式和细节上的各种改变。

Claims (10)

1.一种半导体堆叠封装结构，其特征在于所述半导体堆叠封装结构包括：
基板；
第二芯片，表面形成有多个焊料凸起；以及
第一芯片，位于所述第二芯片上方，
其中，所述第二芯片以倒装的方式通过所述多个焊料凸起与所述基板连接，所述第一芯片通过焊线与所述第二芯片连接。
2.根据权利要求1所述的半导体堆叠封装结构，其特征在于所述焊线与所述基板分隔开。
3.根据权利要求1所述的半导体堆叠封装结构，其特征在于所述第二芯片为具有高速信号需求的芯片。
4.根据权利要求3所述的半导体堆叠封装结构，其特征在于所述第二芯片为逻辑芯片，所述第一芯片为存储芯片。
5.根据权利要求1所述的半导体堆叠封装结构，其特征在于所述半导体堆叠封装结构还包括用于保护所述第一芯片、所述第二芯片和所述基板的塑封体。
6.根据权利要求1所述的半导体堆叠封装结构，其特征在于所述半导体堆叠封装结构还包括设置于所述基板的下端的焊球。
7.根据权利要求1所述的半导体堆叠封装结构，其特征在于所述半导体堆叠封装结构还包括位于所述第一芯片上的至少一个芯片，不同的芯片之间通过焊线彼此连接。
8.一种制造半导体堆叠封装结构的方法，其特征在于所述方法包括：
在载板上形成第一芯片；
在所述第一芯片上形成第二芯片，所述第二芯片的上表面形成有多个焊料凸起；
通过焊线连接所述第一芯片和所述第二芯片；
以倒装的方式通过所述多个焊料凸起将所述第二芯片和基板彼此连接；
去除所述载板。
9.根据权利要求8的方法，其特征在于所述方法还包括：在去除所述载板之后，对所述第一芯片、所述第二芯片和所述基板进行模封以形成塑封体，在所述基板的下端形成焊球。
10.一种制造半导体堆叠封装结构的方法，其特征在于所述方法包括：
在载板上形成至少一个芯片；
在所述至少一个芯片上形成倒装芯片，所述倒装芯片的上表面形成有多个焊料凸起；
通过焊线使不同的芯片彼此连接；
以倒装的方式通过所述多个焊料凸起将所述倒装芯片和所述基板彼此连接；
去除所述载板。
CN201710192547.XA 2015-07-31 2015-07-31 一种半导体堆叠封装结构及其制造方法 Pending CN106920789A (zh)

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