CN108630626A - 无基板封装结构 - Google Patents

无基板封装结构 Download PDF

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Publication number
CN108630626A
CN108630626A CN201710594249.3A CN201710594249A CN108630626A CN 108630626 A CN108630626 A CN 108630626A CN 201710594249 A CN201710594249 A CN 201710594249A CN 108630626 A CN108630626 A CN 108630626A
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China
Prior art keywords
chip
encapsulation
closing line
adhesive layer
layer
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CN201710594249.3A
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English (en)
Inventor
范文正
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Powertech Technology Inc
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Powertech Technology Inc
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Publication of CN108630626A publication Critical patent/CN108630626A/zh
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Abstract

本发明提供了一种无基板封装结构，包含一芯片、一接合线、一封胶层及一重布层。该芯片包含一导电接脚。该接合线接合于该芯片的该导电接脚。该封胶层包覆该芯片及该接合线。该重布层设置于该封胶层上，且电性接触于该接合线的一外露部分。本发明可降低堆叠式封装的厚度，从而制造具有低侧高的超薄堆叠式封装结构。

Description

无基板封装结构
技术领域
本发明是关于一种封装结构，尤指一种具低侧高的无基板封装结构。
背景技术
在封装领域，尺寸是需高度考虑的产品特征。若封装后的集成电路(IC)芯片的尺寸可较小，则可更易于嵌入终端产品(例如移动电话或电子仪器)。因此，更小的芯片尺寸有助于产品竞争力。
为了缩小封装尺寸，已有多种方法可使用。举例而言，堆叠式封装(package-on-package，PoP)工艺可用以将两个、或更多已封装的芯片通过球栅阵列(ball grid array，BGA)垂直堆叠。多个芯片可因此整合于一封装内，从而可降低尺寸及电路复杂度。然而，该方法仍不易降低封装的厚度。由于堆叠式封装包含至少两互相堆叠的封装，故堆叠式封装的常见问题是厚度过厚而难以缩减。以移动电话等应用而言，堆叠式封装嵌入于小尺寸装置的难度高，因此，本领域仍须可降低封装结构的厚度的解决方案。
发明内容
本发明实施例提供一封装，包含一芯片、一接合线、一封胶层及一重布层。该芯片包含一导电接脚。该接合线接合于该芯片的该导电接脚。该封胶层包覆该芯片及该接合线。该重布层设置于该封胶层上，且耦接到该接合线的一外露部分。
本发明另一实施例提供一种封装方法，包含将一芯片设置于一载体上；将一接合线接合到该芯片的一导电接脚；填充一封胶材料以形成一封胶层，该封胶层包覆该芯片及该接合线，该封胶层包含一第一面及一第二面，该第二面接触该载体；移除该载体；从该第一面降低该封胶层的厚度以使该接合线的一部分外露；及将一重布层设置于该封胶层的该第一面，该重布层接触该接合线外露于该封胶层的的该部分。该芯片、该接合线、该封胶层及该重布层属于一封装。
本发明可降低堆叠式封装的厚度，从而制造具有低侧高的超薄堆叠式封装结构。
附图说明
图1是实施例的封装结构的示意图。
图2是另一实施例的封装结构的示意图。
图3是另一实施例的封装结构的示意图。
图4是实施例的封装方法的流程图。
图5至图11是对应于图4的步骤的工艺示意图。
图12是另一实施例的封装方法的流程图。
图13至图18是对应于图12的步骤的工艺示意图。
附图标号
100a、200、300 封装结构
110、210、310 第一封装
120、220 第二封装
110d 第一芯片
110f、2106、2109 粘贴层
110w、2102 接合线
110e、2103、2206 封胶层
110s 第一基板层
110b、120b、2105、2205、2203 导电焊球
120d 第二芯片
120s 第二基板层
TH1、Hb 厚度
2101、2204、2108 芯片
2104 重布层
2101a、2108a 导电接脚
2102a 端点
2102e 外露部分
2202 基板层
2201 导电介面
488 载体
400、1200 封装方法
410至450、1208至1250 步骤
210a 接面
21031 第一面
21032 第二面
具体实施方式
图1是实施例的封装结构100a的示意图。封装结构100a是堆叠式封装(PoP)结构，包含第一封装110及第二封装120。第一封装110包含第一芯片110d、粘贴层110f、接合线110w、封胶层110e、第一基板层110s及导电焊球110b。第二封装120包含第二芯片120d、第二基板层120s、及导电焊球120b。封装结构100a可用的堆叠式封装结构，但须使用至少两基板层(如110s、120s)，且封装结构100a的厚度TH1须包含第一基板层110s及第二基板层120s的厚度。
图2是另一实施例中，封装结构200的示意图。封装结构200可包含第一封装210、及第二封装220。第一封装210可包含芯片2101、接合线2102、封胶层2103、重布层(redistribution layer，RDL)2104及导电焊球2105。芯片2101可包含导电接脚2101a。接合线2102接合(bond)于芯片2101的对应的导电接脚2101a。封胶层2103包覆芯片2101及接合线2102。重布层2104设置于封胶层2103上，且电性耦接到接合线2102的外露部分2102e。将接合线2102打线接合后，可形成环弧状结构，具有弧高。当接合线2102被接合到芯片2101及载体488(示于图6)后，接合线2102可接合到芯片2101以形成第一接合点，且被拉牵至载体488的预期位置，接合于该预期位置以形成第二接合点。当拉牵接合线2102到该预期位置时，该拉线(loop)操作可将接合线2102置入于第一接合点与第二接合点之间，且形成弧拱状。当打线工具以自然拋物线或椭圆曲线拉牵接合线，导致的弧拱状可称为线弧(wireloop)。线弧的特征可包含形状、长度及高度，且该些特征可整合为接合线的一组线弧记录。如图2所示，外露部分2102e位于接合线2102的弧状部分。封胶层2103的高度可实质上等于接合线2102的弧高。
导电焊球2105可焊接于重布层2104。第二封装220可包含导电介面2201。导电介面2201可电连接于第一封装210的导电焊球2105，用以于第一封装210及第二封装220之间，发送及/或接收信号及数据。由于每条接合线2102的端点2102a外露于第一封装210的接面210a，且端点2102a可电性耦接于芯片2101，可选择性地将第三半导体芯片设置于第一封装210的接面210a。每条接合线2102的端点2102a可用以电性耦接一第三封装及第一封装210。举例而言，第三封装的每一连接端点，可直接耦接于接合线2102的端点2102a。或者，电连接于端点2102a的重布层可形成于第一封装210的接面210a，且第三封装的每一连接端点可通过该重布层，对应地电性耦接到接合线2102的端点2102a。
如图2所示，第二封装220可另包含芯片2204、基板层2202、导电焊球2203、封胶层2206、及导电焊球2205，位于芯片2204及基板层2202之间。基板层2202可包含设计电路。基板层2202可为多层架构。重布层2104可设计且规划线路以形成电路。芯片2204可包含接脚，连接于导电焊球2205。每个导电焊球2205可连接于对应的基板层2202的导电介面2201，以形成芯片2204及基板层2202之间的数据路径。
重布层2104形成的电路、及基板层2202形成的电路，可根据应用或产品规格而予以设计。因此，在芯片2101及2204之间，可通过导电接脚2101a、接合线2102的外露部分2102e、重布层2104、导电焊球2105、导电介面2201、基板层2202、及连接于芯片2204的导电焊球2205，发送且接收数据及信号。换言之，通过接合线2102的外露部分2102e，可建立通信路径。
根据实施例，第一封装210可包含粘贴层2106，粘贴于第一芯片2101。封胶层2103及2206可使用(但不限于)环氧树脂模塑材料(epoxy molding compound，EMC)或其他适宜的树脂类形成。导电焊球2203可用以接触外部电路，例如外部的印刷电路板(PCB)等。
图3是实施例中，封装结构300的示意图。封装结构300相似于封装结构200，包含第一封装310及第二封装220。相较于图2的第一封装210，图3的第一封装310另包含芯片2108。芯片2108包含导电接脚2108a。除了接合于芯片2101的导电接脚2101a，图3的接合线2102可另接合于芯片2108的导电接脚2108a。因此，在图3的示例中，数据及信号可通过接合线2102的外露部分，在芯片2101、2202、2108之间传送。上述中，多条接合线2102可用于解释封装结构200、300的操作。然而根据实施例，封装结构200、300亦可仅有单条接合线具有外露部分，亦可实现封装结构200、300的操作。图3中，粘贴层2109可粘贴于芯片2108以保护且固定芯片2108。粘贴层2109可为(但不限于)芯片黏附薄膜(die attach film，DAF)。在图2及图3中，第一封装210及第一封装310可视为上封装。根据不同实施例，上封装可包含一个、二个或更多芯片。图3中，厚度Hb可为150微米-200微米(micrometer)。常用的堆叠式封装(PoP)中，上封装的封胶层可约为350微米。因此，根据本发明实施例，上封装(不含导电焊球)的厚度可降低至现有技术的42.8％至57.1％。此外，如图2、图3所示，封装结构200或300可仅包含一基板层，亦即基板层2202。然而，图1的封装结构100a包含两基板层110s、120s。因此，封装结构200、300的厚度，相较于封装结构100a，可更加降低。因此，根据本发明实施例，可得到超薄堆叠式封装(super thin PoP)结构。图3中，外露部分2102e可电连接导电接脚2101a，故可使导电焊球2105耦接到芯片2101。另一例中，外露部分2102e可电连接到导电接脚2101a及2108a，故可使导电焊球2105耦接到芯片2101及2108。
图4是根据实施例，封装方法400的流程图。封装方法400可用以制造封装结构200，其可包含下列步骤。
步骤410：将芯片2101设置于载体488上；
步骤415：将接合线2102接合到芯片2101的导电接脚2101a；
步骤420：填充封胶材料以形成封胶层2103，封胶层2103包覆芯片2101及接合线2102，封胶层2103包含第一面21031及第二面21032，第二面21032接触载体488；
步骤430：从第一面21031降低封胶层2103的厚度，以使接合线2102的外露部分2102e可外露；
步骤435：将重布层2104设置于封胶层2103的第一面21031，重布层2104可接触接合线2102外露于封胶层2103的外露部分2102e；
步骤440：将导电焊球2105焊接于重布层2104；
步骤445：移除载体488；及
步骤450：将第一封装210设置于第二封装220(如图2所示)，其中导电焊球2105可接触第二封装220的导电介面2201。
图5至图11、及图2，可为分别对应图4的步骤410至450的工艺示意图。图5至图11中，可见图2的封装结构200的上封装210的工艺。
步骤415中，接合线2102可接合至导电脚位2101a及载体488，如图6所示。适宜的中介材料可用以将接合线2102固定于载体488。步骤450中，作为上封装的第一封装210可翻转，以使导电焊球2105可焊接于导电介面2201，从而建立第一封装210及第二封装220之间的传输路径。
图5至图11中制造的上封装只包含单一芯片，然而根据其他实施例，上封装可包含更多芯片，如图3所示。图12是实施例中，封装方法1200的流程图。封装方法1200中，可在上封装设置多个芯片，其可包含以下步骤。
步骤1208：将芯片2108设置于载体488上；
步骤1210：将芯片2101设置于芯片2108上；
步骤1215：将接合线2102接合至芯片2101的导电脚位2101a及芯片2108的导电脚位2108a；
步骤1220：填充封胶材料以形成封胶层2103，封胶层2103包覆芯片2101、芯片2108及接合线2103，封胶层2103具有第一面21031及第二面21032，第二面21032接触载体488；
步骤1230：从第一面21031降低封胶层2103的厚度，以使接合线2102的外露部分2102e可外露；
步骤1235：将重布层2104设置于封胶层2103的第一面21031，重布层2104可接触接合线2102外露于封胶层2103的外露部分2102e；
步骤1240：将导电焊球2105焊接于重布层2104；
步骤1245：移除载体488；及
步骤1250：将第一封装310设置于第二封装220(如图3所示)，其中导电焊球2105可接触第二封装220的导电介面2201。
图13至图18可为图3的封装结构300的上封装，即第一封装310的工艺示意图。图13、图14可对应于步骤1208、1210、1215。如图14所示，当上封装(如第一封装310)具有两芯片(如芯片2108、2101)时，接合线2102除了接合于芯片2101的导电接脚2101a，还可另接合于芯片2108的导电接脚2108a，从而形成芯片2101及2108之间的传输路径。图15可对应于步骤1220。图16可对应于步骤1230。图17可对应于步骤1235至1240。图18可对应于步骤1245。图3可对应于步骤1250。在步骤445及1245中，载体488可通过研磨、刻蚀、及/或剥离等方式移除。步骤430及1230中，封胶层2103的厚度可通过研磨来降低。载体488可作为基底元件，使芯片及封胶层2103可形成于其上，待形成后，则载体488可移除。载体488可由玻璃、陶瓷、塑胶及/或适宜的材料形成。如图5所示，粘贴层2106可粘贴设置于芯片2101及载体488之间。举例而言，粘贴薄膜(例如芯片黏附薄膜)可粘贴于未切割的芯片，该芯片承载芯片2101。芯片被切割后，芯片2101可粘附一片粘贴薄膜，亦即粘贴层2106。同理，根据图13至图17的实施例，可将粘贴层2106设置于芯片2101及2108之间，粘贴层2109可设置于芯片2108及载体488之间，以提升可靠度。
综上，根据本发明实施例提供的封装(如210、310)、封装方法(如400、1200)及封装结构(如200、300)，可降低堆叠式封装的厚度，从而制造具有低侧高的超薄堆叠式封装结构。
以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (10)

1.一种封装，其特征在于，包含：
一第一芯片，包含一导电接脚；
一接合线，接合于该第一芯片的该导电接脚；
一封胶层，包覆该第一芯片及该接合线；及
一重布层，设置于该封胶层上，且耦接到该接合线的一外露部分。
2.如权利要求1所述的封装，其特征在于，另包含：
一第二芯片，堆叠于该第一芯片上，且包含一导电接脚；
其中该封胶层另包覆该第二芯片，且该接合线另接合于该第二芯片的该导电接脚。
3.如权利要求2所述的封装，其特征在于，另包含：
一第一粘贴层，粘贴于该第一芯片及该第二芯片之间；及
一第二粘贴层，粘贴于该第二芯片。
4.一种封装结构，其特征在于，包含：
一第一封装，包含：
一第一芯片，包含一导电接脚；
一接合线，接合于该第一芯片的该导电接脚；
一封胶层，包覆该第一芯片及该接合线；及
一重布层，设置于该封胶层上，且电连接于到该接合线的一外露部分；及
一导电焊球，焊接于该重布层；及
一第二封装，包含一导电介面，该导电介面电连接于该第一封装的该导电焊球。
5.如权利要求4所述的封装结构，其特征在于，该第一封装另包含一第二芯片，设置于该第一芯片上，该第二芯片包含一导电接脚，且该接合线另接合于该第二芯片的该导电接脚。
6.如权利要求5所述的封装结构，其特征在于，该第一封装另包含：
一第一粘贴层，粘贴于该第一芯片及该第二芯片之间；及
一第二粘贴层，粘贴于该第二芯片。
7.一种封装方法，其特征在于，包含：
将一第一芯片设置于一载体上；
将一接合线接合到该第一芯片的一导电接脚；
填充一封胶材料以形成一封胶层，该封胶层包覆该第一芯片及该接合线，该封胶层包含一第一面及一第二面，该第二面接触该载体；
移除该载体；
从该第一面降低该封胶层的厚度以使该接合线的一部分外露；及
将一重布层设置于该封胶层的该第一面，该重布层接触该接合线外露于该封胶层的的该部分；
其中该第一芯片、该接合线、该封胶层及该重布层属于一第一封装。
8.如权利要求7所述的方法，其特征在于，另包含：
将一导电焊球焊接于该重布层；及
将该第一封装设置于一第二封装之上；
其中该导电焊球接触该第二封装的一导电介面。
9.如权利要求7所述的方法，其特征在于，另包含：
将一第二芯片设置于该载体及该第一芯片之间；
其中该接合线另接合于该第二芯片的一导电接脚。
10.如权利要求7所述的方法，其特征在于，将该重布层设置于该封胶层的该第一面，包含：
对该重布层规划连线以形成一电路；及
将已规划线路的该重布层设置于该封胶层的该第一面。
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