CN108389850A - 三维系统级封装结构及其封装方法 - Google Patents

三维系统级封装结构及其封装方法 Download PDF

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CN108389850A
CN108389850A CN201810419313.9A CN201810419313A CN108389850A CN 108389850 A CN108389850 A CN 108389850A CN 201810419313 A CN201810419313 A CN 201810419313A CN 108389850 A CN108389850 A CN 108389850A
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袁鹰
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Abstract

本发明公开了一种三维系统级封装结构与封装方法，包括QFN(Quad Flat No‑lead)封装基体以及倒置于其中的内嵌封装体，内嵌封装体的上表面设置有内嵌封装体的电路引出端，在内嵌封装体的上表面上方放置有芯片（集成电路芯片和/或微机电芯片）和/或其他元器件并且与内嵌封装体电路引出端或QFN的焊盘通过相应的电连接机构形成电连接，内嵌封装体电路引出端通过相应的电连接机构与QFN的焊盘形成至少一个电连接。本方案可以在内嵌封装体内外都进行2D/3D芯片集成，集成芯片数量多，集成灵活性大，工艺成熟容易实现，成本低，适用于将各类芯片形成系统级集成模块，产品质量有充分保证，具有很高良品率。

Description

三维系统级封装结构及其封装方法
技术领域
本发明属于集成电路芯片封装领域，具体地，是一种系统级封装结构与封装方法。
背景技术
集成电路芯片是20世纪50年代后期及60年代发展起来的一种新型半导体器件，它是经过氧化、光刻、扩散、外延、蒸铝等半导体制造工艺，将具有一定功能电路所包含的晶体管、电阻、电容等元件及它们之间的电连接机构全部集成在一小块硅片表面上，再通过封装工艺将硅片表面电路与外部建立电连接并保护起来。因此集成电路的封装是把集成电路芯片装配为最终产品的过程，最常见的是将芯片制造厂家（Foundry）生产出来的集成电路裸芯片放在一块起到承载作用的基板上，把管脚引出来，然后固定包封形成一个封装体的过程。
随着消费类电子产品、航空航天电子、军事电子等技术的飞速发展，作为现代信息技术核心的半导体器件必须最大限度地实现小型化、轻量化、高密度化及高可靠性。而集成电路技术的工艺节点正在接近其物理极限，长期以来遵循的摩尔定律即芯片特征尺寸等比例缩小的原则，在实际应用中已无法满足半导体技术发展的需求。为满足产品轻、薄、短、小以及系统整合的需求，各种式样的封装技术于是被推陈出新。
系统级封装(System in Package，SiP)利用成熟的封装工艺集成多种元器件，即在一个封装体内组装多个集成电路芯片、各种类型的元器件、以及诸如微机电(MEMS)或者光学器件等，实现一定功能的单个标准封装件，构成复杂且完整的电子系统，其周期短、成本低，因此作为在系统层面上延续摩尔定律的技术路线，得到了越来越多的关注和应用。系统级封装已经成为重要的先进封装和系统集成技术，是电子产品小型化和多功能化的重要技术路线，具有广阔的应用市场和发展前景，广泛应用于RF/无线、传感器、网络与计算机技术、高速数字产品、物联网终端等方面。
系统级封装方式没有一定型态。可用多芯片模块(Multi-chip Module；MCM)的平面式2D封装，也可用多芯片3D堆叠的结构，以有效缩减封装面积，其内部互连技术可以是单纯的引线键合(Wire Bonding)，亦可使用倒装焊(Flip Chip)方式，也可二者混用；除了2D与3D的芯片组合结构外，也可以通过封装体堆叠POP(Package on Package)方式来实现；可采用3D芯片埋入式或埋入式芯片+表面元件的方式达到功能整合的目的，亦属于系统级封装；另外的方式是通过硅通孔技术（Through Silicon Via，TSV）或晶圆级扇出型封装技术实现系统级封装。图1至图12给出了现有主要的系统级封装形式。这些不同的芯片排列方式，与不同的内部互连技术搭配，使SiP的封装型态产生多样化的组合，并可依照客户或产品的需求加以客制化或弹性生产。
在上述这些系统级封装方式中，2D封装方式的芯片数量受到封装尺寸与基板利用范围的限制；多芯片3D堆叠则受到芯片尺寸匹配及布线位置的制约而缺乏灵活性；封装堆叠方式在工艺中存在封装体翘曲问题，其经常难以克服，因而影响封装良率；芯片埋入式对嵌入的芯片有某些特殊要求，非通适可用；采用硅通孔技术（TSV）或晶圆级扇出型封装技术可以实现很小型的系统级封装，但其成本较为昂贵。
所以，有必要推出一种集成芯片数量多、集成灵活性较大、工艺简单且无典型工艺问题、成本较低、满足大多数应用要求的系统级封装形式。
发明内容
有鉴于此，本发明所要解决的技术问题是：提供一种三维系统级封装结构及封装方法，以解决现有技术中芯片集成度不高、集成灵活性不大、工艺困难点及成本等方面问题。
本发明为解决上述技术问题采用以下技术方案：
三维系统级封装结构与封装方法，包括QFN(Quad Flat No-lead)封装基体以及倒置于其中的内嵌封装体，内嵌封装体的上表面设置有内嵌封装体的电路引出端，在内嵌封装体的上表面上方放置有一个或多个芯片（集成电路芯片和/或微机电芯片）和/或其他元器件并且与内嵌封装体电路引出端或QFN的焊盘通过相应的电连接机构形成电连接，内嵌封装体电路引出端通过相应的电连接机构与QFN的焊盘形成至少一个电连接。
进一步地，所述内嵌封装体未被QFN封装完整包覆，内嵌封装体的下表面可以暴露出来，这种情况下不存在QFN的中央散热焊盘。
进一步地，所述内嵌封装体的上表面以及上方的芯片和/或元器件被QFN的塑封胶塑封，在特定应用情况下也可以使芯片/元器件的部分表面被暴露出来。
进一步地，某些应用需要情况下（如传感器），所述内嵌封装体的上表面有部分区域及该区域上方放置的芯片和/或元器件没有被QFN的塑封胶塑封。
进一步地，在所述内嵌封装体的上表面没有被塑封的区域上方放置已封装的元器件，形成POP(Package on Package)的封装结构。
进一步地，所述内嵌封装体中包含一个或多个芯片(集成电路芯片和/或微机电芯片)和/或其他元器件，这些芯片或元器件通过相应的电连接机构与内嵌封装体衬底部分形成电连接。
所述内嵌封装体中包含的芯片和/或元器件，与内嵌封装体上方的芯片和/或元器件通过内嵌封装体内部电路及其电路引出端、以及内嵌封装体上方电连接机构形成电连接，内嵌封装体电路引出端再通过电连接机构连接QFN焊盘，从而与外界形成电路连接，达到功能整合的系统级封装目的。
所述内嵌封装体内部所含、以及所述内嵌封装体上方的多个芯片都可以采用二维平铺、三维堆叠或是两者混合的方式进行放置。
进一步地，可以用中央漏空的有机载体基板替代传统的金属焊盘框架结构，有机载体基板上下表面有外露的焊盘。
进一步地，所述QFN的焊盘可采用多圈（多排）结构，以增加封装的引脚数量。
一种三维系统级封装结构，包括如下制作步骤：
步骤1、制作完成内嵌封装体。
步骤2、在QFN焊盘下方粘贴载体材料（此步骤为QFN常规工艺）。
步骤3、将内嵌封装体倒置并粘贴于QFN焊盘中间暴露的载体材料上(无中央散热焊盘)。
步骤4、在内嵌封装体的上表面放置芯片，制作形成芯片、内嵌封装体的电路引出端、QFN的焊盘三者间应有的电连接。
步骤5、进行QFN的塑封。
步骤6、去除QFN焊盘下方的载体材料。
对于多圈（多排）焊盘的情况，则首先对金属焊盘框架结构进行预塑封，再用机械切割的方法去除框架结构中多余的金属连接部分，以形成多圈且分散独立的QFN焊盘，这样避免了不需要的焊盘间电连接，再后续的工艺过程与上述步骤相同。
与现有技术相比，本发明具有以下有益效果：
1、本发明相当于在内嵌封装体内外都进行2D/3D芯片集成，芯片间信号线路短，因此方案封装集成度较高，集成芯片数量多，也适合于高速数字应用。
2、由于在内嵌封装体内外都进行2D/3D芯片集成，因此本发明方案集成灵活性较大，芯片放置匹配与布线设计自由度较大。
3、本发明方案中所有工艺均属常规制程，成熟简单且无典型工艺问题，成本较低。采用成熟的引线键合(Wire Bonding)或倒装焊(Flip Chip)工艺，亦或二者混用的方式即可实现系统产品内部的电连接。
利用本发明可以为RF/无线、传感器、网络与计算机技术、高速数字产品、物联网终端应用中需要的各类系统级模块做集成设计，制造出各种应用的集成产品投放市场。
附图表说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1至图12为列出的现有技术中系统级封装的多种主要形式。
图1 2D芯片QFP封装。
图2 2D芯片BGA封装。
图3 2D倒装芯片单元。
图4 3D芯片堆叠QFP封装。
图5 3D芯片堆叠（引线键合）。
图6 3D芯片堆叠（引线键合+倒装芯片）。
图7 SOP堆叠。
图8 封装体堆叠（POP）。
图9 3D芯片埋入式。
图10 埋入式芯片+表面芯片。
图11 TSV (Through Silicon Via)。
图12 3D扇出型WLP。
图13为传统的QFN封装结构。
图14为本发明以QFN为基体的三维系统级封装结构简图。
图15为具体实施例一的系统级封装结构。
图16为具体实施例一中热增强方案的示意图。
图17为具体实施例一中热增强方案的PCB贴装图。
图18是为具体实施例一设计的两圈焊盘的结构。
图19为本发明封装方法（具体实施例一为例）的流程图。
图20是本发明的多圈焊盘的制作说明图。
其中，图中的标记如下：1-I/O焊盘；2-中央散热焊盘；3-中央散热焊盘上方芯片；4-塑封胶；5-内嵌封装体；6-QFN封装基体；7-内嵌LGA(Land Grid Array)封装体；8-LGA的下表面；9-LGA内的芯片；10-LGA的基板；11-LGA内键合引线； 12-LGA塑封胶；13-LGA上表面；14-LGA的电路引出端；15-LGA上方芯片；16-LGA上方芯片与电路引出端的键合引线；17-LGA与I/O焊盘之间的键合引线；18-I/O焊盘；19-QFN塑封胶；20-倒装芯片；21-倒装芯片上的金属凸点；22-印刷电路板PCB；23-焊料；24-导热数脂；25-多圈焊盘；26-预塑封胶；27-QFN焊盘下方的载体材料(贴膜)。
具体实施方式
正如背景技术中所述，现有的系统级封装技术中，存在芯片集成度不高、集成灵活性不大、工艺困难点及成本高等方面问题。因此，本发明提出了一种三维系统级封装结构与封装方法，以解决上述问题。该结构以QFN封装为基体，为便于说明，下面与传统QFN封装作对比且结合附图，对本发明的结构作进一步表述。
图13为传统的QFN封装结构，其下部是I/O焊盘1和中央散热焊盘2，中央散热焊盘2上方放置有芯片3，它们均被塑封胶4塑封。以此为基础，图14为本发明的三维系统级封装构架简图，即在一个QFN封装基体内倒置一个内嵌封装体5，内嵌封装体5上方放置一个或多个芯片(集成电路芯片和/或微机电芯片)和/或其他元器件，内嵌封装体5内也包含有芯片和/或元器件，上述所有芯片及元器件通过电连接机构、内嵌封装体5内布线及电路端口形成需要的电互连，再通过电连接机构连接QFN焊盘，从而与外界形成电路连接，实现系统级封装。
图13与图14对比可见，本发明的封装结构充分利用了QFN的内部空间，相当于在内嵌封装体内外都进行2D/3D芯片集成，芯片间信号线路短，因此方案封装集成度较高，集成芯片数量多，也适合于高速数字应用；由于在内嵌封装体内外都进行2D/3D芯片集成，因此本发明方案集成灵活性较大，芯片放置匹配与布线设计自由度较大；工艺与成本方面，本发明是三维系统级封装的一种新的构架，其结构简单、成本较低、工艺成熟，采用传统的引线键合+倒装焊接方式就可进行规模化量产，极易实现产品化。
具体实施例一
参见图15，三维系统级封装结构包括QFN(Quad Flat No-lead)封装基体6以及倒置于其中的内嵌LGA（Land Grid Array）封装体7。QFN封装基体6去除了中央散热焊盘，LGA封装体7被置于QFN封装基体6的下部中央，且LGA封装体7未被完整包覆，其下表面8被暴露出来。LGA封装体7中包含两个集成电路芯片9，LGA基板10一侧在上方，集成电路芯片9一侧在下方且与LGA基板10通过键合引线11形成电连接。LGA封装体7内的芯片9与键合引线11均被LGA塑封胶12塑封。LGA的上表面13设置有LGA电连接金属外露端面14，在LGA上表面13上方放置有两个集成电路芯片15并且与LGA电连接金属外露端面14通过键合引线16形成电连接，LGA电连接金属外露端面14也通过键合引线17与QFN的I/O焊盘18形成至少一个电连接。I/O焊盘18、LGA封装体7、上方的两个集成电路芯片15以及键合引线16、17被QFN的塑封胶19塑封。由此，LGA封装体7内部两个芯片9与外部两个芯片15通过键合引线11、LGA基板内部电路、键合引线16形成电互连，再通过LGA基板内部电路、键合引线17、I/O焊盘18与外界实现电路连接。
传统QFN封装(参见图13)的I/O焊盘1长度L一般为0.4-0.6mm，I/O焊盘1与中央散热焊盘2之间的间隙G一般≥0.25mm以降低焊接时的桥连概率，因此中央散热焊盘上方芯片尺寸与放置匹配受到了一定限制。现参见图15，在本具体实施例一中没有中央散热焊盘，不存在桥连问题，因此LGA封装体7可以足够大，理论上LGA封装体7与I/O焊盘18之间的间隙可以足够小，但考虑到焊盘尺寸制造精度以及LGA封装体7的放置偏差精度，该间隙需要留有一定裕量。目前的焊盘尺寸制造精度为±0.025mm，LGA的四边至其中心的距离精度为±0.015mm，贴片机（以精度较高的倒装贴片机来考虑）的贴装精度为±0.006mm，假如预先设计留有0.05mm间隙，则足以满足总体的尺寸公差配合及工艺贴装需要。因此作为本发明实施例一的封装结构设计，设计焊盘长度为0.45mm，LGA封装体7与I/O焊盘18之间的间隙设计为0.05mm，两者相加使LGA封装体7最外边至QFN外边缘的距离为0.5mm，边缘距离0.5mm已经可以满足常用引线键合的工艺操作要求。因此在长宽方向上LGA封装体7比QFN尺寸总计小1mm，比如QFN外观长宽尺寸为6x6mm的话，那么内嵌LGA封装体7的长宽尺寸最大就可以做到5x5mm。另外，无中央散热焊盘使得LGA封装体下表面暴露，这种结构可以降低封装的整体厚度，满足薄型化需要。
本实施例仅以总计四个集成电路芯片为例进行说明，但不限于这些芯片，可根据不同的用户需求设置多个不同的芯片（包括微机电芯片）和/或其他元器件，再加上应用多种电互连或其混合方式（如引线键合+倒装焊），同时内嵌LGA封装体7内外所有芯片可以采用二维平铺、三维堆叠或是两者混合的方式进行放置，因而可配置成不同的组合进行设置。
图16示出了具体实施例一的另一种配置方式，与前述唯一不同的是：其内嵌LGA封装体内只放置一个倒装芯片20，它通过表面的金属凸点21与基板形成电连接，倒装芯片20及金属凸点21被LGA塑封胶以MUF(Molded Underfill)的形式塑封，但倒装芯片20未被完全包覆，其背面被暴露出来。图17是该种方式的PCB贴装示意图，在与印刷电路板(PCB)22焊接时，其I/O焊盘用焊料23与PCB连接，而倒装芯片的背面可用导热树脂24与PCB连接，芯片工作产生的热量就可以直接通过导热数脂24往下经PCB散发，改善封装的热性能，这样为解决系统级封装中的高耗热器件散热问题提供了有效的方案。
参见图18，这是具体实施例一的多圈（多排）焊盘情况下的结构，图18中示出了有两圈焊盘25的封装结构，焊盘之间包含有预塑封胶26。预塑封胶26的作用是固定焊盘结构，使分散的独立焊盘在工艺过程中稳固不动。
下面，就本发明的三维系统级封装方法进行描述。请参见图19，以具体实施例一为例，该三维系统级封装方法包括如下步骤：
步骤1、制作完成内嵌LGA封装体，内含两个集成电路芯片。
步骤2、在QFN焊盘下方粘贴载体粘贴膜27（此步骤为QFN常规工艺）。
步骤3、将内嵌封装体倒置并粘贴于QFN焊盘中间暴露的载体粘贴膜27上。
步骤4、在内嵌封装体的上表面贴装两个芯片，采用引线键合工艺，制作形成芯片、内嵌封装体的电路引出端、QFN的焊盘三者间应有的电连接。
步骤5、进行QFN的塑封。
步骤6、去除QFN焊盘下方的载体粘贴膜27。
对于多圈（多排）焊盘的情况，则需要先制作多圈金属焊盘框架，再后续的工艺过程与上述步骤相同。
参见图20，图20给出了本发明的多圈金属焊盘框架制作的简要说明。首先对金属焊盘框架结构进行预塑封，再用机械切割的方法去除框架结构中多余的金属连接部分，以形成多圈且分散独立的QFN焊盘，这样避免了不需要的焊盘间电连接。目前封装工艺中常用的切割刀具及工艺能力完全可以满足去除多余金属、保证焊盘尺寸与结构的要求。
如前所述，可以用倒装贴片机将LGA封装体贴装在QFN焊盘下方的载体粘贴膜上，目前倒装贴片机的贴装精度为±0.006mm，完全满足置片需要。粘贴膜通常具有很高粘性，能很好地粘牢LGA封装体，满足后续的装配需求。在用引线键合完成各类电连接的工艺中，粘贴膜的高粘性固定+膜下方的高真空底吸可以使整个机构稳固，保证引线键合工艺的顺利完成。所有步骤都可用常规设备和常规工艺来完成。
综上所述，本发明提出了一种三维系统级封装结构和封装方法，通过在QFN封装基体内倒置一个内嵌封装体，在该内嵌封装体的内外都进行2D/3D芯片集成，从而大幅度增加集成芯片数量，明显提升了集成度，显著提高了芯片放置匹配性与布线设计自由度，集成灵活性大为改善，也可以为解决系统级封装中的高耗热器件散热问题提供有效的方案。相比较现有的系统级封装技术，本发明采用的QFN封装基体+内嵌封装体组合，其结构简单、成本较低、工艺成熟，采用传统的引线键合+倒装焊接方式就可进行规模化量产，极易实现产品化。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (9)

1.一种三维系统级封装结构，包括QFN(Quad Flat No-lead)封装基体以及倒置于其中的内嵌封装体，内嵌封装体的上表面设置有内嵌封装体的电路引出端，在内嵌封装体的上表面上方放置有一个或多个芯片（集成电路芯片和/或微机电芯片）和/或其他元器件并且与内嵌封装体电路引出端或QFN的焊盘通过相应的电连接机构形成电连接，内嵌封装体电路引出端通过相应的电连接机构与QFN的焊盘形成至少一个电连接。
2.根据权利要求1所述的三维系统级封装结构，其特征在于：所述内嵌封装体未被QFN封装完整包覆，内嵌封装体的下表面可以暴露出来，这种情况下不存在QFN的中央散热焊盘。
3.根据权利要求1所述的三维系统级封装结构，其特征在于：所述内嵌封装体的上表面以及上方的芯片和/或元器件被QFN的塑封胶塑封，在特定应用情况下也可以使芯片/元器件的部分表面被暴露出来。
4.根据权利要求1所述的三维系统级封装结构，其特征在于：某些应用需要情况下（如传感器），所述内嵌封装体的上表面有部分区域及该区域上方放置的芯片和/或元器件没有被QFN的塑封胶塑封。
5.根据权利要求4所述的三维系统级封装结构，其特征在于：在所述内嵌封装体的上表面没有被塑封的区域上方放置已封装的元器件，形成POP(Package on Package)的封装结构。
6.根据权利要求1所述的三维系统级封装结构，其特征在于：所述内嵌封装体中包含一个或多个芯片(集成电路芯片和/或微机电芯片)和/或其他元器件，这些芯片或元器件通过相应的电连接机构与内嵌封装体衬底部分形成电连接，所述内嵌封装体内部所含、以及所述内嵌封装体上方的多个芯片都可以采用二维平铺、三维堆叠或是两者混合的方式进行放置。
7.根据权利要求2所述的三维系统级封装结构，其特征在于：用中央漏空的有机载体基板替代传统的金属焊盘框架结构，有机载体基板上下表面有外露的焊盘。
8.根据权利要求1所述的三维系统级封装结构，其特征在于： 所述QFN的焊盘为多圈（多排）结构，以增加封装的引脚数量。
9.一种基于权利要求1所述的三维系统级封装结构封装方法，其特征在于：
封装工艺包括如下步骤：
步骤1、制作完成内嵌封装体；
步骤2、在QFN焊盘下方粘贴载体材料；
步骤3、将内嵌封装体倒置并粘贴于QFN焊盘中间暴露的载体材料上(无中央散热焊盘)；
步骤4、在内嵌封装体的上表面放置芯片，制作形成芯片、内嵌封装体的电路引出端、QFN的焊盘三者间应有的电连接；
步骤5、进行QFN的塑封；
步骤6、去除QFN焊盘下方的载体材料；
多圈焊盘QFN的封装工艺包括如下步骤：
首先对金属焊盘框架结构进行预塑封，再用机械切割的方法去除框架结构中多余的金属连接部分，以形成多圈且分散独立的QFN焊盘，避免了不需要的焊盘间电连接。
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CN110190051A (zh) * 2019-05-29 2019-08-30 广州致远电子有限公司 混合信号微控制器、设备及制备方法
CN112447606A (zh) * 2019-08-29 2021-03-05 天津大学青岛海洋技术研究院 一种应用于系统级封装的去耦电容放置方法
CN113540069A (zh) * 2021-07-20 2021-10-22 甬矽电子(宁波)股份有限公司 芯片叠层封装结构和芯片叠层封装方法
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CN110190051A (zh) * 2019-05-29 2019-08-30 广州致远电子有限公司 混合信号微控制器、设备及制备方法
CN110190051B (zh) * 2019-05-29 2021-03-19 广州致远电子有限公司 混合信号微控制器、设备及制备方法
CN112447606A (zh) * 2019-08-29 2021-03-05 天津大学青岛海洋技术研究院 一种应用于系统级封装的去耦电容放置方法
CN113540069A (zh) * 2021-07-20 2021-10-22 甬矽电子(宁波)股份有限公司 芯片叠层封装结构和芯片叠层封装方法
CN113540069B (zh) * 2021-07-20 2024-02-02 甬矽电子(宁波)股份有限公司 芯片叠层封装结构和芯片叠层封装方法
CN115441135A (zh) * 2022-08-09 2022-12-06 中国电子科技集团公司第五十五研究所 一种高可靠超宽带三维堆叠微波组件及其制作方法
CN115441135B (zh) * 2022-08-09 2023-12-01 中国电子科技集团公司第五十五研究所 一种高可靠超宽带三维堆叠微波组件及其制作方法

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