CN101290929B - 堆栈式芯片封装结构 - Google Patents
堆栈式芯片封装结构 Download PDFInfo
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Abstract
本发明公开了一种堆栈式芯片封装结构,包括一导线架、一芯片封装体、一第二芯片与一第二封装胶体。导线架具有多个彼此电性绝缘的第一引脚及第二引脚。第一引脚具有一第一上表面,第二引脚具有一第二上表面,第一上表面与第二上表面不共平面。芯片封装体配置于第一引脚上,其包括一衬底、一第一芯片以及一第一封装胶体。第二芯片堆栈于芯片封装体上,且与第二引脚电性连接。第二封装胶体配置于导线架上,且填充于各第一及第二引脚之间,以包覆芯片封装体与第二芯片。
Description
技术领域
本发明是有关于一种芯片封装结构,且特别是有关于一种堆栈式芯片封装结构。
背景技术
在半导体产业中,集成电路(integrated circuits,IC)的生产主要可分为三个阶段:集成电路的设计(IC design)、集成电路的制作(IC process)及集成电路的封装(IC package)。
在集成电路的制作中,芯片(chip)是经由晶圆(wafer)制作、形成集成电路以及切割晶圆(wafer sawing)等步骤而完成。晶圆具有一主动面(active surface),其泛指晶圆的具有主动元件(active device)的表面。当晶圆内部的集成电路完成之后,晶圆的主动面更配置有多个焊垫(bonding pad),以使最终由晶圆切割所形成的芯片可经由这些焊垫而向外电性连接于一承载器(carrier)。承载器例如为一导线架(leadframe)或一封装衬底(package substrate)。芯片可以打线接合(wire bonding)或覆晶接合(flip chip bonding)的方式连接至承载器上,使得芯片的这些焊垫可电性连接于承载器的接点,以构成一芯片封装结构。
图1A~1E绘示为在日本专利申请案公开案第2005-317998号中所揭露的一种半导体装置的制作流程剖面示意图。首先,请参看图1A,提供具有一铜箔21,此铜箔21具有分别形成于其上表面及下表面的一作为电性接点的第一图案化金属层22以及一第二图案化金属层23。请参看图1B,于铜箔21的下表面上形成一刻蚀阻抗层24,接着,利用第一图案化金属层22作为一刻蚀掩膜(etching mask)对铜箔21的上表面进行一半刻蚀(half-etching)工艺,以于在铜箔21的上表面上形成多个凹部R。之后,请参看图1C,藉由使用黏着层20将半导体装置11固定于其中一作为芯片座的凹部R上,且在半导体装置11与铜箔21的打线接合部12之间形成多条导线16。接着,请参看图1D,于铜箔21的上表面上形成一第二绝缘材料18,以包覆半导体装置11、导线16,以及铜箔21的上表面。最后,请参看图1E,利用第二图案化金属层23作为刻蚀掩膜对铜箔21的下表面进行背刻蚀工艺,以形成具有面阵列引脚(area array lead)的芯片封装结构10。
上述这种利用整块铜箔去刻蚀出芯片座及引脚的方式为一种新型式的QFN封装态样,其优点是引脚数目可以增加,使依据上述流程制作而成的封装体可朝向微型化与高密度化的方向发展。然而,目前这种新型式的QFN封装态样主要是做单一芯片的封装,并无法符合多芯片模块封装的潮流。
发明内容
有鉴于此,本发明的主要目的在于提供一种堆栈式芯片封装结构,其主要是将PIP(package-in-package)的概念导入新型式QFN型式的封装结构中,以提高芯片封装结构整体的构装密度。
本发明提出一种堆栈式芯片封装结构,其包括一导线架、一芯片封装体、一第二芯片以及一第二封装胶体。导线架具有多个彼此电性绝缘的第一引脚及第二引脚。这些第一引脚具有一第一上表面,而这些第二引脚具有一第二上表面,其中第一上表面与第二上表面不共平面。芯片封装体配置于这些第一引脚的第一上表面上,其包括一衬底、一第一芯片以及一第一封装胶体。衬底与这些第一引脚电性连接。第一芯片配置于衬底上,且与衬底电性连接。第一封装胶体配置于衬底上,且包覆第一芯片。第二芯片堆栈于芯片封装体上,且与上述第二引脚电性连接。第二封装胶体配置于导线架上,且填充于各第二引脚之间,以包覆芯片封装体与第二芯片。
在本发明的一实施例中,第一芯片是透过多条打线导线与衬底电性连接。
在本发明的一实施例中,第一芯片是透过多个焊球与衬底电性连接。
在本发明的一实施例中,芯片封装体进一步包括一第三芯片。此第三芯片堆栈于第一芯片上,且与衬底电性连接。
在本发明的一实施例中,芯片封装体进一步包括一第四芯片以及一第五芯片。第四芯片配置于衬底上,且与衬底电性连接,而第五芯片横跨于第一芯片与第四芯片之间,且第五芯片与第一芯片及第四芯片电性连接。
在本发明的一实施例中,衬底是透过多个焊球与第一引脚电性连接。
在本发明的一实施例中,芯片封装体是以倒置的方式配置于第一引脚上,且衬底是透过多条打线导线与第二引脚电性连接。
在本发明的一实施例中,第二芯片是透过多条打线导线与衬底电性连接。
在本发明的一实施例中,第二芯片是透过多条打线导线与第二引脚电性连接。
在本发明的一实施例中,第一引脚与第二引脚凸出于第二封装胶体外。
在本发明的一实施例中,堆栈式芯片封装结构进一步包括一第一黏着层,配置于第一芯片与衬底之间。
在本发明的一实施例中,堆栈式芯片封装结构进一步包括一第二黏着层,配置于第二芯片与芯片封装体之间。
本发明另提出一种堆栈式芯片封装结构,其包括一导线架、一芯片封装体、一第二芯片以及一第二封装胶体。导线架具有多个彼此电性绝缘的第一引脚及第二引脚。芯片封装体固定于导线架的第一引脚上,且包括一衬底、一第一芯片与一第一封装胶体。衬底具有一第一表面以及与其相对的一第二表面。此衬底包括多个配置于第二表面上的焊球,且这些焊球由导线架中暴露出来。第一芯片配置于衬底上,且与衬底电性连接。第一封装胶体配置于衬底上,且包覆第一芯片。第二芯片堆栈于芯片封装体上,且与这些第二引脚电性连接。第二封装胶体配置于导线架上,且填充于这些第一引脚与第二引脚之间,以包覆第一封装胶体与第二芯片。
在本发明的一实施例中,第一芯片是透过多条打线导线与衬底电性连接。
在本发明的一实施例中,第一芯片是透过多个焊球与衬底电性连接。
在本发明的一实施例中,芯片封装体进一步包括一第三芯片。此第三芯片堆栈于第一芯片上,且与衬底电性连接。
在本发明的一实施例中,芯片封装体进一步包括一第四芯片以及一第五芯片。第四芯片配置于衬底上,且与衬底电性连接。而第五芯片横跨于第一芯片与第四芯片之间,且第五芯片与第一芯片及第四芯片电性连接。
在本发明的一实施例中,第二芯片是透过多条打线导线与第二引脚电性连接。
在本发明的一实施例中,这些第一引脚与第二引脚凸出于第二封装胶体外。
在本发明的一实施例中,这些第一引脚分别具有一阶梯结构。这些阶梯结构形成一容置凹槽,使芯片封装体固定于容置凹槽中。
在本发明的一实施例中,这些第一引脚具有一第一上表面,而这些第二引脚具有一第二上表面。其中,第一上表面及第二上表面不共平面
在本发明的一实施例中,堆栈式芯片封装结构进一步包括一第一黏着层,配置于第一芯片与衬底之间。
在本发明的一实施例中,堆栈式芯片封装结构进一步包括一第二黏着层,配置于第二芯片与芯片封装体之间。
本发明的堆栈式芯片封装结构主要是将新型式QFN型式的封装与PIP(package-in-package)技术结合,以将一芯片封装体与另一芯片堆栈于一利用刻蚀金属板材而形成的导线架上。如此,即可形成将芯片堆栈于芯片封装体上的堆栈式芯片封装结构,以达到封装结构所需的微型化与高密度化的需求。
为让本发明的上述特征和优点能更明显易懂,下文特举较佳实施例,并配合所附图式,作详细说明如下。
附图说明
图1A~1E绘示为在日本专利申请案公开案第2005-317998号中所揭露的一种半导体装置的制作流程剖面示意图。
图2A绘示为根据本发明的第一实施例的一种堆栈式芯片封装结构的剖面示意图。
图2B绘示为根据本发明的第二实施例的一种堆栈式芯片封装结构的剖面示意图。
图3绘示为根据本发明的第三实施例的一种堆栈式芯片封装结构的剖面示意图。
图4A及4B绘示为其它型式的芯片封装结构的剖面示意图。
【主要元件符号说明】
10:芯片封装结构
11:半导体装置
12:线结合部分
16:导线
18:第二绝缘材料
20:黏着层
21:铜箔
22:第一图案化金属层
23:第二图案化金属层
24:刻蚀电阻层
100、100’、100”:堆栈式芯片封装结构
110、110’、110”:导线架
112、112’、112”:第一引脚
114、114’、114”:第二引脚
120、120’、120”:芯片封装体
122、122’、122”:衬底
124:第一芯片
124a’、124a”:第一芯片
124b’、124b”:第二芯片
124c”:第三芯片
126、126’、126”:第一封装胶体
128:焊球
130:第二芯片
140:第二封装胶体
150、152:打线导线
S:阶梯结构
S1、S1”:第一上表面
S2、S2”:第二上表面
具体实施方式
本发明所提出的堆栈式芯片封装结构可应用于已完成封装的芯片封装体与不同类型的芯片的整合,如一般常见的数字芯片、模拟芯片或存储器芯片等。为了涵盖上述变化,下文中是以第一芯片~第五芯片来指称不同类型的芯片。
图2A绘示为根据本发明的第一实施例的一种堆栈式芯片封装结构的剖面示意图。请参考图2A所示,此堆栈式芯片封装结构100主要包括一导线架110、一芯片封装体120、一第二芯片130以及一第二封装胶体140。以下将搭配图标说明堆栈式芯片封装结构100所包含的各元件以及元件之间的连接关系。
导线架110具有多个彼此电性绝缘的第一引脚112与第二引脚114,且这些第一引脚112与第二引脚114是由一金属板材,例如:铜箔,经过刻蚀等步骤制作而成。如图2A所示,第一引脚112具有一第一上表面S1,而第二引脚114具有一第二上表面S2,此第一上表面S1与第二上表面S2不共平面。
芯片封装体120可为一芯片尺寸封装(chip scale package)的封装体。芯片封装体120配置于第一引脚112的第一上表面S1上,且其包括一衬底122、一第一芯片124以及一第一封装胶体126。第一芯片124配置于衬底122上,且与衬底122电性连接。在本发明的一实施例中,第一芯片124可藉由一黏着层(图中未示)而固定于衬底122上。如图2A所示,在此实施例中,第一芯片124是透过多条打线导线与衬底122电性连接。然而,第一芯片124亦可透过多个焊球以覆晶接合的方式与衬底122电性连接,本发明对于第一芯片124与衬底122电性连接的方式不作任何限制。第一封装胶体126配置于衬底122上,且包覆第一芯片124与这些打线导线。而整个芯片封装体120是透过配置于衬底122的下表面上的多个焊球128与相对应的第一引脚112电性连接。
第二芯片130堆栈于芯片封装体120上,且与导线架110的第二引脚114电性连接。在此实施例中,第二芯片130是透过多条打线导线与第二引脚114电性连接。此外,第二芯片130亦可藉由一黏着层(图中未示)而固定于芯片封装体120上。第二封装胶体140配置于导线架110上,且填充于各第一引脚112与第二引脚114之间,以包覆芯片封装体120、这些焊球128与第二芯片130。此外,第一引脚112与第二引脚114会凸出于第二封装胶体140之外。
图2B绘示为根据本发明的第二实施例的一种堆栈式芯片封装结构的剖面示意图。请参考图2B所示,此堆栈式芯片封装结构100’大致上与第一实施例中的堆栈式芯片封装结构100雷同,而二者间主要不同之处在于:在堆栈式芯片封装结构100’中,芯片封装体120是以倒置的方式配置于导线架110’的第一引脚112’上。如此,第二芯片130可透过打线导线150与衬底122电性连接,而衬底122可再透过打线导线152与第二引脚114’电性连接。
图3绘示为根据本发明的第三实施例的一种堆栈式芯片封装结构的剖面示意图。请参考图3所示,此堆栈式芯片封装结构100”与图2A中所示的堆栈式芯片封装结构100略有不同,二者不同之处主要在于:在图2A的堆栈式芯片封装结构100中,其芯片封装体120是整个包覆在第二封装胶体140中,再透过衬底122上的焊球128与引脚112电性连接。而在图3所示的堆栈式芯片封装结构100”中,其导线架110”同样具有第一引脚112”与第二引脚114”两个部分。芯片封装体120是固定于导线架110”的第一引脚112”上,且芯片封装体120的下表面及焊球128会由导线架110”的下表面暴露出来,如此,其焊球128与第二引脚114”即可作为与其它电子元件电性连接的接点使用。
更进一步而言,如图3所示,第一引脚112”具有一第一上表面S1”,而第二引脚114”具有一第二上表面S2”,此第一上表面S1”与第二上表面S2”不共平面。此外,每个第一引脚112”分别具有一阶梯结构S,这些阶梯结构S会形成一容置凹槽,使芯片封装体120可固定于此容置凹槽中。
再者,在此实施例中,焊球128的底部与第二引脚114”的下表面为共平面。然而,焊球128的底部亦可略高于第二引脚114”的下表面,只要暴露出来的焊球128可与其它电子元件电性连接即可。此外,在第三实施例中,芯片封装体120的第一芯片124是透过打线接合技术与衬底122电性连接,然而,其亦可透过覆晶接合的方式与衬底122电性连接。本发明对于第一芯片124与衬底122电性连接的方式不作任何限制。
在以上实施例中,芯片封装体120是以将单一芯片堆栈于衬底上为例以作说明。然而,芯片封装体120亦可为由多个芯片堆栈而成的芯片封装结构。以下将举两个例子为例以作说明,然而,本发明对于芯片封装体120内的芯片数目及芯片间的电性连接方式不作任何限制。
图4A及4B绘示为其它型式的芯片封装结构的剖面示意图。首先,请参考图4A所示,芯片封装体120’具有一衬底122’、一第一芯片124a’、一第二芯片124b’以及一第一封装胶体126’。第一芯片124a’配置于衬底122’上,且透过覆晶接合的方式与衬底122’电性连接。第二芯片124b’堆栈于第一芯片124a’上,且透过打线接合技术与衬底122’电性连接。第一封装胶体126’配置于衬底122’上,且包覆第一芯片124’、第二芯片124b’与打线导线。请参考图4B所示,芯片封装体120”具有一衬底122”、一第一芯片124a”、一第二芯片124b”、一第三芯片124c”以及一第一封装胶体126”。第一芯片124a”与第二芯片124b”皆配置于衬底122”上,且透过打线接合的方式与衬底122”电性连接。第三芯片124c”横跨于第一芯片124a”与第二芯片124b”之间,且透过覆晶接合技术与第一芯片124a”以及第二芯片124b”电性连接。第一封装胶体126”配置于衬底122”上,且包覆第一芯片124a”、第二芯片124b”与第三芯片124c”。
综上所述,本发明的堆栈式芯片封装结构主要是将新型式QFN型式的封装与PIP(package-in-package)技术结合,以将一芯片封装体与另一芯片堆栈于一利用刻蚀金属板材而形成的导线架上,以达到封装结构所需的微型化与高密度化的需求,此外,引脚不共平面的设计亦可以减少堆栈式芯片封装结构其整体的高度,且减少第二芯片的打线距离。
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视权利要求所界定的范围为准。
Claims (18)
1.一种堆栈式芯片封装结构,其特征在于,包括:
一导线架,具有多个彼此电性绝缘的第一引脚及第二引脚,该多个第一引脚具有一第一上表面,该多个第二引脚具有一第二上表面,其中该第一上表面及该第二上表面不共平面;
一芯片封装体,配置于该多个第一引脚的该第一上表面上,该芯片封装体包括:
一衬底,与该多个第一引脚电性连接;
一第一芯片,配置于该衬底上,且与该衬底电性连接;以及
一第一封装胶体,配置于该衬底上,且包覆该第一芯片;
一第二芯片,堆栈于该芯片封装体上,且与该多个第二引脚电性连接;以及
一第二封装胶体,配置于该导线架上,且填充于各该第一及第二引脚之间,以包覆该芯片封装体与该第二芯片,其中该多个第一引脚与该多个第二引脚凸出于该第二封装胶体外。
2.根据权利要求1所述的堆栈式芯片封装结构,其特征在于,其中该第一芯片是透过多条打线导线或多个焊球与该衬底电性连接。
3.根据权利要求1所述的堆栈式芯片封装结构,其特征在于,其中该芯片封装体进一步包括一第三芯片,该第三芯片堆栈于该第一芯片上,且与该衬底电性连接。
4.根据权利要求1所述的堆栈式芯片封装结构,其特征在于,其中该芯片封装体进一步包括一第四芯片以及一第五芯片,该第四芯片配置于该衬底上,且与该衬底电性连接,而该第五芯片横跨于该第一芯片与该第四芯片之间,且该第五芯片与该第一芯片及该第四芯片电性连接。
5.根据权利要求1所述的堆栈式芯片封装结构,其特征在于,其中该衬底是透过多个焊球与该多个第一引脚电性连接。
6.一种堆栈式芯片封装结构,其特征在于,包括:一导线架,具有多个彼此电性绝缘的第一引脚及第二引脚;
一芯片封装体,固定于该导线架的该多个第一引脚上,该芯片封装体包括:
一衬底,具有一第一表面以及与其相对的一第二表面,其中该衬底包括多个配置于该第二表面上的焊球,且该多个焊球由该导线架中暴露出来;
一第一芯片,配置于该衬底上,且与该衬底电性连接;以及
一第一封装胶体,配置于该衬底上,且包覆该第一芯片;
一第二芯片,堆栈于该芯片封装体上,且与该多个第二引脚电性连接;以及
一第二封装胶体,配置于该导线架上,且填充于该多个第一引脚与该多个第二引脚之间,以包覆该第一封装胶体与该第二芯片,且该第二封装胶体暴露出该多个焊球,其中该多个第一引脚与该多个第二引脚凸出于该第二封装胶体外。
7.根据权利要求6所述的堆栈式芯片封装结构,其特征在于,其中该第一芯片是透过多条打线导线或多个焊球与该衬底电性连接。
8.根据权利要求6所述的堆栈式芯片封装结构,其特征在于,其中该芯片封装体进一步包括一第三芯片,该第三芯片堆栈于该第一芯片上,且与该衬底电性连接。
9.根据权利要求6所述的堆栈式芯片封装结构,其特征在于,其中该芯片封装体进一步包括一第四芯片以及一第五芯片,该第四芯片配置于该衬底上,且与该衬底电性连接,而该第五芯片横跨于该第一芯片与该第四芯片之间,且该第五芯片与该第一芯片及该第四芯片电性连接。
10.根据权利要求6所述的堆栈式芯片封装结构,其特征在于,其中该第二芯片是透过多条打线导线与该多个第二引脚电性连接。
11.根据权利要求6所述的堆栈式芯片封装结构,其特征在于,其中该多个第一引脚与该多个第二引脚凸出于该第二封装胶体外。
12.根据权利要求6所述的堆栈式芯片封装结构,其特征在于,其中该多个第一引脚分别具有一阶梯结构,该多个阶梯结构形成一容置凹槽,使该芯片封装体固定于该容置凹槽中。
13.根据权利要求6所述的堆栈式芯片封装结构,其特征在于,其中该多个第一引脚具有一第一上表面,该多个第二引脚具有一第二上表面,其中该第一上表面及该第二上表面不共平面。
14.一种堆栈式芯片封装结构,其特征在于,包括:
一导线架,具有多个彼此电性绝缘的第一引脚及第二引脚,该多个第一引脚具有一第一上表面,该多个第二引脚具有一第二上表面,其中该第一上表面及该第二上表面不共平面;
一芯片封装体,以倒置的方式配置于该多个第一引脚的该第一上表面上,该芯片封装体包括:
一衬底,透过多条打线导线与该多个第二引脚电性连接;
一第一芯片,配置于该衬底上,并位于该衬底与该多个第一引脚之间,且与该衬底电性连接;以及
一第一封装胶体,配置于该衬底上,并位于该衬底与该多个第一引脚之间,且包覆该第一芯片;
一第二芯片,堆栈于该芯片封装体上,且与该多个第二引脚电性连接;以及
一第二封装胶体,配置于该导线架上,且填充于各该第一及第二引脚之间,以包覆该芯片封装体与该第二芯片,其中该多个第一引脚与该多个第二引脚凸出于该第二封装胶体外。
15.根据权利要求14所述的堆栈式芯片封装结构,其特征在于,其中该第二芯片是透过多条打线导线与该衬底电性连接。
16.根据权利要求14所述的堆栈式芯片封装结构,其特征在于,其中该第一芯片是透过多条打线导线或多个焊球与该衬底电性连接。
17.根据权利要求14所述的堆栈式芯片封装结构,其特征在于,其中该芯片封装体进一步包括一第三芯片,该第三芯片堆栈于该第一芯片上,且与该衬底电性连接。
18.根据权利要求14所述的堆栈式芯片封装结构,其特征在于,其中该芯片封装体进一步包括一第四芯片以及一第五芯片,该第四芯片配置于该衬底上,且与该衬底电性连接,而该第五芯片横跨于该第一芯片与该第四芯片之间,且该第五芯片与该第一芯片及该第四芯片电性连接。
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