CN102867800B - 将功能芯片连接至封装件以形成层叠封装件 - Google Patents

将功能芯片连接至封装件以形成层叠封装件 Download PDF

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CN102867800B
CN102867800B CN201210199485.2A CN201210199485A CN102867800B CN 102867800 B CN102867800 B CN 102867800B CN 201210199485 A CN201210199485 A CN 201210199485A CN 102867800 B CN102867800 B CN 102867800B
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functional chip
substrate
trace
chip
functional
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CN102867800A (zh
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蔡佩君
吴胜郁
萧景文
郭庭豪
陈承先
刘重希
李建勋
李明机
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开一种层叠封装件(PoP)，其包括：基板，具有多条基板迹线；第一功能芯片，在基板的顶部上，通过多个迹线上接合连接件连接至基板；以及第二功能芯片，在第一功能芯片的顶部上，直接连接至基板。另一层叠封装件(PoP)包括：基板，具有多条基板迹线；第一功能芯片，在基板的顶部上，通过形成在连接至焊料块的SMD接合焊盘上的多个焊接掩模限定(SMD)连接件连接至基板；以及第二功能芯片，在第一功能芯片的顶部上，通过多个迹线上接合连接件直接连接至基板。

Description

将功能芯片连接至封装件以形成层叠封装件
技术领域
本发明涉及集成电路封装技术领域。
背景技术
电子设备可以分为由设备(诸如，集成电路(IC)芯片、封装件、印刷电路板(PCB)和系统)构成的简单层级。封装是电子设备(诸如，计算机芯片)和PCB之间的界面。设备由半导体材料(诸如，硅)制成。集成电路使用引线接合(WB)、带式自动焊接(TAB)、或倒装芯片(FC)凸块组装技术，被组装成封装(诸如，四边形扁平封装(QFP)、引脚栅格阵列(pingridarray，PGA)、球栅阵列(ballgridarray,，BGA))中。然后，被封装器件直接附着至印刷线路板或者另一类型的基板，其被限定为第二级封装。
球栅阵列(BGA)封装技术是先进的半导体封装技术，其特征在于，半导体芯片被装配在基板的前表面上，并且诸如焊球的多个导电元件以矩阵阵列，通常称为球栅阵列，被布置在基板的后表面上。球栅阵列允许半导体封装被粘合并且电连接至外部PCB或其他电子器件。可以在存储器(诸如，动态随机存取存储器和其他)中采用BGA封装。
基本的倒装芯片(FC)封装技术包括IC、互连系统、和基板。功能芯片通过多个焊料块连接至基板，其中，焊料块形成芯片和基板之间的冶金互连件。功能芯片、焊料块、以及基板形成倒装芯片封装。而且，多个球形成球栅阵列(BGA)。
引线接合可以用于进行从芯片组件(诸如，芯片电阻器或芯片电容器)到基板的电连接。两个功能芯片被堆叠在多个基板层的顶部上。芯片通过多条结合金线连接至基板。也可以使用其他形式的引线，诸如，铝线。功能芯片、金线、以及基板形成引线接合(WB)封装。
层叠封装(PoP)是集成电路封装技术，允许垂直结合离散逻辑和存储器球栅阵列(BGA)封装。两个或更多封装通过标准界面被安装在另一个的顶部上(即，堆叠)，以在它们之间路由信号。这允许例如在移动电话/PDA市场的更高密度。
标准POP结构基于通过引线接合或倒装芯片连接至基板以形成封装的堆叠芯片。由于引线接合连接和焊料块桥，导致这种PoP结构具有大封装尺寸。而且，由于引线接合连接，导致封装机械强度很弱。
发明内容
本发明提供一种层叠封装件(PoP)，包括：基板，具有多条基板迹线；第一功能芯片，在所述基板的顶部上，通过多个迹线上接合连接件连接至所述基板；以及第二功能芯片，在所述第一功能芯片的顶部上，直接连接至所述基板。
优选地，所述第二功能芯片通过多个迹线上接合连接件直接连接至所述基板。
优选地，所述第一功能芯片和所述基板之间的所述多个迹线上接合连接件包括多个连接件，每个连接件均在不进行预焊接的情况下在位于基板迹线上的Cu柱上通过焊料块形成。
优选地，所述Cu柱可以是熔化温度高于300℃的其他金属。
优选地，所述第二功能芯片通过连接至焊料块的多个焊接掩模限定(SMD)接合焊盘直接连接至所述基板。
优选地，所述第一功能芯片和所述第二功能芯片用于不同功能。
优选地，所述多条基板迹线可以由金属饰面覆盖，诸如涂敷在多条基板迹线上的有机薄膜层或Ni/Pd/Au的混和材料。
优选地，所述第二功能芯片比所述第一功能芯片具有更大的尺寸，使得所述第二功能芯片覆盖所述第一功能芯片的整个表面。
优选地，该层叠封装件进一步包括：中间环氧层，在所述第一功能芯片和所述第二功能芯片中间，连接至两个功能芯片。
优选地，该层叠封装件进一步包括：第三功能芯片，在所述第一功能芯片的顶部上，直接连接至所述基板。
根据本发明的另一方面，提供一种层叠封装件(PoP)，包括：基板，具有多条基板迹线；第一功能芯片，在所述基板的顶部上，通过在连接至焊料块的SMD接合焊盘上形成的多个焊接掩模限定(SMD)连接件连接至所述基板；以及第二功能芯片，在所述第一功能芯片的顶部上，通过多个迹线上接合连接件直接连接至所述基板。
优选地，所述第一功能芯片和所述基板之间的所述多个SMD连接件具有用于底部填充的化合物，以填充所述第一功能芯片、SMD连接件的焊料块、以及所述基板之间的空间。
优选地，所述第二功能芯片和所述基板之间的所述多个迹线上接合连接件包括：多个连接件，在不进行预焊接的情况下在位于基板迹线上的Cu柱上通过焊料块形成。
优选地，所述Cu柱可以是熔化温度高于300℃的其他金属。
优选地，所述第一功能芯片和所述第二功能芯片用于不同功能。
优选地，所述第二功能芯片具有比所述第一功能芯片更大的尺寸，使得所述第二功能芯片覆盖所述第一功能芯片的整个表面。
优选地，该层叠封装件进一步包括：中间环氧层，在所述第一功能芯片和所述第二功能芯片中间，所述中间环氧层连接至两个功能芯片。
优选地，该层叠封装件进一步包括：第三功能芯片，在所述第一功能芯片的顶部上，通过多个迹线上接合连接件直接连接至所述基板。
根据本发明的再一方面，提供一种形成层叠封装件(PoP)的方法，包括：通过多个迹线上接合连接件将在具有多条基板迹线的基板的顶部上的第一功能芯片连接至所述基板；将第二功能芯片放在所述第一功能芯片的顶部上；以及将所述第二功能芯片直接连接至所述基板。
优选地，直接连接所述第二功能芯片包括：通过多个迹线上接合连接件或通过多个SMD连接件连接至所述基板。
附图说明
为了更完整地理解本发明及其优点，现在结合附图对以下说明作出参考，其中：
图1(a)是底部迹线上板(BOT，board-on-trace)封装的顶部上的功能芯片的示意性实施例的示意图；
图1(b)是底部迹线上接合(BOT，bond-on-trace)封装的示意性实施例的示意图；图1(c)是迹线上接合(BOT)连接的示意性实施例的示意图；
图1(d)-(g)是在具有不同连接和中间层的多个位置中的BOT封装的顶部上的一个或多个功能芯片的示意性实施例的示意图；以及
图2(a)-(e)是在具有到基板和中间层的BOT连接的多个位置中的焊接掩模限定(SMD)封装的顶部上的一个或多个功能芯片的示意性实施例的示意图。
附图、图表和示意图是示意性的并且不是限制性的，而是本发明的实施例的实例，被简化用于解释目的，并且不按比例绘制。
具体实施方式
本典型实施例的制造和形成在以下详细地论述。然而，应该想到，本发明的实施例提供可以在多种特定上下文中具体化的多种可应用发明思想。所论述的特定实施例仅说明制造和使用本发明的特定方式，并且不限制本发明的范围。
将关于特定上下文中的典型实施例(即，迹线上接合封装的顶部上的一个或多个功能芯片及其形成方法)描述本发明。
图1(a)是底部迹线上板(BOT)封装的顶部上的功能芯片的示意性实施例的示意图。基板205具有在基板205的顶表面处由Cu制成的多条基板迹线203。可以存在多层基板205。图1(a)中示出的两层基板仅用于示意性目的，并且不是限制性的。基板205下面的多个球206形成球栅阵列(BGA)。第一功能芯片2011放在基板205的顶部上，并且通过多个迹线上接合(BOT)连接件207连接至基板。BOT连接件的详情在图1(c)中示出。第一功能芯片2011和基板205之间的空间由化合物填充，以填充芯片2011之间的空间。BOT连接件207和基板205形成封装体204。功能芯片2011、具有基板迹线203的基板205、以及多个BOT连接件207形成底部BOT封装210。
通过将第二功能芯片放在BOT封装210的第一功能芯片2011的顶部上，将第二功能芯片2012进一步放在底部BOT封装210的顶部上。从而，第二功能芯片2012不需要其自己的封装基板，而是其与底部封装BOT封装210共享基板。而且，第一功能芯片和第二功能芯片可以具有不同功能，例如，存储芯片，诸如，动态随机存取存储器芯片(DRAM)、或控制芯片等。第二功能芯片2012具有与第一功能芯片2011直接重叠的部分，并且其具有不在2011上面的第二部分，使得第二部分可以直接连接至基板205，如通过图1(a)中的207BOT连接所示，或者通过其他方式将功能芯片2012直接连接至基板205。该示意性布置结合与基板直接连接并且放在BOT底部封装210的顶部上的功能芯片2012。顶层功能芯片2012可以是不为封装形式的一个或多个功能芯片(在图1(g)中随后示出)。这种布置的优点在于以最小封装尺寸、低成本将多功能芯片构建到一起，增加总封装机械强度，并且可伸缩用于具有高支座(stand-off)的精细凸块间距。除了迹线的数量之外，功能芯片的尺寸、以及相对位置、以及BOT连接的数量仅用于示意性目的，并且不是限制性的。本领域技术人员将容易地认识到，存在多种其他改变。
图1(b)是形成图1(a)的结构的一部分的底部迹线上接合(BOT)封装210的示意性实施例的详细示意图。BOT封装210包括基板205、基板205的表面的顶部上的多条基板迹线203，其中，迹线连接至Cu柱凸块202(图1(a))，其进一步连接至功能芯片2011。第一功能芯片2011和基板205之间的空间被填充有化合物，以填充芯片2011之间的空间。BOT连接207和基板205形成封装体204。以上所有组件205、203、202、2011、207和204形成BOT封装210。
图1(c)是迹线上接合(BOT)连接的示意性实施例的示意图。基板205的表面的顶部上的迹线203连接至Cu柱凸块202，其进一步连接至功能芯片201。Cu柱凸块通过与焊料块2022连接的Cu柱2021形成。简而言之，BOT连接由Cu柱上的焊料块构成。图1(c)中所示的结构仅用于示意性目的，并且不是限制性的。可以想到附加实施例，例如，Cu柱可以是熔化温度高于300℃的其他金属。而且，多条基板迹线可以通过金属饰面覆盖，诸如，涂覆在基板迹线上的有机薄膜层或诸如Ni/Pd/Au的混和材料。
图1(a)中的第二功能芯片2012可以通过图1(a)所示的BOT连接直接连接至基板205。而且，第二功能芯片2012可以通过连接至焊料块的焊接掩模限定(SMD)接合焊盘直接连接至基板205，如图1(d)所示。多个SMD连接件如图1(d)所示，其中，SMD连接件208包括连接至在基板205的表面的顶部上的SMD焊盘2082的焊料块2081。基板中的焊接掩模限定焊盘通常对基板迹线进行预焊接，以改善连接。
图1(e)是底部迹线上板(BOT)封装210的顶部上的第二功能芯片2012的示意性实施例的示意图。第二功能芯片2012通过BOT连接207直接连接至底部BOT封装的基板。而且，第二功能芯片2012具有比第一功能芯片2011更大的尺寸，使得第二功能芯片2012覆盖第一功能芯片2011的整个表面，并且第二功能芯片2012从延伸超过所覆盖的第一功能芯片2011的两个或更多侧直接连接。图1(e)中所示的BOT连接的数量仅用于示意性目的，并且不是限制性的。可以存在图1(e)中所示的两个或三个BOT连接。而且，第二功能芯片2012与基板205之间的直接连接可以是图1(d)中所示的SMD类型的，而不是图1(e)中所示的BOT连接。
图1(f)是底部迹线上板(BOT)封装210的顶部上的第二功能芯片2012的示意性实施例的示意图，进一步包括第一功能芯片2011和第二功能芯片2012之间的中间环氧层209，其连接至两个功能芯片。在此示出的环氧层209仅用于示意性目的，并且不是限制性的。环氧层209可以被进一步应用至图1(a)、图1(c)中所示的其他结构或多种其他变性中。其他粘合层也可以代替环氧层使用。
图1(g)是底部迹线上板(BOT)封装210的顶部上的第二功能芯片2012的示意性实施例的示意图，进一步包括在第一功能芯片2011的顶部上的第三功能芯片2013。第三功能芯片2013还直接连接至基板。图1(g)示出第三功能芯片2013通过多个BOT连接直接连接至基板205。而且，SMD连接件还可以用于将第三功能芯片2013或第二功能芯片2012连接至基板205。而且，可以分别在第一功能芯片、和第二功能芯片、以及第三功能芯片之间存在环氧中间层(未示出)。本领域技术人员将容易地认识到，可以存在多种其他改变。
多于两个功能芯片可以通过将多个功能芯片放在第一功能芯片2011的顶部上并且将多个功能芯片直接连接至基板(未示出)添加在底部BOT封装210的顶部上。本领域技术人员将容易地认识到，存在多种其他改变。
对于图2(a)-(e)中所示的所有示意性实施例，底部封装是BOT封装，其中，第一功能芯片通过多个BOT连接连接至基板。而且，其他连接可以用于形成底部封装，例如，多个SMD连接件可以用于形成将第一功能芯片连接至基板的底部封装。
图2(a)是在底部SMD封装的顶部上的功能芯片的示意性实施例的示意图。图2(a)-图2(e)中所示的实施例都具有底部SMD封装，与图1(a)-图1(g)中所示的实施例相比，所有都具有BOT底部封装。基板205具有在基板205的顶面处由Cu制成的多条基板迹线203。可以存在多层基板205(未示出)。第一功能芯片2011被放在基板205的顶部上，并且通过多个SMD连接件208连接至基板。SMD连接件的详情在图1(d)中示出，其中，SMD连接件包括连接至焊料块2081的在基板的顶部上的SMD焊盘2082。第一功能芯片2011和基板205之间的空间被填充有化合物，以填充该空间。SMD连接件208和基板205形成封装体204。功能芯片2011、基板205与多个SMD连接件208一起形成底部SMD封装211。
通过将第二芯片2012放在SMD封装211的第一功能芯片2011的顶部上，第二功能芯片2012被进一步放在底部SMD封装的顶部上。从而，第二功能芯片2012不需要其自己的封装基板，而是其与底部封装SMD封装211共享基板。而且，第一功能芯片和第二功能芯片可以具有不同功能，例如，存储芯片(诸如，动态随机存取存储器芯片(DRAM))或控制芯片等。第二功能芯片2012具有与第一功能芯片2011直接重叠的部分，并且其具有不在2011之上的第二部分，使得第二部分可以直接连接至基板205，如通过图2(a)中的207BOT连接所示。当底部封装211是SMD封装时，第二功能芯片2012通过多个BOT连接直接连接至基板205，该BOT连接包括在不进行预焊接的情况下在位于基板迹线上的Cu柱上通过焊料块形成的多个连接。而且，Cu柱可以是熔化温度高于300℃的其他金属。
该示意性布置结合与基板直接连接的功能芯片2012并且其位于SMD底部封装211的顶部上。顶层功能芯片2012可以是一个或多个功能芯片(随后在图2(d)中示出)，并且不是封装形式。这种布置的优点在于，以最小封装尺寸、低成本将多功能芯片构建在一起，增加总封装机械强度，并且可伸缩用于具有高支座的精细凸块间距。除了基板迹线的数量之外，功能芯片的尺寸及其相对位置、以及SMD和BOT连接的数量仅用于示意性目的，并且不是限制性的。本领域技术人员将容易地认识到，存在多种其他改变。
图2(b)是底部SMD封装211的顶部上的第二功能芯片2012的示意性实施例的示意图。第二功能芯片2012通过BOT连接207直接连接至底部SMD封装的基板。而且，第二功能芯片2012具有比第一功能芯片2011更大的尺寸，使得第二功能芯片2012覆盖第一功能芯片2011的整个表面，并且第二功能芯片2012从延伸超过所覆盖的第一功能芯片2011的所有侧面直接连接。图2(b)中所示的BOT连接的数量仅用于示意性目的，并且不是限制性的。可以存在多于两个或三个图2(b)中所示的BOT连接。
图2(c)是底部SMD封装211的顶部上的第二功能芯片2012的示意性实施例的示意图，进一步包括在第一功能芯片2011和第二功能芯片2012中间的中间环氧层209，连接至两个功能芯片。在此示出的环氧层209仅用于示意性目的，并且不是限制性的。环氧层209可以进一步应用至图2(a)或图2(d)中所示的其他结构，或者多种其他变型中。
图2(d)是底部SMD封装211的顶部上的第二功能芯片2012的示意性实施例的示意图，进一步包括第一功能芯片2011的顶部上的第三功能芯片2013。第三功能芯片2013还直接连接至基板。图2(d)示出第三功能芯片2013通过多个BOT连接直接连接至基板205。而且，在第一功能芯片、以及第二和第三功能芯片的层之间可以存在环氧中间层，如图2(e)所示。本领域技术人员将认识到，可以存在多种其他改变。
通过将多个功能芯片放在第一功能芯片2011的顶部上并且将多个功能芯片直接连接至基板(未示出)，可以将两个以上的功能芯片添加在底部SMD封装211的顶部上。本领域技术人员将认识到，可以存在多种其他改变。
一种形成层叠封装件(PoP)的方法包括以下步骤：通过多个迹线上接合连接件，将在具有多条基板迹线的基板的顶部上的第一功能芯片连接至基板；将第二功能芯片放在第一功能芯片的顶部上；并且将第二功能芯片直接连接至基板。
一种形成层叠封装件(PoP)的方法包括以下步骤：通过形成在连接至焊料块的SMD接合焊盘上的多个焊接掩模限定(SMD)连接，将在具有多条基板迹线的基板的顶部上的第一功能芯片连接至基板；将第二功能芯片放在第一功能芯片上；以及通过多个迹线上接合连接件将第二功能芯片直接连接至基板。

Claims (21)

1.一种层叠封装件PoP，包括：
基板；
位于所述基板表面的多条基板迹线；
第一功能芯片，在所述基板的顶部上，通过多个迹线上接合连接件连接至所述基板，其中，所述多个迹线上接合连接件包括多个焊料块；以及
第二功能芯片，在所述第一功能芯片的顶部上，直接连接至所述基板，
其中，所述第二功能芯片具有与所述第一功能芯片直接重叠的部分并且还具有不在所述第一功能芯片上面的第二部分。
2.根据权利要求1所述的PoP，其中，所述第二功能芯片通过多个迹线上接合连接件直接连接至所述基板。
3.根据权利要求2所述的PoP，其中，所述第一功能芯片和所述基板之间的所述多个迹线上接合连接件包括多个连接件，每个连接件均在不进行预焊接的情况下在位于基板迹线上的Cu柱上通过焊料块形成。
4.根据权利要求3所述的PoP，其中，所述Cu柱可以是熔化温度高于300℃的其他金属。
5.根据权利要求1所述的PoP，其中，所述第二功能芯片通过连接至焊料块的多个焊接掩模限定SMD接合焊盘直接连接至所述基板。
6.根据权利要求1所述的PoP，其中，所述第一功能芯片和所述第二功能芯片用于不同功能。
7.根据权利要求1所述的PoP，其中，所述多条基板迹线由金属饰面覆盖。
8.根据权利要求7所述的PoP，其中，所述金属饰面的材料包括有机薄膜层或Ni/Pd/Au的混和材料。
9.根据权利要求1所述的PoP，其中，所述第二功能芯片比所述第一功能芯片具有更大的尺寸，使得所述第二功能芯片覆盖所述第一功能芯片的整个表面。
10.根据权利要求1所述的PoP，进一步包括：中间环氧层，在所述第一功能芯片和所述第二功能芯片中间，连接至两个功能芯片。
11.根据权利要求1所述的PoP，进一步包括：第三功能芯片，在所述第一功能芯片的顶部上，直接连接至所述基板。
12.一种层叠封装件PoP，包括：
基板；
位于所述基板表面的多条基板迹线；
第一功能芯片，在所述基板的顶部上，通过在连接至焊料块的焊接掩模限定SMD接合焊盘上形成的多个SMD连接件连接至所述基板；以及
第二功能芯片，在所述第一功能芯片的顶部上，通过多个迹线上接合连接件直接连接至所述基板，其中，所述多个迹线上接合连接件包括多个焊料块，
其中，所述第二功能芯片具有与所述第一功能芯片直接重叠的部分并且还具有不在所述第一功能芯片上面的第二部分。
13.根据权利要求12所述的PoP，其中，所述第一功能芯片和所述基板之间的所述多个SMD连接件具有用于底部填充的化合物，以填充所述第一功能芯片、SMD连接件的焊料块、以及所述基板之间的空间。
14.根据权利要求12所述的PoP，其中，所述第二功能芯片和所述基板之间的所述多个迹线上接合连接件包括：多个连接件，在不进行预焊接的情况下在位于基板迹线上的Cu柱上通过焊料块形成。
15.根据权利要求14所述的PoP，其中，所述Cu柱可以是熔化温度高于300℃的其他金属。
16.根据权利要求12所述的PoP，其中，所述第一功能芯片和所述第二功能芯片用于不同功能。
17.根据权利要求12所述的PoP，其中，所述第二功能芯片具有比所述第一功能芯片更大的尺寸，使得所述第二功能芯片覆盖所述第一功能芯片的整个表面。
18.根据权利要求12所述的PoP，进一步包括：中间环氧层，在所述第一功能芯片和所述第二功能芯片中间，所述中间环氧层连接至两个功能芯片。
19.根据权利要求12所述的PoP，进一步包括：第三功能芯片，在所述第一功能芯片的顶部上，通过多个迹线上接合连接件直接连接至所述基板。
20.一种形成层叠封装件PoP的方法，包括：
通过多个迹线上接合连接件将在基板的顶部上的第一功能芯片连接至所述基板，其中，所述多个迹线上接合连接件包括多个焊料块，以及所述基板的表面包括多条基板迹线；
将第二功能芯片放在所述第一功能芯片的顶部上；以及
将所述第二功能芯片直接连接至所述基板，
其中，所述第二功能芯片具有与所述第一功能芯片直接重叠的部分并且还具有不在所述第一功能芯片上面的第二部分。
21.根据权利要求20所述的方法，其中，直接连接所述第二功能芯片包括：通过多个迹线上接合连接件或通过多个SMD连接件连接至所述基板。
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