JP2009129975A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2009129975A JP2009129975A JP2007300687A JP2007300687A JP2009129975A JP 2009129975 A JP2009129975 A JP 2009129975A JP 2007300687 A JP2007300687 A JP 2007300687A JP 2007300687 A JP2007300687 A JP 2007300687A JP 2009129975 A JP2009129975 A JP 2009129975A
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- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Abstract
【解決手段】本発明は、上面に凹部12を有する中継基板10と、中継基板10の凹部12内に搭載された半導体チップ20と、半導体チップ20上方に、中継基板10と接続端子28を介し搭載された内蔵半導体装置50と、中継基板10と内蔵半導体装置50との間に充填し半導体チップ20を封止する第1樹脂部26と、を具備する半導体装置およびその製造方法である。
【選択図】図1
Description
12 凹部
20 半導体チップ
26 第1樹脂部
28 半田端子
30 中継基板
40 半導体チップ
50 内蔵半導体装置
56 第2樹脂部
58 ダム部
Claims (10)
- 上面に凹部を有する中継基板と、
前記中継基板の前記凹部内に搭載された半導体チップと、
前記半導体チップ上方に、前記中継基板と接続端子を介し搭載された内蔵半導体装置と、
前記中継基板と前記内蔵半導体装置との間に充填し前記半導体チップを封止する第1樹脂部と、を具備することを特徴とする半導体装置。 - 前記第1樹脂部および前記内蔵半導体装置を封止する第2樹脂部を具備することを特徴とする請求項1記載の半導体装置。
- 前記第1樹脂部と前記第2樹脂部とは同じ樹脂からなることを特徴とする請求項2記載の半導体装置。
- 前記第1樹脂部はフィラーフリーであり、前記第2樹脂部はフィラーを有することを特徴とする請求項2記載の半導体装置。
- 前記内蔵半導体装置の上面は、前記第2樹脂部の上面から露出していることを特徴とする請求項2から4のいずれか一項記載の半導体装置。
- 前記中継基板上の周辺部に前記内蔵半導体装置および前記半導体チップを囲むように設けられたダム部を具備し、
前記第2樹脂部は、ダム部内に設けられていることを特徴とする請求項3記載の半導体装置。 - 上面に凹部を有する中継基板の前記凹部内に半導体チップを搭載する工程と、
前記半導体チップの上方に、前記中継基板と接続端子を用い内蔵半導体装置を搭載する工程と、
前記中継基板と前記内蔵半導体との間に充填するように、前記半導体チップを封止する第1封止部を形成する工程と、を有することを特徴とする半導体装置の製造方法。 - 第1樹脂部および前記内蔵半導体装置を封止する第2樹脂部を形成する工程を有することを特徴とする請求項7記載の半導体装置。
- 前記第1樹脂部を形成する工程と前記第2樹脂部を形成する工程とは、同じ樹脂を用い同時に実行されることを特徴とする請求項8記載の半導体装置の製造方法。
- 前記第1樹脂部を形成する工程を行った後、前記第2樹脂部を形成する工程を行うことを特徴とする請求項8記載の半導体装置の製造方法。
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JP2007300687A JP2009129975A (ja) | 2007-11-20 | 2007-11-20 | 半導体装置及びその製造方法 |
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JP2007300687A JP2009129975A (ja) | 2007-11-20 | 2007-11-20 | 半導体装置及びその製造方法 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011049560A (ja) * | 2009-08-26 | 2011-03-10 | Taiwan Semiconductor Manufacturing Co Ltd | 集積回路構造および集積回路構造を形成する方法 |
Citations (7)
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JP2000012770A (ja) * | 1998-06-18 | 2000-01-14 | Sony Corp | 半導体装置およびその製造方法 |
JP2005340451A (ja) * | 2004-05-26 | 2005-12-08 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2005340415A (ja) * | 2004-05-26 | 2005-12-08 | Sony Corp | 半導体パッケージ及びその製造方法 |
JP2006100663A (ja) * | 2004-09-30 | 2006-04-13 | Ricoh Co Ltd | 半導体装置実装体及びその製造方法 |
WO2006095852A1 (ja) * | 2005-03-10 | 2006-09-14 | Kyocera Corporation | 電子部品モジュール及びその製造方法 |
JP2007012748A (ja) * | 2005-06-29 | 2007-01-18 | Renesas Technology Corp | 積層型半導体装置およびその製造方法 |
JP2007281129A (ja) * | 2006-04-05 | 2007-10-25 | Toshiba Corp | 積層型半導体装置 |
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2007
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Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000012770A (ja) * | 1998-06-18 | 2000-01-14 | Sony Corp | 半導体装置およびその製造方法 |
JP2005340451A (ja) * | 2004-05-26 | 2005-12-08 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2005340415A (ja) * | 2004-05-26 | 2005-12-08 | Sony Corp | 半導体パッケージ及びその製造方法 |
JP2006100663A (ja) * | 2004-09-30 | 2006-04-13 | Ricoh Co Ltd | 半導体装置実装体及びその製造方法 |
WO2006095852A1 (ja) * | 2005-03-10 | 2006-09-14 | Kyocera Corporation | 電子部品モジュール及びその製造方法 |
JP2007012748A (ja) * | 2005-06-29 | 2007-01-18 | Renesas Technology Corp | 積層型半導体装置およびその製造方法 |
JP2007281129A (ja) * | 2006-04-05 | 2007-10-25 | Toshiba Corp | 積層型半導体装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011049560A (ja) * | 2009-08-26 | 2011-03-10 | Taiwan Semiconductor Manufacturing Co Ltd | 集積回路構造および集積回路構造を形成する方法 |
US8743561B2 (en) | 2009-08-26 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level molded structure for package assembly |
US9117939B2 (en) | 2009-08-26 | 2015-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming wafer-level molded structure for package assembly |
US9754917B2 (en) | 2009-08-26 | 2017-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming wafer-level molded structure for package assembly |
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