CN104253115B - 用于半导体封装中减小的管芯到管芯间隔的底部填充材料流控制 - Google Patents
用于半导体封装中减小的管芯到管芯间隔的底部填充材料流控制 Download PDFInfo
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- CN104253115B CN104253115B CN201410298336.0A CN201410298336A CN104253115B CN 104253115 B CN104253115 B CN 104253115B CN 201410298336 A CN201410298336 A CN 201410298336A CN 104253115 B CN104253115 B CN 104253115B
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Abstract
描述了用于半导体封装中的减小的管芯到管芯间隔的底部填充材料流控制和所得的半导体封装。在一示例中,半导体装置包括第一和第二半导体管芯,每个半导体管芯具有其上有集成电路的表面,所述集成电路通过多个导电接触耦合于公共半导体封装衬底的最上面金属化层的接触盘,该第一和第二板导体管芯分开一间隔。阻挡层结构位于第一半导体管芯和公共半导体封装衬底之间并且至少部分地在第一半导体管芯之下。底部填充材料层与第二半导体管芯接触并且与阻挡层结构接触,但是不与第一半导体管芯接触。
Description
技术领域
本发明的实施例涉及半导体封装领域,尤其是用于半导体封装中的减小的管芯到管芯间隔的底部填充(underfill)材料流控制以及所得到的半导体封装。
背景技术
如今的消费者电子市场频繁地要求需要非常复杂的电路的复杂功能。缩放到越来越小的例如晶体管之类的基本构建块已经使得能够随着渐进式的世代将甚至更复杂电路合并到单个管芯上。半导体封装被用于保护集成电路(IC)芯片或管芯,并且还用于向管芯提供去往外部电路的电接口。随着对更小的电子器件的要求增加,半导体封装被设计成更紧凑的,并且必须支持更大的电路密度。此外,对高性能器件的要求导致对经改善的半导体封装的需求,该经改善的半导体封装实现薄封装轮廓和与后续组装处理相兼容的低的总翘曲。
多年来已使用C4焊料球连接来提供半导体器件和衬底之间的倒装芯片互连。倒装芯片或受控塌陷芯片连接(C4)是一种用于半导体器件(诸如集成电路(IC)芯片、MEMS或组件)的安装类型,其利用焊料隆起而不是引线接合。焊料隆起沉积在位于衬底封装顶侧的C4盘上。为了将半导体器件安装到衬底上,将半导体器件翻转——有源侧向下地位于安装区域上。焊料隆起被用来将半导体器件直接连接到衬底。
处理倒装芯片类似于常规IC制造,但有几个附加的步骤。在制造过程接近结束时,将附接盘(attachment pad)金属化以使附接盘更容易被焊料接纳。这通常由若干处理组成。随后将小焊料点沉积在每个经金属化的盘上。随后正常地将芯片从晶片切开。为了将倒装芯片附接到电路中,将该芯片翻转以使焊料点向下到达底下的电子器件或电路板上的连接器上。随后将焊料重新熔化(通常使用超声或替换回流焊料工艺)以产生电连接。这也在芯片的电路系统和底下的安装之间留下了小空间。在大多数情况下,随后电绝缘的粘合剂被“底部填充”以提供更强的机械连接、提供热桥、以及确保焊料接头不会由于芯片和系统其他部分的不同加热而承压。然而,需要对用于在此种倒装芯片布置中底部填充的材料做出改进。
为了实现高性能的多芯片模块(MCM)和系统级封装(SiP),更新的封装以及管芯到管芯互连方法(诸如硅通孔(TSV)和硅插入件(silicon interposer))获得了来自设计者的许多关注。然而,对于这些更新的封装体系,还需要底部填充材料技术的更多改进。
附图说明
图1示出根据本发明的一实施例的半导体封装的横截面视图,该半导体封装具有连接管芯1(存储器)和管芯2(CPU/SoC)的嵌入式互连桥(EmIB)。
图2示出根据本发明的一实施例的共同封装(co-packaged)高性能计算(HPC)管芯和高带宽存储器(HBM)布局的封装布局的平面图。
图3示出根据本发明的一实施例的半导体封装的横截面视图,该半导体封装包括位于公共衬底上的存储器管芯和CPU/SoC管芯。
图4示出根据本发明的一实施例的半导体封装的横截面视图,该半导体封装包括位于公共衬底上的存储器管芯和CPU/SoC管芯。
图5是根据本发明的一实施例的被管芯到管芯(D2D)间隔分开的铜(Cu)平面和底部填充(UF)区域的示意布局。
图6是根据本发明的一实施例的被管芯到管芯(D2D)间隔分开的铜(Cu)平面和底部填充(UF)区域的示意布局。
图7示出根据本发明的一实施例的用于小填角(fillet)的管芯间的铜迹线的布局的示例性平面视图。
图8示出根据本发明的一实施例的图7的铜迹线的布局的一部分的图解性横截面视图。
图9是示出根据本发明的一实施例使用铜迹线/沟槽来限制环氧树脂填角的图像。
图10示出根据本发明的一实施例的用作多余环氧树脂的逃逸路径的铜迹线/沟槽的布局的平面图。
图11包括根据本发明的一实施例的展示逃逸沟槽概念的来自模拟结果的多个模拟图像。
图12包括根据本发明的一实施例的被管芯到管芯(D2D)间隔分开的油墨阻挡层和底部填充(UF)区域的示意布局。
图13A示出根据本发明的一实施例的半导体封装的横截面视图,该半导体封装包括与嵌入式互连桥(EmIB)耦合的多个管芯并且包括用于控制底部填充材料流的阻挡层。
图13B示出根据本发明的一实施例的半导体封装的横截面视图,该半导体封装包括与嵌入式互连桥(EmIB)耦合的多个管芯并且包括用于控制底部填充材料流的阻挡层。
图14示出根据本发明的一实施例的半导体封装的横截面视图,该半导体封装包括与插入件耦合的多个管芯并且包括用于控制底部填充材料流的阻挡层。
图15示出根据本发明的一实施例的3D集成电路封装的横截面视图,该3D集成电路封装具有贯通模制(through-mold)的第一级互连并且包括用于控制底部填充材料流的阻挡层。
图16示出根据本发明的一实施例的3D集成电路封装的横截面视图,该3D集成电路封装具有贯通模制的第一级互连并且包括用于控制底部填充材料流的阻挡层。
图17示出了根据本发明的一实施例的具有嵌入式层叠硅通孔管芯并且包括用于控制底部填充材料流的阻挡层的无芯衬底的横截面图。
图18是根据本发明实施例的计算机系统的示意图。
具体实施方式
描述了用于半导体封装中的减小的管芯到管芯间隔的底部填充材料流控制和所得的半导体封装。在以下的描述中,阐述了很多具体细节,诸如封装和互连架构,以提供对本发明实施例的透彻理解。将对本领域技术人员明显的是,没有这些具体细节也可实践本发明的实施例。在其它实例中,公知的特征——诸如具体的半导体制造工艺——不被详细描述以免不必要地混淆本发明各实施例。此外,要理解,附图中示出的各实施例是说明性表示并且不一定按比例绘出。
本文描述的一个或多个实施例涉及用于控制底部填充(UF)流以便减小基于嵌入式互连桥(EmIB)的半导体封装和产品的管芯到管芯(D2D)间隔的方法和工艺。各方面可包括毛细管型底部填充、基于EmIB的结构、基于硅插入件的结构、紧密的管芯到管芯间隔、以及具有紧密管芯到管芯距离规范的通用产品中的一者或多者。
为了提供上下文,正在针对具有高带宽存储器(HBM)的高性能计算(HPC)使用和/或评估嵌入式互连桥(EmIB)技术,在下面结合以下的图1和图2描述了其示例。一般而言,允许中央处理单元/片上系统(CPU/SoC)管芯和存储器管芯之间的小(例如,约100微米)管芯到管芯(D2D)间隔已被证明充满挑战性,下面结合图3描述了其示例。
图1示出根据本发明的一实施例的半导体封装100的横截面视图,该半导体封装具有连接管芯1(存储器)和管芯2(CPU/SoC)的嵌入式互连桥(EmIB)。参考图1,半导体封装100包括第一管芯102(例如,存储器管芯)和第二管芯104(例如,CPU或SoC管芯)。第一管芯102和第二管芯104分别通过第一管芯102和第二管芯104的凸块108和110、以及EmIB的接合盘(例如,通过热压接合(TCB))耦合于EmIB106。第一管芯102、第二管芯104、以及EmIB106与附加的路由层114被包括在一起,如图1中所示。附加路由层可以是简单的或复杂的,并且可以用于耦合到其他封装或者可形成有机封装或印刷电路板的部分或全部等。
图2示出根据本发明的一实施例的共同封装高性能计算(HPC)管芯和高带宽存储器(HBM)布局的封装布局200的平面图。参考图2,封装布局200包括公共衬底202。CPU/SoC管芯204连同8个存储器管芯206一起受衬底202支撑。多个EmIB208通过C4连接210将存储器管芯206桥接到CPU/SoC管芯204。管芯到管芯间隔212大致为100-200微米。应该理解,从由上至下视角看来,管芯204和206被置于C4连接210上方,C4连接210被置于EmIB208上方,EmIB208被包括在衬底202中。
图3示出根据本发明的一实施例的半导体封装300的横截面视图,该半导体封装包括位于公共衬底306上的存储器管芯302和CPU/SoC管芯304。参考图3,存储器管芯302和CPU/SoC管芯304之间的管芯到管芯(D2D)间隔308为约100-200微米。底部填充(UF)填角材料309被置于空隙308中。存储器管芯302的凸块310位于距存储器管芯302的边缘312约1毫米处。根据本发明的一实施例,所得的区域314可被用来放置经图案化的阻挡层材料,如下面结合图4更详细地描述的。此外,这种阻挡层材料(例如,铜(Cu)平面)中的槽可减小区域316中的环氧树脂填角宽度/排除区(keep out zone)。
更具体而言,一般性地参考图1-3,与HBM管芯相关联的高成本可能需要在存储器管芯附接之前测试CPU管芯。当前的CPU底部填充工艺得到的环氧树脂填角宽度能阻止存储器管芯附接距CPU管芯小于约200微米。涉及在CPU管芯侧壁或坝上使用阻挡层的初始评估尚未成功。此外,如果所有管芯均在底部填充之前被接合,则与填充所有管芯而不形成空隙相关的挑战可能出现。主要的风险看上去源自合并流前锋,还源自沿小的管芯到管芯距离的非常快的边缘流。
在通用方法中,根据本发明的一个或多个实施例,对于给定的底部填充(UF)环氧树脂材料和工艺条件,UF填角几何形状(例如,高度、宽度和延展)可通过在阻挡层(例如,使用铜平面)的帮助下控制多余环氧树脂的流动来调制,所述阻挡层被图案化(例如,具有槽)以便为环氧树脂材料提供沟道并且得到短填角宽度。在一个这样的实施例中,形成具有不同宽度和长度的诸如铜迹线或沟槽等阻挡层,并且取决于在没有阻挡层的情况下本应观察到的环氧树脂流前锋来设计阻挡层的位置和取向。可针对不同的管芯尺寸和所需的管芯间间隔来定制这些槽。在特定的替换实施例中,如果沿油墨阻挡层的长度制造槽和/或沟槽,可使其他阻挡层(诸如表面能量阻挡层)更有效。用于制造油墨阻挡层槽的适当方法包括衬底图案化和激光烧蚀。
更具体而言,根据本发明的一个或多个实施例,通过阻碍CPU管芯上的UF填角几何形状干扰存储器管芯的放置来实现100到200微米D2D间隔。UF延展/流注(bleed)不会扩展到存储器盘表面(例如,对于CPU管芯边缘的约1.1毫米的距离)。在特定实施例中,衬底表面上的CPU和存储器管芯上的细间距凸点之间的区域(例如,约1.3毫米)为在其中放置阻挡层材料的区域。
作为以上描述的一个示例,图4示出根据本发明的一实施例的半导体封装400的横截面视图,该半导体封装400包括位于公共衬底上的存储器管芯402和CPU/SoC管芯404。参考图4,EmIB结构405被包括在衬底406中并且耦合存储器管芯402和CPU/SoC管芯404。存储器管芯402和CPU/SoC管芯404之间的管芯到管芯(D2D)间隔408为约100-200微米。底部填充(UF)填角材料409被置于空隙408中。存储器管芯402的细间距凸块410位于距存储器管芯402的边缘412约1毫米处。根据本发明的一实施例,所得区域414包括位于其上的经图案化的阻挡层材料层418(例如,经图案化的铜层)。在一具体实施例中,如下面更详细地描述的,在阻挡层材料层418中形成的槽可用于减小环氧树脂条件宽度/排除区(KOZ),例如,在图4的区域A处。相应地,图4例示了控制CPU UF环氧树脂填角与存储器管芯边缘的接近度。所述控制可以通过阻碍CPU管芯上的UF填角几何形状干扰存储器管芯的放置(例如,在区域A处)来实现。
预计沿CPU管芯的边缘的UF环氧树脂流在到EmIB的细间距(例如,55或65微米)互连区域中更快,从而使该区域通常呈现更大的填角宽度。作为示例,图5是根据本发明的一实施例的被管芯到管芯(D2D)间隔506(例如,100-200微米)分开的铜(Cu)平面502和底部填充(UF)504区域的示意布局500。参考图5,Cu平面502具有形成于其中的槽508并且UF流具有图案510。图5的左侧示出阻挡层材料(例如,Cu平面)的放置。Cu平面502在两个相邻的管芯之间延伸,例如,沿着CPU管芯505的整个长度,并且还可能在相邻的存储器管芯的一部分之下。
应该理解,可调节槽长度和宽度以便最小化环氧树脂填角的高度和宽度,如图5中所示。而且,可在阻挡层(例如,铜平面)材料中形成除槽以外的图案。铜或其他阻挡层材料中的这些槽或者图案切口可允许控制沿管芯边缘的不同区域中的UF延展和/或填角形状或高度。在一个实施例中,这些槽或者图案是使用激光烧蚀制造的,以便减小底部填充排除区(KOZ)。应该理解,取决于具体应用,这些槽或者图案可被制造为具有不同的形状、尺寸和/或取向。
在一实施例中,铜平面的边缘担当对UF环氧树脂的阻挡层,并且此外,可在铜平面中制造槽以“流出”延伸到管芯区域之外的任何多余的环氧树脂材料。再次参考图5,UF分配方向由箭头512示出。在一特定实施例中,UF在EmIB550处的细间距互连区域中流得更多,如图5中所示。
在另一方面,在其中两个CPU管芯被置于公共衬底上方的情况下,阻挡层材料中的槽可取决于UF分配流的方向形成为人字形(chevron)图案和取向。作为示例,图6是根据本发明的一实施例的被管芯到管芯(D2D)间隔606(例如,100-200微米)分开的铜(Cu)平面602和底部填充(UF)604区域的示意布局600。参考图6,Cu平面602具有形成于其中的具有第一取向的第一多个槽608和具有不同的第二取向的第二多个槽609。该UF流具有图案610。图6的左侧示出阻挡层材料(例如,Cu平面)的放置。Cu平面602被两个CPU管芯605A和605B共享,并且还可能在相邻的存储器管芯的一部分下方。UF分配方向由箭头612和613示出。在一特定实施例中,UF在EmIB650处的细间距互连区域中流得更多,如图6中所示。在一特定实施例中,如图所示,在Cu平面中制造人字形槽(608和609)并将所述槽在UF环氧树脂流的相应方向612或613中取向。
再次参考图5和6,可使用紫外(UV)激光烧蚀工艺来在铜平面中形成诸如槽508、608和609等槽或者其他几何图案,所述紫外激光烧蚀工艺不损害底下的介电材料。在一示例性实施例中,合适的激光参数集合包括使用激光波长为约355纳米、功率为约18mJ、频率(例如,重复速率)为约32kHz、Galvonic速度为约210mm/s、激光点大小为约8微米、波束扩展为约10X(例如,对于约40微米的波束直径)的脉冲波UV激光烧蚀。在一个实施例中,执行激光烧蚀涉及将槽图案的DXF文件加载到激光系统,而振镜(galvo)引导激光束来仅烧蚀槽区域处的铜。
图7示出根据本发明的一实施例的用于小填角(fillet)的管芯间的铜迹线的布局700的示例性平面视图。参考图7,多个铜迹线702与被提供以避免起皱的一个或多个盘704、706、708、710耦合。CPU管芯712、第一存储器管芯714、以及第二存储器管芯716覆盖布局700。所示布局可允许两遍(two-pass)工艺流,其中在接合存储器管芯之前底部填充该CPU。在另一实施例中,该布局还允许以下工艺流程:其中只要每个管芯至少具有没有相邻管芯的一侧从而允许分配UF材料,则所有管芯在底部填充之前被接合。
图8示出根据本发明的一实施例的图7的铜迹线的布局的一部分的图解性横截面视图。参考图8,半导体封装800包括具有靠近凸块806的第一悬垂804的第一管芯802并且包括具有靠近凸块812的第二悬垂810的第二管芯808。第一和第二管芯被置于封装衬底814和介于中间的介电层816上方。在一个实施例中,介电层816是味之素(Aginomoto)构建膜(ABF)介电层。铜迹线818被置于介电层816上,在管芯802和808之间。在一个实施例中,如图所示,铜迹线818的特征具有约20微米的间隔。较窄的特征宽度为约20微米,而较宽的特征宽度为约50微米,如图所示。在一个实施例中,台阶式管芯尺寸在每一侧上比实际管芯尺寸大约25微米。应该理解,迹线之间的沟槽可以制造成有不同的宽度、高度和/或间隔。
图9是示出根据本发明的一实施例使用铜迹线/沟槽来限制环氧树脂填角的图像900。参考图像900,环氧树脂填角限于约60微米。该限制的范围足以允许100微米的管芯到管芯距离。也就是说,使用铜(Cu)迹线实现了小于100微米的排除区(KOZ)。
图10示出根据本发明的一实施例的用作多余环氧树脂的逃逸路径的铜迹线/沟槽的布局1000的平面图。参考图10,布局1000包括多个铜迹线1002(注意,所述迹线可替换地被视为在铜中形成的沟槽)。铜迹线1002提供在分配在位于布局1000的右侧上的管芯1004时多余环氧树脂的逃逸路径。在一个实施例中,确定迹线1002之间的间隔以使得毛细管压强(拉力)比管芯凸块区域1006更高。这导致多余环氧树脂被逃逸迹线吸走而远离管芯边缘,从而保持填角很小。再参考图7,在管芯间实现这些迹线。
图11包括根据本发明的一实施例的展示逃逸沟槽概念的来自模拟结果的多个模拟图像1100。参考模拟图像1100,在(A)处,环氧树脂1102被分配在管芯1104的右侧上。在图像(A)-(H)之后,环氧树脂1102被拉到管芯1104的C4区域1106之下。随着填角增长,该填角触及左侧的沟槽。该沟槽继续用更高的毛细管力拉取多余的环氧树脂,直到填角在左侧断裂为止。这留下比管芯和沟槽之间的距离更小的填角宽度。
在另一实施例中,不使用铜,而是使用油墨阻挡层。在一个这样的实施例中,油墨阻挡层所形成的图案可大于约150微米宽。相反,宽度处于或小于150微米的特征可能在环氧树脂流工艺期间破裂。在一个实施例中,更宽的油墨阻挡层(例如,宽度大于150微米的特征)与在金属阻挡层材料(例如,铜阻挡层中的)一起用于提供环氧树脂流的附加包含。在另一实施例中,在环氧树脂流更大的区域中用相对更宽的空腔图案化槽(例如,其中有细间距互连的区域)。
作为使用油墨阻挡层的实现的示例,图12包括根据本发明的一实施例的被管芯到管芯(D2D)间隔1206(例如,100-200微米)分开的油墨阻挡层1202和底部填充(UF)1204区域的示意布局1200。在细凸块结构处,UF材料1204可流注到更大的范围,如图12中所示。第二油墨阻挡层1203也包括在间隔1206的与UF1204相同的一侧上。图12还包括油墨阻挡层1202的放大视图(示为平面视图1202A和横截面视图1202B)和油墨阻挡层1203的放大视图(示为平面视图1203A和横截面视图1203B)。如从放大视图所示,在一实施例中,槽1250和1252可以分别被包括在油墨阻挡层1202和1203中。在一个这样的实施例中,油墨阻挡层1202和1203中的槽或图案被切割到油墨中以便包含任何UF材料,所述UF材料打断油墨阻挡层高度。在一具体实施例中,如图12中所示,位于布局1200的左手侧上的槽以及在布局1200的右手侧上的相连接的槽帮助多余的UF材料的流动以及填角宽度的减小。
本文描述的实施例可具有影响深远的实现,例如,用于可靠性改善。应用可包括但不必限于:CPU/处理器、包括CPU与其他器件的组合的多芯片/3D封装、存储器(例如,闪存/DRAM/SRAM)等。下面提供若干非限制性示例。实现包括在高性能微处理器(例如,服务器)封装、多芯片封装、有机封装衬底、传输线、2.5D(管芯和板之间的Si特征)、管芯上、包装上等架构中的应用。更一般而言,本文描述的实施例可具有影响深远的实现,用于CPU/处理器、包括CPU与其他器件的组合的多芯片/3D封装、存储器(例如,闪存/DRAM/SRAM)等。下面提供若干非限制性示例。应用可对于倒装芯片、受控塌陷芯片连接(C4)和/或球栅阵列(BGA)实现特别有用。
在第一通用示例(在图4中示出了其示例)中,根据本发明的一实施例,取决于具体应用,将管芯耦合至柔性衬底或刚性衬底。该衬底具有置于其中的多条电迹线。在一实施例中,还形成外部接触层。在一个实施例中,外部接触层包括球栅阵列(BGA)。在其他实施例中,外部接触层包括诸如、但不限于焊盘栅阵列(LGA)或针脚阵列(PGA)之类的阵列。在封装衬底中提供用于包括用于控制底部填充材料流的阻挡层418的区域414。
在另一示例实现中,图13A示出根据本发明的一实施例的半导体封装1300A的横截面视图,该半导体封装1300A包括与EmIB耦合的多个管芯并且每个管芯包括用于控制底部填充材料流动的阻挡层。参考图13A,半导体封装1300A包括第一管芯1302(诸如CPU、存储器芯片组等)以及第二管芯1304(诸如CPU、存储器芯片组等)。第一管芯1302和第二管芯1304分别通过第一管芯1302和第二管芯1304的凸块1308和1310、以及硅桥的接合盘1312(例如,通过热压接合(TCB))耦合于EmIB1306。第一管芯1302、第二管芯1304、以及EmIB1306与附加的路由层1314被包括在一起,如图13A中所示。附加路由层可以是简单的或复杂的,并且可以用于耦合到其他封装或者可形成有机封装或印刷电路板的部分或全部等。环氧树脂填片材料1349被包括在第一管芯1302和EmIB1312/结构1314界面之间以及在第二管芯1304和EmIB1312/结构1314界面之间。在一个实施例中,在结构1314中提供用于包括用于控制底部填充材料流的阻挡层的区域1301。在另一实施例中,硅桥被使用并且不被嵌入在封装中,而是在开放的孔穴中。
在另一示例实现中,图13B示出根据本发明的一实施例的半导体封装400B的横截面视图,该半导体封装400B包括与嵌入式互连桥(EmIB)耦合的多个管芯/管芯层叠并且每个管芯/管芯层叠包括用于控制底部填充材料流动的阻挡层。参考图13B,半导体封装1300B包括第一管芯1352(诸如中央处理单元CPU)以及第二管芯1354(诸如附加的CPU或存储器管芯或存储器管芯层叠,即图13B中示出的存储器管芯层叠)。第一管芯1352和第二管芯1354分别通过第一管芯1352和第二管芯1354的凸块1358和1360(例如,通过热压接合(TCB))耦合于EmIB1356。EmIB1356嵌入在衬底(例如,柔性有机衬底)或板(诸如环氧树脂PCB材料)材料1370中,如图13B中所示。环氧树脂填片材料1399被包括在第一管芯1352和EmIB1356/衬底1370界面之间以及在第二管芯1354和EmIB1356/衬底1370界面之间。在一个实施例中,在衬底1370中提供用于包括用于控制底部填充材料流的阻挡层的区域1351。
本发明的实施例还可应用于在插入件/衬底界面或在管芯/插入件界面中的一者或两者处的插入件结构。例如,图14示出根据本发明的一实施例的半导体封装1400的横截面视图,该半导体封装包括与插入件耦合的多个管芯并且包括用于控制底部填充材料流的阻挡层。参考图14,半导体封装1400包括第一管芯1402和第二管芯1404。第一管芯1402和第二管芯1404耦合于插入件1406,诸如硅插入件。第一管芯1402和第二管芯1404分别通过第一管芯1402和第二管芯1404的凸块1408和1410、以及插入件1406的接合盘1412(例如,通过热压接合(TCB))耦合于插入件1406。插入件1406将第一管芯1402和第二管芯1404与有机封装1420耦合。有机封装1420可包括其自己的路由层,如图14中所示。又如图14中所示,通过插入件1406的耦合可以通过使用硅通孔(TSV)1430来实现。在一实施例中,如图所示,包括底部填充材料1497、1498或1498的可能位置包括:在第一管芯1402和插入件1406之间、在第二管芯1404和插入件1406之间、以及在插入件1406和封装1420之间。在一个实施例中,在插入件1406中提供用于包括用于控制管芯和中间件之间的底部填充材料流的阻挡层的区域1401A。在一个实施例中,在有机封装1420中提供用于包括用于控制中间件和衬底之间的底部填充材料流的阻挡层的区域1401B。
在另一方面,描述了根据本发明的实施例的具有贯通模制的第一级互连并且包括环氧树脂填片材料的各种3D集成电路封装。
在第一示例中,参考图15,半导体封装1500包括衬底1502。底部半导体管芯1504具有带有表面区域的有源侧1506。底部半导体管芯1504耦合于衬底1502,其中有源侧1506在离衬底1502的远端。顶部半导体管芯1508具有有源侧1510,该有源侧1510的表面区域大于底部半导体管芯1504的表面区域。顶部半导体管芯1508耦合于衬底1502,其中有源侧1510在离衬底1502的近端。底部半导体管芯1504的有源侧1506面对顶部半导体管芯1508的有源侧1510,并且通过管芯到管芯互连结构1512(例如,由从每个管芯的焊接凸块构成的)导电地耦合于顶部半导体管芯1508的有源侧1510。顶部半导体管芯1508通过第一级互连1514导电耦合于衬底1502,第一级互连1514绕过底部半导体管芯1504。顶部半导体管芯1508通过多个凸块1520(例如,高的铜凸块)进一步导电耦合于衬底1502,凸块1502从顶部半导体管芯1508的有源侧1510延伸并且邻近底部半导体管芯1504。多个凸块1520耦合于第一级互连1514。在一实施例中,底部半导体管芯1504和多个凸块1520被容纳在模制层1516中,如图15中所示。又如图15中所示,在一实施例中,顶部半导体管芯1508和底部半导体管芯1504进一步通过环氧树脂填片材料1518耦合于衬底1502。在一个实施例中,在衬底1502中提供用于包括用于控制底部填充材料流的阻挡层的区域1501。
在一实施例中,顶部半导体管芯1508被配置为向底部半导体管芯1504提供电力。在一实施例中,顶部半导体管芯1508被配置为便于底部半导体管芯1504和衬底1504之间的通信(例如,通过衬底1508中的路由)。在一实施例中,底部半导体管芯1504没有硅通孔(TSV)。从而,底部管芯1504和衬底1502之间的连接是通过顶部管芯1508上的互连线以及FLI凸块1514间接实现的。然而,应该理解,在一替换实施例中,可以使用底部管芯上的TSV直接连接底部管芯。
从而,参考图15,对于具有贯通模制FLI的3D IC,底部和顶部有源管芯被面对面地层叠。TSV不是实现这种3D IC层叠所必需的。FLI铜凸块被嵌入在模制层中。顶部和底部管芯具有被模制化合物底部填充的公共界面。就制造而言,具有贯通模制的第一级互连(FLI)的最终的3D IC层叠管芯被附接到封装衬底、被底部填充并随后被组装。
半导体管芯1504或1508中的一者或两者可以从半导体衬底(诸如单晶硅衬底)形成。还可以考虑其他材料,诸如但不限于:III-V族材料以及锗或硅锗材料衬底。半导体管芯1504或1508的有源侧(分别是1506、1510)可以是在其上形成半导体器件的那一侧。在一实施例中,半导体管芯1504或1508各自的有源侧1506或1510包括多个半导体器件,诸如但不限于:晶体管、电容器和电阻器,它们通过管芯互连结构互连在一起成为功能电路,以藉此形成集成电路。本领域的技术人员能够理解,半导体管芯的器件侧包括具有集成电路系统和互连的有源部分。根据若干不同实施例,半导体管芯可以是任何合适的集成电路器件,包括但不限于:微处理器(单核或多核)、存储器器件、芯片组、图形器件、专用集成电路。
层叠管芯装置1500尤其可以适于将存储器管芯与逻辑管芯封装在一起。例如,在一实施例中,管芯1504或1508之一是存储器管芯。另一管芯是逻辑管芯。在本发明的一实施例中,存储器管芯是存储器器件,诸如但不限于:静态随机存取存储器(SRAM)、动态存取存储器(DRAM)、非易失性存储器(NVM),并且TSV管芯是逻辑器件,诸如但不限于微处理器和数字信号处理器。
根据本发明的一实施例,管芯互连结构1512、多个凸块1520、或第一级互连1514中的一者或多者是由金属凸块阵列构成的。在一个实施例中,每个金属凸块由诸如但不限于铜、金或镍等金属构成。取决于具体应用,衬底1502可以是柔性衬底或刚性衬底。在一实施例中,衬底1502具有置于其中的多条电迹线。在一实施例中,还形成外部接触层。在一个实施例中,外部接触层包括球栅阵列(BGA)。在其他实施例中,外部接触层包括诸如、但不限于焊盘栅阵列(LGA)或针脚阵列(PGA)之类的阵列。
参考模制层1516,可使用若干选项来制造该层。在一实施例中,使用FLI凸块和底部管芯过模制(bottom-die over-mold)方法。在一个实施例中,过模制层随后被研磨背面以暴露FLI凸块。在一个实施例中,研磨背面是在凸块(例如,铜凸块)附近执行的,随后使用激光烧蚀来打开铜凸块。随后,在铜凸块上执行焊膏印刷或微球附接。在一个实施例中,执行铜凸块的直接激光开口而不执行任何研磨背面。可以与上面类似地执行焊料操作。在另一实施例中,暴露凸块和底部管芯模制,其中聚合物膜在FLI凸块和底部管芯上方。凸块暴露不是必须的;然而,等离子或激光等可能需要FLI铜凸块的清洁。在另一实施例中,使用转移或压模。在另一实施例中,延伸毛细管底部填充层形成以覆盖FLI凸块而不是常规模制。模制层1516可以由非导电材料构成。在一个实施例中,模制层1516由诸如但不限于由氧化硅填料构成的塑料或环氧树脂等材料构成。
在第二示例中,参考图16,半导体封装1600包括衬底1602。底部半导体管芯1604具有带有表面区域的有源侧1606。底部半导体管芯1604耦合于衬底1602,其中有源侧1606在离衬底1602的远端。顶部半导体管芯1608具有有源侧1610,该有源侧1604的表面区域大于底部半导体管芯1504的表面区域。顶部半导体管芯1608耦合于衬底1602,其中有源侧1610在离衬底1602的近端。底部半导体管芯1604的有源侧1606面向顶部半导体管芯1608的有源侧1610,并通过管芯到管芯互连结构1612导电耦合于顶部半导体管芯1608的有源侧1610。顶部半导体管芯1608通过第一级互连1614导电耦合于衬底1602,第一级互连1614绕过底部半导体管芯1604。顶部半导体管芯1608被进一步通过多个凸块1602导电耦合于衬底1602,多个凸块1620从顶部半导体管芯1608并且至少部分邻近底部半导体管芯1604的有源侧1610延伸到多个焊料球1622。多个焊料球1622耦合于第一级互连1614。在一实施例中,底部半导体管芯1604、多个凸块1620、和多个焊料球1622被容纳在模制层1616中,如图16中所示。又如图16中所示,在一实施例中,顶部半导体管芯1608和底部半导体管芯1604进一步通过环氧树脂填片材料1618耦合于衬底1602。在一个实施例中,在衬底1602中提供用于包括用于控制底部填充材料流的阻挡层的区域1601。
从而,参考图16,用于具有贯通模制FLI的3D IC的另一方法包括在模制层内部设置焊料。焊料可在模制之前放置并随后通过研磨背面或激光开口来暴露。替换地,可在激光开口贯通铜凸块之后放置焊膏。封装管芯的特性和配置以及封装1600的材料可以与上面针对封装1500所描述的那些相同或类似。在一实施例中,焊料球1622包含铅或者不含铅,诸如为金和锡焊料或银和锡焊料的合金。
参考图15和16,混合FLI凸块高度可用于顶部半导体管芯。例如,在一个实施例中,通过使用高帽或细长的铜柱凸块工艺来创建混合高度FLI凸块。这里,第一凸块掩模和镀覆操作提供了FLI和LMI的短凸块高度。第二凸块掩模和镀覆操作仅提供了更高的FLI凸块。应该理解,针对FLI可执行铜和焊料凸块的各种组合,如图15和16中所示。
在本发明的另一方面,公开了具有嵌入式层叠硅通孔管芯的无芯衬底。例如,具有C4焊料球连接的半导体管芯可用无凸块构建层(即BBUL)或BBUL处理器封装技术来封装。这种工艺是无凸块的,因为其不使用常用的微小焊料凸块来将硅管芯附连到处理器封装引线。其具有构建层,因为其是围绕硅管芯生长或构建的。此外,一些半导体封装现在使用无芯衬底,该无芯衬底不包括常规衬底中常见的厚树脂芯层。在一实施例中,作为BBUL工艺的一部分,使用半添加工艺(SAP)来在半导体管芯的有源侧上方形成导电通孔和路由层,以完成其余的层。在一实施例中,形成外部接触层。在一个实施例中,外部导电接触部的阵列是球栅阵列(BGA)。在其他实施例中,外部导电接触部的阵列是诸如、但不限于焊盘栅阵列(LGA)或针脚阵列(PGA)之类的阵列。在涉及层叠管芯的一具体示例中,图17示出了根据本发明的实施例的具有嵌入式层叠硅通孔管芯并且包括用于控制底部填充材料流动的阻挡层的无芯衬底的横截面图。
参考图17,层叠管芯装置1700包括嵌入在无芯衬底1704中的第一管芯1702。无芯衬底1704包括焊区侧1706和管芯侧1708。第一管芯1702还包括有源表面或器件侧1710、以及背侧表面或背侧1712,并且可以看出,第一管芯1702的有源表面1710朝向焊区侧1706,而背侧1712与无芯衬底1704的管芯侧1708朝向相同的方向。有源表面可以包括多个半导体器件,诸如但不限于通过管芯互连结构被连接到一起形成功能电路的晶体管、电容器和电阻器以由此形成集成电路。
本领域的技术人员能够理解,第一管芯1702的器件侧1710包括具有集成电路和互连的有源部分(未示出)。根据若干不同实施例,第一管芯1702可以是任何合适的集成电路器件、包括但不限于微处理器(单核或多核)、存储器器件、芯片组、图形器件、专用集成电路。在一实施例中,层叠管芯装置1700还包括布置在第一管芯1702的背侧1712上的管芯接合膜1730。
在一实施例中,第一管芯1702是包括第二管芯1714的更大装置的一部分,第二管芯1714布置在管芯侧1708之下并且耦合到第一管芯1702。第二管芯1714还以简化的图示被示为具有有源表面或器件侧1716,但是它还可以具有M1至M11的金属化部或任何数目和顶部金属化部厚度。第二管芯1714还具有背侧表面或背侧1718。
第二管芯1714也嵌入在无芯衬底1704中。在一实施例中,第二管芯1714具有至少一个硅通孔1720。示出了两个硅通孔,枚举了所述两个硅通孔之一,但是为简单起见呈现了所示的两个硅通孔。在一实施例中,第二管芯1714中存在高达1000个硅通孔。因此,第二管芯1714可以被称为包括其中布置有硅通孔的管芯(TSV管芯1714)。TSV管芯1714的器件侧1716朝向焊区侧1706,而背侧1718朝向无芯衬底1704的管芯侧1708。本领域的技术人员能够理解,TSV管芯1714的器件侧1716还包括具有集成电路和互连的有源部分(未示出)。根据若干不同实施例,TSV管芯1714可以是任何合适的集成电路设备,包括但不限于微处理器(单核或多核)、存储器设备、芯片组、图形设备、专用集成电路。
如所示那样,第一管芯1702通过所述至少一个硅通孔1720耦合到TSV管芯1714。在一实施例中,第一管芯1702通过所述一个或多个硅通孔电耦合到TSV管芯1714。在一个实施例中,第一管芯1702经由所述一个或多个硅通孔1720通过布置在第一管芯1702上的一个或多个相应的导电凸块1726以及通过布置在TSV管芯1714上的一个或多个接合焊盘(未示出)电耦合到TSV管芯1714。接合焊盘被包括在TSV管芯1714的背侧1718上并且与所述一个或多个硅通孔1720对准。在一实施例中,环氧助焊剂材料层1728布置在第一管芯1702与TSV管芯1714之间。在一实施例中,无芯衬底1704在第一管芯1702与TSV管芯1714之间不含附加的布线层。也就是说,在一实施例中,第一管芯1702和TSV管芯1714仅仅通过第一管芯1702的器件侧1710上的导电凸块以及TSV管芯1714的所述一个或多个硅通孔1720来通信。
TSV管芯1714还以简化形式被示出具有器件侧1718上的的金属化部。金属化部在器件侧1716与TSV管芯1714中的集成电路接触。在一实施例中,金属化部具有金属1(M1)到金属11(M11)金属化层以便将TSV管芯1714的复杂度输出到外界,其中M1与TSV管芯1714中的集成电路接触。在所选实施例中,在M1与M11之间可以存在任何数目的金属化部。在示例实施例中,TSV管芯1714具有从M1至M7的金属化部,且M7比M1至M6更厚。根据给定应用效用,可实现其他金属化部数目和厚度组合。
在一实施例中,如图17所示,层叠管芯装置1700包括在无芯衬底1704的焊区侧1706处的基础衬底1722。例如,在第一管芯1702和TSV管芯1714是手持式设备(诸如智能电话实施例或手持式阅读器实施例)的一部分的情况下,基础衬底1722是主板。在第一管芯1702和TSV管芯1714是手持式设备(诸如智能电话实施例或手持式阅读器实施例)的一部分的示例性实施例中,基础衬底1722是外壳,诸如个人在使用时触摸的部分。在第一管芯1702和TSV管芯1714是手持式设备(诸如智能电话实施例或手持式阅读器实施例)的一部分的示例性实施例中,基础衬底1722包括主板和外壳(诸如个人在使用时触摸的部分)。在一实施例中,通过底部填充材料1799(例如,环氧树脂底部填充材料)将无芯衬底1704进一步耦合于基础衬底1122,也如图17中所示。在一个这样的实施例中,在基础衬底1722中提供用于包括用于控制底部填充材料流的阻挡层的区域1701。
外部导电接触部1732的阵列布置在无芯衬底1704的焊区侧1706上。在一实施例中,外部导电接触部1732将无芯衬底1704耦合到基础衬底1722。外部导电接触部1732被用于与基础衬底1722的电通信。在一个实施例中,外部导电接触部1732的阵列是球栅阵列(BGA)。焊料掩模1734遮蔽形成无芯衬底1704的焊区侧1706的材料。外部导电接触部1732布置在凸块接合焊盘1736上。
图18是根据本发明实施例的计算机系统1800的示意图。所描绘的计算机系统1800(也称为电子系统1800)可具体化根据若干所公开的实施例中的任一个和在本公开中所陈述的它们的等价方案的具有用于控制底部填充材料流的阻挡层的封装衬底。计算机系统1800可以为诸如上网本计算机的移动装置。计算机系统1800可以是诸如无线智能电话之类的移动设备。计算机系统1800可以为台式计算机。计算机系统1800可以是手持式读取器。计算机系统1800可以为服务器系统。计算机系统1800可以是超级计算机或高性能计算系统。
在实施例中,电子系统1800为计算机系统,该计算机系统包括用以电耦合电子系统1800的多个部件的系统总线1820。系统总线1820为单个总线或根据各个实施例的总线的任何组合。电子系统1800包括将功率提供至集成电路1810的电压源1830。在一些实施例中,电压源1830通过系统总线1820将电流提供至集成电路1810。
集成电路1810电耦合至系统总线1820并且包括任何电路,或根据实施例的电路的组合。在一实施例中,集成电路1810包括任何类型的处理器1812。如本文所使用的,处理器1812可意指任何类型的电路,诸如,但不限于,微处理器、微控制器、图形处理器、数字信号处理器、或其他处理器。在一实施例中,处理器1812包括或耦合于用于致密多芯片封装互连的可靠微带路由,如本文中所公开的。在一实施例中,SRAM实施例在处理器的存储器高速缓存中找到。可包括在集成电路1810中的其他类型的电路为定制电路或专用集成电路(ASIC),例如,在诸如蜂窝电话、智能电话、寻呼机、便携式计算机、双向无线电、以及类似的电子系统的无线装置中使用的通信电路1814,或用于服务器的通信电路。在一实施例中,集成电路1810包括诸如静态随机存取存储器(SRAM)之类的管芯上存储器1816。在一实施例中,集成电路1810包括诸如嵌入式动态随机存取存储器(eDRAM)的嵌入式管芯上存储器1816。
在一个实施例中,集成电路1810与随后的集成电路1811互补。有用的实施例包括双处理器1813、双通信电路1815和双管芯上存储器1817,诸如SRAM。在实施例中,双集成电路1810包括诸如eDRAM之类的嵌入式管芯上存储器1817。
在一实施例中,电子系统1800还包括外部存储器1840,该外部存储器1840又可包括适合于特定应用的一个或多个存储器元件,诸如RAM形式的主存储器1842、一个或多个硬驱动器1844、和/或处理可移除介质1846(诸如软磁盘、紧致盘(CD)、数字多功能盘(DVD)、快闪存储器驱动器以及本领域已知的其他可移除介质)的一个或多个驱动器。根据一实施例,外部存储器1840也可以是嵌入式存储器1848,诸如嵌入在管芯叠层中的第一管芯。
在一实施例中,电子系统1800还包括显示设备1850、音频输出1860。在一实施例中,电子系统1800包括输入设备,诸如控制器1870,其可以是键盘、鼠标、轨迹球、游戏控制器、话筒、语音识别设备、或向电子系统1800中输入信息的任何其他输入设备。在实施例中,输入设备1870是照相机。在一实施例中,输入设备1870是数字录音器。在一实施例中,输入设备1870是照相机和数字录音器。
如本文中所示,集成电路1810可按照多种不同实施例来实现,包括根据若干公开的实施例中的任一实施例及其等价方案的具有用于控制底部填充材料流的阻挡层的封装衬底、电子系统、计算机系统、一种或多种制造集成电路的方法、以及一种或多种制造包括根据如本文多个实施例中陈述的若干公开实施例中的任一实施例及其业内认可等价方案的具有用于控制底部填充材料流的阻挡层的电子组装件的方法。根据所公开的若干具有用于控制底部填充材料流的封装衬底实施例及其等效方案,可以改变元件、材料、几何形状、尺寸以及操作顺序以适合特定I/O耦合要求,这些要求包括处理器安装衬底中所嵌入的微电子管芯的阵列接触数、阵列接触配置。如图18中的虚线所表示的,可包括基础衬底。同样如图18中所示,还可包括无源器件。
本发明的各实施例包括用于半导体封装中的减小的管芯到管芯间隔的底部填充材料流控制和所得的半导体封装。
在一实施例中,半导体装置包括第一和第二半导体管芯,每个半导体管芯具有其上有集成电路的表面,所述集成电路通过多个导电接触耦合于公共半导体封装衬底的最上面的金属化层的接触盘,该第一和第二板导体管芯分开一间隔。阻挡层结构位于第一半导体管芯和公共半导体封装衬底之间并且至少部分地在第一半导体管芯之下。底部填充材料层与第二半导体管芯接触并且与阻挡层结构接触,但是不与第一半导体管芯接触。
在一个实施例中,阻挡层结构包括位于公共半导体封装衬底的最上表面上的多条铜迹线。
在一个实施例中,该多条铜迹线具有人字形图案。
在一个实施例中,阻挡层结构包括位于公共半导体封装衬底的最上表面上的经图案化的油墨结构。
在一个实施例中,将第一和第二半导体管芯分开的该间隔为约100微米。
在一个实施例中,第一半导体管芯是存储器管芯,而第二半导体管芯是一个诸如但不限于微处理器管芯或片上系统(SoC)管芯的管芯。
在一个实施例中,该阻挡层结构包括用于限制用于形成底部填充材料层的底部填充材料的流动的多个槽。
在一个实施例中,该第一和第二半导体管芯通过置于该公共半导体封装衬底内的嵌入式互连桥(EmIB)彼此电耦合。
在一实施例中,半导体封装包括分开一间隔的第一和第二相邻的半导体管芯。硅插入件结构被置于第一和第二半导体管芯下方并电耦合该第一和第二半导体管芯。有机封装衬底被置于硅插入件结构下方并电耦合于该硅插入件结构。该有机封装衬底包括位于其中的多个路由层。阻挡层结构被置于第一半导体管芯和硅插入件结构之间并且至少部分地在第一半导体管芯之下。底部填充材料层与第二半导体管芯接触并且与阻挡层结构接触,但是不与第一半导体管芯接触。
在一个实施例中,阻挡层结构包括位于该硅插入件结构的最上表面上的多条铜迹线。
在一个实施例中,该多条铜迹线具有人字形图案。
在一个实施例中,阻挡层结构包括位于该硅插入件结构的最上表面上的经图案化的油墨结构。
在一个实施例中,将第一和第二半导体管芯分开的该间隔为约100微米。
在一个实施例中,第一半导体管芯是存储器管芯,而第二半导体管芯是一个诸如但不限于微处理器管芯或片上系统(SoC)管芯的管芯。
在一个实施例中,该阻挡层结构包括用于限制用于形成底部填充材料层的底部填充材料的流动的多个槽。
在一个实施例中,该半导体封装还包括被置于该有机封装衬底和该硅插入件结构之间的第二阻挡层结构。
在一实施例中,无凸块构建层(BBUL)半导体装置包括具有背侧和器件侧的半导体管芯。无芯衬底包括焊区侧和管芯侧,而半导体衬底被嵌入在无芯衬底中。半导体管芯的背侧朝向无芯衬底的管芯侧,并且半导体管芯的器件侧朝向无芯衬底的焊区侧。包括基础衬底。外部导电接触阵列被置于该无芯衬底的焊区侧上,从而将该无芯衬底电耦合于该基础衬底。阻挡层结构被置于该半导体管芯和邻近该半导体管芯的该基础衬底之间。底部填充材料层被置于该无芯衬底的焊区侧和该基础衬底之间,并且围绕该多个外部导电接触,该底部填充材料层与该阻挡层结构接触。
在一个实施例中,阻挡层结构包括位于该基础衬底的最上表面上的多条铜迹线。
在一个实施例中,该多条铜迹线包括人字形图案。
在一个实施例中,阻挡层结构包括位于该基础衬底的最上表面上的经图案化的油墨结构。
在一个实施例中,该阻挡层结构包括用于限制用于形成底部填充材料层的底部填充材料的流动的多个槽。
Claims (18)
1.一种半导体装置,包括:
第一和第二半导体管芯,每个半导体管芯具有其上有集成电路的表面,所述集成电路通过多个导电接触耦合于公共半导体封装衬底的最上面金属化层的接触盘,所述第一和第二半导体管芯分开一间隔;
被置于所述第一半导体管芯和所述公共半导体封装衬底之间并且至少部分地在所述第一半导体管芯之下的阻挡层结构,其中所述阻挡层结构包括被置于所述公共半导体封装衬底的最上表面上的多条铜迹线,或者其中所述阻挡层结构包括被置于所述公共半导体封装衬底的最上表面上的经图案化的油墨结构;以及
底部填充材料层,与所述第二半导体管芯接触并且与所述阻挡层结构接触,但是不与所述第一半导体管芯接触。
2.如权利要求1所述的半导体装置,其特征在于,当所述阻挡层结构包括被置于所述公共半导体封装衬底的最上表面上的多条铜迹线时,所述多条铜迹线包括人字形图案。
3.如权利要求1所述的半导体装置,其特征在于,将所述第一和第二半导体管芯分开的所述间隔为约100微米。
4.如权利要求1所述的半导体装置,其特征在于,所述第一半导体管芯为存储器管芯,而所述第二半导体管芯为从微处理器管芯和片上系统SoC管芯中选择的一管芯。
5.如权利要求1所述的半导体装置,其特征在于,所述阻挡层结构包括用于限制用于形成所述底部填充材料层的底部填充材料的流动的多个槽。
6.如权利要求1所述的半导体装置,其特征在于,所述第一和第二半导体管芯通过置于所述公共半导体封装衬底内的嵌入式互连桥EmIB彼此电耦合。
7.如权利要求1所述的半导体装置,其特征在于,当所述阻挡层结构包括被置于所述公共半导体封装衬底的最上表面上的多条铜迹线时,所述阻挡层结构包括针对所述底部填充材料层的多余部分的多条逃逸迹线。
8.一种半导体封装,包括:
分开一间隔的邻近的第一和第二半导体管芯;
硅插入件结构,其被置于所述第一和第二半导体管芯下方并电耦合所述第一和第二半导体管芯;
有机封装衬底,其被置于所述硅插入件结构下方并且电耦合于所述硅插入件结构,所述有机封装衬底包括位于其中的多个路由层;
阻挡层结构,其被置于所述第一半导体管芯和所述硅插入件结构之间并且至少部分地在所述第一半导体管芯之下,其中所述阻挡层结构包括被置于所述硅插入件结构的最上表面上的多条铜迹线,或者其中所述阻挡层结构包括被置于所述硅插入件结构的最上表面上的经图案化的油墨结构;以及
底部填充材料层,与所述第二半导体管芯接触并且与所述阻挡层结构接触,但是不与所述第一半导体管芯接触。
9.如权利要求8所述的半导体封装,其特征在于,当所述阻挡层结构包括被置于所述硅插入件结构的最上表面上的多条铜迹线时,所述多条铜迹线包括人字形图案。
10.如权利要求8所述的半导体封装,其特征在于,将所述第一和第二半导体管芯分开的所述间隔为约100微米。
11.如权利要求8所述的半导体封装,其特征在于,所述第一半导体管芯为存储器管芯,而所述第二半导体管芯为从微处理器管芯和片上系统SoC管芯中选择的一管芯。
12.如权利要求8所述的半导体封装,其特征在于,所述阻挡层结构包括用于限制用于形成所述底部填充材料层的底部填充材料的流动的多个槽。
13.如权利要求8所述的半导体封装,其特征在于,还包括:
被置于所述有机封装衬底和所述硅插入件结构之间的第二阻挡层结构。
14.如权利要求8所述的半导体封装,其特征在于,当所述阻挡层结构包括被置于所述硅插入件结构的最上表面上的多条铜迹线时,所述阻挡层结构包括针对所述底部填充材料层的多余部分的多条逃逸迹线。
15.一种无凸块构建层半导体装置,包括:
具有背侧和器件侧的半导体管芯;
包括焊区侧和管芯侧的无芯衬底,其中所述半导体管芯嵌入在所述无芯衬底中,所述半导体管芯的所述背侧面向所述无芯衬底的所述管芯侧,而所述半导体管芯的所述器件侧面向所述无芯衬底的所述焊区侧;
基础衬底;
外部导电接触阵列,其被置于所述无芯衬底的焊区侧上,从而将所述无芯衬底电耦合于所述基础衬底;
阻挡层结构,其被置于所述半导体管芯和邻近所述半导体管芯的所述基础衬底之间,其中所述阻挡层结构包括被置于所述基础衬底的最上表面上的多条铜迹线,或者其中所述阻挡层结构包括被置于所述基础衬底的最上表面上的经图案化的油墨结构;以及
底部填充材料层,其被置于所述无芯衬底的所述焊区侧和所述基础衬底之间,并且围绕多个外部导电接触,所述底部填充材料层与所述阻挡层结构接触。
16.如权利要求15所述的无凸块构建层半导体装置,其特征在于,当所述阻挡层结构包括被置于所述基础衬底的最上表面上的多条铜迹线时,所述多条铜迹线包括人字形图案。
17.如权利要求15所述的无凸块构建层半导体装置,其特征在于,所述阻挡层结构包括用于限制用于形成所述底部填充材料层的底部填充材料的流动的多个槽。
18.如权利要求15所述的无凸块构建层半导体装置,其特征在于,当所述阻挡层结构包括被置于所述基础衬底的最上表面上的多条铜迹线时,所述阻挡层结构包括针对所述底部填充材料层的多余部分的多条逃逸迹线。
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CN104253115A (zh) | 2014-12-31 |
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KR20150002518A (ko) | 2015-01-07 |
DE102014108992A1 (de) | 2014-12-31 |
KR101645507B1 (ko) | 2016-08-05 |
US10192810B2 (en) | 2019-01-29 |
US20190148268A1 (en) | 2019-05-16 |
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