CN102543923A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN102543923A
CN102543923A CN2011104171778A CN201110417177A CN102543923A CN 102543923 A CN102543923 A CN 102543923A CN 2011104171778 A CN2011104171778 A CN 2011104171778A CN 201110417177 A CN201110417177 A CN 201110417177A CN 102543923 A CN102543923 A CN 102543923A
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CN102543923B (zh
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L.海策尔
T.迈耶
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Infineon Technologies AG
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Abstract

本发明涉及半导体器件及其制造方法。公开一种半导体器件和制作半导体器件的方法。半导体器件包括布置于芯片之上的再分布层，该再分布层包括第一再分布线。半导体还包括：设置于再分布层之上的隔离层，该隔离层具有形成第一焊盘区的第一开口；以及位于第一开口中并且与第一再分布线接触的第一互连。第一焊盘区中的再分布线与到半导体器件的中性点的第一方向正交布置。

Description

半导体器件及其制造方法
技术领域
本发明一般地涉及一种半导体器件和一种用于制造半导体器件的方法。
背景技术
一般而言，在完全处理晶片之后，芯片被切分（dice）、然后包装成个别封装或者与其它部件一起装配于混合或者多芯片模块中。
该封装可以提供芯片到印刷电路板（PCB）或者到电子产品的连接。由于芯片中使用的薄和易碎的金属系统而可能未直接产生与芯片的连接。
该封装可以物理上保护芯片免受破损或者污染。该封装也可以保护芯片免受可能干扰芯片的化学物、湿气和/或气体。
该封装也可以在芯片处于操作时从芯片耗散热量。一些芯片可能生成大量热量，使得重要的是外壳（enclosure）材料可以用于从芯片带走热量。
发明内容
根据本发明的一个实施例，公开一种半导体器件。该半导体器件包括布置于芯片之上的再分布层，该再分布层包括第一再分布线。半导体还包括：设置于再分布层之上的隔离层，该隔离层具有形成第一焊盘区的第一开口；以及位于第一开口中并且与第一再分布线接触的第一互连。第一焊盘区中的再分布线与到半导体器件的中性点的第一方向正交布置。
根据本发明的另一实施例，公开一种用于制造半导体器件的方法。该方法包括：在芯片之上形成第一再分布线，该第一再分布线电连接到位于芯片的顶表面上的第一芯片焊盘；并且在再分布线之上形成阻焊（solder stop）层。该方法还包括：通过在阻焊层中形成暴露第一再分布线的第一开口来形成第一焊盘区，使得第一焊盘区中的第一再分布线与到半导体器件的中性点的第一方向正交定向；并且将第一互连附着到第一焊盘区。
附图说明
为了更完整理解本发明及其优点，现在参照与附图结合进行的下文描述，在所述附图中：
图1示出了包括焊盘区的半导体器件的横截面图；
图2a示出了焊盘区在第一方向上的横截面图；
图2b示出了两个邻近互连的横截面图；
图2c示出了焊盘区的俯视图；
图2d示出了焊盘区在第二方向上的横截面图；
图3a示出了包括焊盘区/互连和再分布线的半导体器件，其中每个焊盘区中的再分布线与它们到中性点的相应方向正交布线（route）；
图3b示出了包括焊盘区/互连和再分布线的半导体器件，其中与中性点更远的焊盘区中的再分布线与它们到中性点的相应方向正交布线，并且其中与中性点更近的焊盘区中的再分布线未与它们到中性点的相应方向正交布线；并且
图4示出了嵌入式晶片级球栅阵列。
具体实施方式
下面详细讨论当前优选实施例的实现和使用。然而应当明白，本发明提供可以在广泛各种具体背景中实施的许多适用发明概念。讨论的具体实施例仅说明用于实现和使用本发明的具体方式而未限制本发明的范围。
将在具体背景（即晶片级封装或者嵌入式晶片级球栅阵列）中关于实施例描述本发明。然而本发明也可以应用于其它类型的半导体器件。
晶片级封装指代一种在晶片级对集成电路进行封装的封装技术。芯片直接封装于晶片上，并且在封装芯片之后进行晶片的切分。晶片级封装可以用来制造芯片规模封装。
扇出（fan-out）晶片级封装可以是晶片级封装的增强。可以不在硅晶片上而是在人造晶片上实现封装。切分标准晶片，并且单体化的（singulated）芯片放置于载体上。可以自由选择在载体上的芯片之间的距离。在芯片周围的间隙可以由铸造化合物填充以形成人造晶片。处理人造晶片以制造包括芯片和周围扇出区的封装。可以在芯片和扇出区上实现互连元件，从而形成嵌入式晶片级球栅阵列（eWLB）封装。
扇出晶片级封装可以提供用于如下芯片的封装解决方案：与应用标准晶片级封装技术的芯片制造相比，这些芯片针对给定节距需要更高集成水平和更大接触数目。
本发明的实施例由于焊盘区中的再分布线的定向而可以提供高器件可靠性。实施例由于线-焊盘设计而可以提供高器件可靠性。实施例由于更厚阻焊层而可以提供高互连成品率。实施例可以增加再分布层的再分布线的布线密度。实施例可以允许在互连之间施加更多再分布线，这使封装设计潜在地更容易。
图1图示了半导体器件100的一个实施例的横截面图。可以根据标准晶片级封装工艺、根据扇出晶片级封装工艺或者根据任何其它适当的包装工艺来制造半导体器件100。
半导体器件100包括具有芯片焊盘120的半导体芯片110。半导体器件100包括第一隔离层140、再分布层（RLD）的再分布线150和第二隔离层160。互连180放置于焊盘区170之上并且焊接到再分布线150。半导体芯片110可以是基带、RF或者功率管理芯片。
半导体芯片110可以包括具有顶部金属化层（未示出）的集成电路。顶部金属化层可以嵌入于层间电介质中。芯片焊盘120可以布置于顶部金属化层中或者顶部金属化层之上并且与顶部金属化层接触。芯片焊盘120可以包括铝（Al）或者其它适当的材料。钝化层可以覆盖层间电介质和金属化层，但是可以不覆盖芯片焊盘120。钝化层可以密封和保护半导体芯片110。
第一隔离层140可以布置于半导体芯片110上。第一隔离层140可以例如是电介质材料或者基于环氧树脂的材料。电介质材料可以包括聚合物（比如聚酰亚胺）。可以使用旋涂（spin-on）沉积或者任何其它适当的沉积技术（比如例如印刷）来形成第一隔离层140。第一隔离层140可以提供在半导体芯片110中的顶部金属化层与再分布线150之间的进一步隔离。
再分布层的再分布线150可以布置于第一隔离层140上。再分布线150电连接芯片焊盘120与互连180。再分布线150可以位于芯片焊盘120上面并且至少部分覆盖芯片焊盘120。再分布线150可以是例如包括铜、钛、镍、金、钨或者这些材料的组合的一层或者多层。再分布线150可以将芯片焊盘120电气上重新定位到半导体器件100上的不同位置。
可以应用电镀工艺来形成再分布线150。在一个实施例中，种子层可以保形地沉积于第一隔离层140之上。种子层可以是单种材料（比如铜）或者材料的组合。可以通过溅射或者另一适当的技术来形成种子层。掩模材料（比如抗电镀剂）可以沉积于种子层之上。可以图案化掩模材料，并且可以去除部分以形成暴露部分种子层的开口。传导材料可以使用电镀工艺而沉积在种子层之上的开口中。传导材料可以是铜或者任何其它适当的材料。可以去除剩余掩模材料从而暴露种子层，然后可以去除暴露的种子层。
第二隔离层160可以布置于再分布线150和第一隔离层140之上。第二隔离层160可以是电介质材料。电介质材料可以包括聚合物（比如聚酰亚胺）。可以使用旋涂沉积或者任何其它适当的沉积技术（比如例如印刷）来沉积第二隔离层160。第二隔离层160可以包括与第一隔离层140相同的材料或者不同的材料。第二隔离层160可以是阻焊层。
开口布置于第二隔离层160中。开口可以暴露底下第一隔离层140和再分布线150的部分。暴露底下第一隔离层140和再分布线150的部分的、开口的区域可以限定焊盘区170。
互连180装配于第二隔离层160的开口中的焊盘区170上。互连180可以直接焊接于再分布线150上。再分布线150和焊接的互连180可以提供低电阻电接触和高强度锚点（anchorage）。互连180可以是焊球。焊球可以是共晶Sn-Pb（锡为63%、铅为37%）或者SAC合金（锡/银/铜，元素符号命名为Sn/Ag/Cu）或者任何其它适当的材料。
半导体器件100仅图示了单个芯片焊盘120、单个再分布线150和单个互连180以求简化。半导体器件100可以包括任何适当数目的芯片焊盘120、再分布线150和互连180。
实施例包括一个互连180焊接到一个再分布线150和/或若干互连180焊接到一个分布线150。
图2a示出了半导体器件100的细节的横截面图。图2a图示了半导体器件100的如下顶部部分，该顶部部分包括半导体芯片110的顶部部分、第一隔离层140、再分布线150、第二隔离层160和互连180。图2a还图示了焊盘区170和在焊盘区以外的区域175。焊盘区170可以被限定为第二隔离层160中的如下开口，该开口暴露再分布线150和第一隔离层140的部分。区域175可以被限定为包围焊盘区170的区。互连180位于第二隔离层160的开口中并且直接焊接于再分布线150上。
第二隔离层160可以是相对厚的层。在常规技术中，第二隔离层160的厚度d1可以是10μm或者更少。在一个实施例中，第二隔离层160的厚度d1可以是约15μm或者更大。隔离层160的增加厚度可以提供防止两个或者更多互连180在回流工艺期间移动到一起太近的优点。可以避免在两个或者更多互连180之间的潜在短路。在图2b中示出了这一点。
互连180的底部可以位于第二隔离层160的开口中。第二隔离层160可以直接接触和支撑互连180。在一个例子中，针对标称300μm的标准互连直径并且针对0.4mm的标准节距，第二隔离层160可以在焊接之后横向包围互连180的约6%。在另一例子中，第二隔离层160可以横向包围互连180的约4%至约8%。
图2c示出了半导体器件100的一个实施例沿着图2a的线2c-2c的俯视图。图2c图示了第一隔离层140、再分布线150和互连180。互连180在焊盘区170放置于再分布线150和底下第一隔离层140上并且与它们电接触。互连180在这一例子中放置于再分布线150的末端或者与该末端接近，但是在其它例子中可以放置于沿着再分布线150的任何地方。
在一个实施例中，焊盘区170为线焊盘。再分布线150可以是焊盘区170中的线，使得焊盘区170包括再分布线150的部分和底下第一隔离层140的部分。再分布线150可以未形成完全覆盖焊盘区170的平面。具体而言，再分布线150可以未形成覆盖完整焊盘区170的圆形焊盘或者矩形焊盘。
在一个实施例中，（在焊盘区以外的）区域175中的再分布线150的宽度d2可以与焊盘区170中的再分布线150的宽度d3基本上相同。在一个实施例中，焊盘区170中的再分布线150的宽度d3相对于区域175中的再分布线的宽度d2可以未延伸、放大或者更宽。
在一个实施例中，再分布线150与到焊盘区170中的半导体器件100的中性点的方向AR正交定向（下面将进一步解释）。区域175中的再分布线150可以具有与焊盘区170中的再分布线150相同的定向或者可以具有与焊盘区170中的再分布线150不同的定向。例如，区域175中的再分布线150可以与方向AR平行布置。
图2d示出了半导体器件100的一个实施例沿着图2c中的线2d-2d的横截面图。图2d的横截面图与图2a的横截面图正交。图2d示出了直接附着到再分布线150的、第二隔离层160的开口中的焊盘区170上放置的互连180。焊盘区170包括再分布线150的部分和底下第一隔离层140的部分。焊盘区170中的再分布线150未覆盖完整焊盘区170。
图3a示出了半导体器件200的一个实施例。多个互连181/182位于半导体器件200的顶表面上的焊盘区171/172中。图示了多个再分布线151/152以便更好理解，即使它们从俯视图中不可见。中性点190可以限定于半导体器件200的顶表面上。中性点190可以是半导体器件200的顶表面上的中间或者中心点。箭头AR表明从焊盘区171/172的中心点到中性点190的方向。例如箭头AR1表明从第一焊盘区171到中性点190的方向而箭头AR2表明从第二焊盘区172到中性点190的方向。
焊盘区/互连171/181中的第一再分布线151相对于方向AR1正交布置，而焊盘区/互连172/182中的第二再分布线152与方向AR2正交布置。如关于图2c讨论的那样，再分布线151/152可以在焊盘区170/171中与到中性点的方向正交布线，但是可以在焊盘区171/172以外不同地布线。在一个实施例中，用于所有焊盘区/互连的再分布线可以与它们到中性点的相应方向正交布置。
图3b示出了半导体器件200的另一实施例。第一焊盘区/互连173/183放置于与中性点190相距第一距离处，而第二焊盘区/互连174/184放置于与中性点190相距第二距离处。第二距离到中性点190比第一距离更短。在一个实施例中，第一焊盘区/互连173/183中的第一再分布线153与方向AR3正交布置，而焊盘区/互连174/184中的第二再分布线154未与方向AR4正交布置。在一个实施例中，标记为A和B的互连的焊盘区中的再分布线与它们的相应方向AR正交布置，而标记为C的互连的焊盘区中的再分布线未与它们的相应方向AR正交布置。在一个实施例中，第一焊盘区/互连173/184比第二焊盘区/互连174/184更接近边缘210定位。
在一个实施例中，第一焊盘区/互连173/183中的再分布线153与到中性点190的方向AR3正交布线而未与半导体器件200的边缘210平行布线。
一个再分布线可以包括两个或者更多焊盘区。每个焊盘区中的再分布线可以与到中性点的相应方向正交布线。再分布线可以在一些焊盘区中与到中性点的方向正交布线，而再分布线在其它焊盘区中未与到中性点的方向正交布线。例如，与中性点的距离更长的第一焊盘区中的再分布线的第一部分与到中性点的第一方向正交布置，而与中性点的距离更短的第二焊盘区中的再分布线的第二部分可以未与到中性点的第二方向正交布置。
用于焊盘区中的与方向AR正交布置的再分布线的再分布线互连连接可以比用于焊盘区中的与方向BR平行（或者与半导体器件的边缘平行）布置的再分布线的再分布线互连连接更可靠。用于焊盘区中的与方向AR正交布置的再分布线的再分布线互连连接可以比用于焊盘区中的与方向AR平行布置的再分布线的再分布线互连连接更可靠。
图4示出了封装300的横截面图。封装300可以是嵌入式晶片级球栅阵列（eWLB）。芯片320嵌入于模制化合物中，从而在芯片320周围形成扇出区域310。芯片焊盘120可以位于芯片320的表面上。再分布层可以延伸超出芯片320，从而在芯片320和扇出区域310上形成焊盘区域170。芯片焊盘120经由再分布层的再分布线150重新布线到芯片320和扇出区域310上的不同焊盘区170。这样的布置允许设计更大的互连节距和/或增加数目的互连。
如上文所描述的那样，互连180可以直接附着和焊接到焊盘区170中的再分布线150。再分布层可以嵌入于第一和第二隔离层140、160中。第二隔离层的厚度可以至少约15μm以防止互连180在回流工艺期间移动到一起太近。焊盘区170中的再分布线150可以相对于它们到可以位于封装300的顶表面的中间或者中心的中性点190的方向AR正交布置。焊盘区170中的再分布线150的宽度可以少于这些焊盘区170以外的再分布线150的宽度或者与其相同。
虽然已详细描述本发明及其优点，但是应当理解这里可以做出各种改变、替换和变更而未脱离如所附权利要求限定的本发明的精神和范围。
另外，本申请的范围并不旨在限于在说明书中描述的过程、机器、制造品、物质组成、装置、方法和步骤的具体实施例。如本领域普通技术人员根据本发明的公开内容将容易明白的那样，可以根据本发明利用当前存在的或者以后将开发的执行与这里描述的对应实施例基本上相同功能或者实现基本上相同结果的过程、机器、制造品、物质组成、装置、方法或者步骤。因而，所附权利要求旨在将这样的过程、机器、制造品、物质组成、装置、方法或者步骤包含于其范围内。

Claims (20)

1.一种半导体器件，包括：
再分布层，布置于芯片之上，所述再分布层包括第一再分布线；
隔离层，设置于所述再分布层之上，所述隔离层具有形成第一焊盘区的第一开口；以及
第一互连，位于所述第一开口中并且与所述第一再分布线接触；
其中所述第一焊盘区中的所述第一再分布线与到所述半导体器件的中性点的第一方向正交布置。
2.根据权利要求1所述的半导体器件，其中所述再分布层包括第二再分布线，其中所述隔离层具有第二开口，所述第二开口形成用于所述第二再分布线的第二焊盘区，其中第二互连位于所述第二开口中并且与所述第二再分布线接触，并且其中所述第二再分布线与到所述中性点的第二方向正交布置。
3.根据权利要求1所述的半导体器件，其中所述再分布层包括第二再分布线，其中所述隔离层具有第二开口，所述第二开口形成用于所述第二再分布线的第二焊盘区，其中第二互连位于所述第二开口中并且与所述第二再分布线接触，并且其中所述第二再分布线未与到所述中性点的第二方向正交布置。
4.根据权利要求3所述的半导体器件，其中所述第二焊盘区比所述第一焊盘区更接近所述中性点。
5.根据权利要求1所述的半导体器件，其中所述第一再分布线的第一宽度在所述第一焊盘区中未比在所述第一焊盘区以外更大。
6.根据权利要求1所述的半导体器件，其中所述隔离层比约15μm更厚。
7.根据权利要求1所述的半导体器件，其中所述芯片包括集成电路。
8.一种半导体器件，包括：
再分布层，布置于芯片之上，所述再分布层包括第一再分布线；
隔离层，设置于所述再分布层之上，所述隔离层具有形成第一焊盘区的第一开口；以及
第一互连，位于所述第一开口中并且与所述第一再分布线接触，其中所述第一再分布线的第一宽度在所述第一焊盘区中未比在所述第一焊盘区以外更大。
9.根据权利要求8所述的半导体器件，其中在所述第一焊盘区的所述第一再分布线与到所述半导体器件的中性点的第一方向正交定向。
10.根据权利要求9所述的半导体器件，其中所述再分布层包括：第二再分布线；在所述隔离层中的第二开口，所述第二开口形成第二焊盘区；以及位于所述第二开口中并且与所述第二再分布线接触的第二互连，其中所述第二再分布线的第二宽度在所述第二焊盘区中未比在所述第二焊盘区以外更大。
11.根据权利要求10所述的半导体器件，其中在第二焊盘区的所述第二再分布线与到所述中性点的第二方向正交定向。
12.根据权利要求10所述的半导体器件，其中在第二焊盘区的所述第二再分布线未与到所述中性点的第二方向正交定向。
13.根据权利要求12所述的半导体器件，其中所述第二焊盘区比所述第一焊盘区更接近所述中性点布置。
14.根据权利要求12所述的半导体器件，其中所述第一焊盘区比所述第二焊盘区接近所述半导体器件的边缘定位。
15.根据权利要求8所述的半导体器件，其中所述隔离层比约15μm更厚。
16.一种用于制造半导体器件的方法，所述方法包括：
在芯片之上形成第一再分布线，所述第一再分布线电连接到位于所述芯片的顶表面上的第一芯片焊盘；
在所述再分布线之上形成阻焊层；
通过在所述阻焊层中形成暴露所述第一再分布线的第一开口来形成第一焊盘区，使得所述第一焊盘区中的所述第一再分布线与到所述半导体器件的中性点的第一方向正交定向；并且
将第一互连附着到所述第一焊盘区。
17.根据权利要求16所述的方法，还包括：在所述芯片之上形成第二再分布线，所述第二再分布线电连接到位于所述芯片的所述顶表面上的第二芯片焊盘；通过在所述阻焊层中形成暴露所述第二再分布线的第二开口来形成第二焊盘区；并且将第二互连附着到所述第二焊盘区。
18.根据权利要求17所述的方法，其中所述第二焊盘区中的所述第二再分布线与到所述半导体器件的所述中性点的第二方向正交定向。
19.根据权利要求17所述的方法，其中所述第二焊盘区中的所述第二再分布线未与到所述半导体器件的所述中性点的第二方向正交定向。
20.根据权利要求16所述的方法，其中所述阻焊层比约15μm更厚。
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