TW202402121A - 半導體裝置及雙重屏蔽的方法 - Google Patents
半導體裝置及雙重屏蔽的方法 Download PDFInfo
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Abstract
本發明提供一種半導體裝置,其具有一基板。一第一電組件及第二電組件安置於該基板上方。一導電柱在該第一電組件與第二電組件之間形成於該基板上方。一第一屏蔽層藉由噴射印刷導電材料而形成於該第一電組件及導電柱上方。一第二屏蔽層藉由濺鍍、噴塗或電鍍導電材料而形成於該第一電組件及第二電組件上方。一絕緣層視情況藉由在該第一屏蔽層上方噴射印刷絕緣材料而形成於該第一屏蔽層與第二屏蔽層之間。
Description
本發明大體上係關於半導體製造,且更特定而言,係關於一種半導體裝置及用於半導體封裝之雙重屏蔽的方法。
半導體裝置通常發現於現代電子產品中。半導體裝置執行廣泛範圍之功能,諸如信號處理、高速計算、傳輸及接收電磁信號、控制電子裝置、將日光變換成電以及產生電視顯示器之視覺影像。半導體裝置發現於通信、功率轉換、網路、電腦、娛樂及消費產品領域中。半導體裝置亦可見於軍事應用、航空、汽車、工業控制器及辦公設備。
半導體裝置常常易受可能干擾其操作之電磁干擾(electromagnetic interference;EMI)、射頻干擾(radio frequency interference;RFI)、諧波失真或其他裝置間干擾(諸如電容式、電感式或電導式耦合,亦稱為串擾)影響。高速類比電路,例如射頻(RF)濾波器,或數位電路亦產生干擾。
導電層通常形成於半導體封裝上方以屏蔽封裝內之電子部件免受EMI及其他干擾。屏蔽層在信號到達封裝內之半導體晶粒及離散組件之前吸收EMI,否則此可能會導致裝置故障。屏蔽層亦形成於具有預期會產生EMI之組件的封裝上方,以保護附近裝置。
關於半導體封裝屏蔽之先前技術方法的一個問題為保形屏蔽層並不防止EMI迴路電流流經屏蔽層且在同一半導體封裝之敏感鄰近組件中誘發電場及磁場。僅遍及最敏感晶粒或組件之選擇性屏蔽有效地阻擋雜訊源且增強僅選擇性遮蔽組件之電效能。
然而,在敏感組件上方形成選擇性屏蔽件亦及在整個半導體封裝上方形成保形屏蔽件為複雜且成本高的製程。因此,需要一種改良的半導體裝置及雙重屏蔽的方法。
本發明之一態樣為一種製造半導體裝置之方法,其包含:提供基板;將第一電組件及第二電組件安置於該基板上方;在該第一電組件與第二電組件之間將導電柱安置於該基板上方;藉由噴射印刷導電材料而在該第一電組件及導電柱上方形成第一屏蔽層;及藉由濺鍍、噴塗或電鍍導電材料而在該第一電組件及第二電組件上方形成第二屏蔽層。
本發明之另一態樣為一種製造半導體裝置之方法,其包含:提供基板;將電組件安置於該基板上方;在該基板上方安置導電柱;在該電組件及該導電柱上方形成第一屏蔽層;及在該第一屏蔽層上方形成第二屏蔽層。
本發明之另一態樣為半導體裝置,其包含:基板;電組件,其安置於該基板上方;導電柱,其安置於該基板上方;第一屏蔽層,其形成於該電組件及該導電柱上方;及第二屏蔽層,其形成於該第一屏蔽層上方。
在以下描述中參考圖式於一或多個具體實例中描述本發明,在圖式中,相同標號表示相同或類似元件。雖然本發明係依據用於達成本發明目標之最佳模式來描述,但所屬技術領域中具有通常知識者將瞭解,其意欲涵蓋如可包括於如由所附申請專利範圍及其如由以下揭示內容及圖式支援之等效物所界定的本發明之精神及範圍內的替代方案、修改及等效物。如本文所使用之術語「半導體晶粒」係指詞之單數形式及複數形式兩者,且因此,可指單個半導體裝置及多個半導體裝置兩者。術語「晶粒」與「半導體晶粒」可互換地使用。
通常使用兩種複雜製程來製造半導體裝置:前端製造及後端製造。前段製造涉及在半導體晶圓之表面上形成複數個晶粒。晶圓上之各晶粒含有主動及被動電組件,該等電組件電連接以形成功能性電路。諸如電晶體及二極體等主動電組件具有控制電流之流動的能力。諸如電容器、電感器及電阻器之被動電組件在執行電路功能所必需之電壓與電流之間建立關係。
後段製造指將成品晶圓切割或單體化(singulate)成個別半導體晶粒,且封裝半導體晶粒以用於結構支撐、電互連及環境隔離。為了單體化半導體晶粒,沿著稱作鋸切道或劃線之晶圓之非功能性區刻劃及打破晶圓。使用雷射切割工具或鋸片來使晶圓單體化。在單體化之後,將個別半導體晶粒安裝至封裝基板,該封裝基板包括接腳或接觸襯墊以用於與其他系統組件互連。隨後將形成於半導體晶粒之上的接觸襯墊連接至封裝內之接觸襯墊。可與導電層、凸塊、柱形凸塊、導電膏、接合線或其他適合的互連結構進行電連接。囊封體或其他模製化合物沉積於封裝上方以提供實體支撐及電隔離。接著將成品封裝插入至電系統中,且使半導體裝置之功能性可用於其他系統組件。
圖1a展示具有基底基板材料102之半導體晶圓100,該基底基板材料諸如矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽或其他塊狀半導體材料。複數個半導體晶粒或組件104形成於由如上文所描述之非主動晶粒間晶圓區域或鋸切道106分離之晶圓100上。鋸切道106提供切割區域以將半導體晶圓100單體化成個別半導體晶粒104。在一個具體實例中,半導體晶圓100具有100至450公釐(mm)之寬度或直徑。
圖1b展示半導體晶圓100之一部分的橫截面視圖。各半導體晶粒104具有背部或非主動表面108及主動表面110,該背部或非主動表面108及該主動表面110含有實施為主動裝置、被動裝置、導電層及介電層之類比或數位電路,該等主動裝置、被動裝置、導電層及介電層形成於晶粒內或上方且根據晶粒之電氣設計及功能而電互連。舉例而言,電路可包括形成於主動表面110內之一或多個電晶體、二極體及其他電路元件以實施類比電路或數位電路,諸如數位信號處理器(digital signal processor;DSP)、ASIC、記憶體或其他信號處理電路。半導體晶粒104亦可含有諸如電感器、電容器及電阻器…等之積體被動裝置(integrated passive devices;IPD)以用於RF信號處理。半導體晶圓100之背表面108可藉由機械研磨或蝕刻製程進行視情況選用之背部研磨操作以移除基底材料102之一部分且減小半導體晶圓100及半導體晶粒104之厚度。
導電層112使用PVD、CVD、電解電鍍、無電極電鍍製程或其他適合之金屬沉積製程而形成於主動表面110上方。導電層112包括鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他合適之導電材料之一或多個層。導電層112作為電連接至主動表面110上之電路的接觸襯墊操作。
導電層112可形成為與半導體晶粒104之邊緣相距第一距離並排安置之接觸襯墊,如圖1b中所示。替代地,導電層112可形成為接觸襯墊,該等接觸襯墊在多個列中偏移以使得第一列接觸襯墊安置成距晶粒之邊緣第一距離,且第二列接觸襯墊與第一列交替安置成距晶粒之邊緣第二距離。導電層112表示形成於具有用於後續電氣互連至較大系統之接觸襯墊的半導體晶粒104上方之最後導電層。然而,可存在形成於主動表面110上之實際半導體裝置與接觸襯墊112之間的一或多個中間導電層及絕緣層以用於信號路由。
使用蒸發、電解電鍍、無電極電鍍、落球或網版印刷製程將導電凸塊材料沉積於導電層112上方。凸塊材料可為Al、Sn、Ni、Au、Ag、鉛(Pb)、鉍(Bi)、Cu、焊料及其組合,其具有視情況選用之焊劑溶液。舉例而言,凸塊材料可為共晶Sn/Pb、高鉛焊料或不含鉛焊料。使用適合附接或接合製程將凸塊材料接合至導電層112。在一個具體實例中,凸塊材料藉由將材料加熱超過其熔點而回焊以形成導電球或凸塊114。導電凸塊114視情況形成於具有潤濕層、阻障層及黏著層之凸塊下金屬化物(under-bump metallization;UBM)上方。導電凸塊114亦可壓縮接合或熱壓接合至導電層112。導電凸塊114表示可形成於導電層112上方以用於電連接至基板之一種類型的互連結構。互連結構亦可使用接合線、導電膏、柱形凸塊、微型凸塊或其他電互連件。
在圖1c中,半導體晶圓100使用鋸片或雷射切割工具118藉由鋸切道106單體化成個別半導體晶粒104。可檢測及電測試個別半導體晶粒104以用於已知良好晶粒(know-good die;KGD)後單體化之識別。
圖2a至圖2g示出形成具有半導體晶粒104之半導體封裝150。在一些具體實例中,封裝150為系統級封裝(system-in-package;SiP)模組。圖2a展示基板152之部分橫截面視圖。雖然僅展示單個基板152,但通常在共同載體上使用本文中針對單個單元描述但整體執行之相同步驟來處理數百或數千個基板。基板152亦可作為多個單元之單個較大基板開始,該等單元在製造製程期間或之後自彼此單體化。
基板152包括與一或多個導電層156交錯之一或多個絕緣層154。在一個具體實例中,絕緣層154為其中導電層156在頂表面及底表面上方圖案化之芯絕緣板,例如敷銅層板基板。導電層156亦包括經由絕緣層154電耦接之導通孔。基板152可包括彼此交錯之任何數目個導電層及絕緣層。焊料遮罩或鈍化層可形成於基板152之任一側上方。在其他具體實例中,任何適合類型之基板或引線框用於基板152。
圖2a中之半導體封裝150上已安裝有半導體晶粒104、離散組件160及導電柱162,以及任何其他離散主動或被動組件、半導體晶粒或封裝之所欲功能性所要的其他組件。在導電層156與半導體晶粒104之間回焊焊料凸塊114,以將晶粒機械且電連接至基板152。任何類型及數目之組件可安裝至如圖2a中所說明之基板152之頂表面、底表面或兩者上,且亦以任何合適的次序及組態嵌入於基板內。
如所說明之離散組件160僅為代表性的。可使用任何類型及數目及組件。導電柱162提供半導體晶粒104與離散組件160之間的電磁干擾(EMI)的側向阻擋。導電柱162典型地但未必經由基板152耦接至接地以輔助EMI減少。導電柱162可為圍繞半導體晶粒104分佈之複數個離散柱,或一直圍繞半導體晶粒持續延伸之單件材料。導電柱162由鋁、銅、鋼、鈦、金、其他金屬或其組合或合金形成。導電柱162分開地形成且接著經拾取且置放至基板152上。在其他具體實例中,導電柱162使用光阻層作為經移除之遮罩而直接形成於基板152上。
在將半導體晶粒104、離散組件160、導電柱162及任何其他所要電組件安裝至基板152上之後,該等組件藉由囊封體或模製化合物170囊封。囊封體170使用糊狀物印刷、壓縮模製、轉移模製、液體囊封體模製、真空層壓、旋塗或另一合適之施加器而沉積於基板152、半導體晶粒104、離散組件160及導電柱162上方。囊封體170可為聚合物複合材料,諸如環氧樹脂、環氧丙烯酸酯或具有或不具有填充劑之聚合物。囊封體170不導電、提供結構支撐且在環境上保護半導體裝置免受外部元件及污染物影響。囊封體170完全覆蓋半導體晶粒104、離散組件160及導電柱162之頂表面及側表面。囊封體170填充基板152與半導體晶粒104或離散組件160之間的任何間隙,除非使用單獨底膠。
在圖2c中,囊封體170的一部分藉由用機械研磨機172背部研磨而移除。在其他具體實例中,使用化學蝕刻、化學機械平坦化(CMP)或另一適合的平坦化方法。研磨製程暴露導電柱162且留下與如圖2d中所展示之導電柱的頂表面176共面的囊封體170的頂表面174。在其他具體實例中,囊封體170在形成導電柱162之前沉積。在彼情況下,導電柱162藉由穿過囊封體170鑽孔至基板152且用導電材料填充所得通孔或孔洞而形成。在一個具體實例中,噴射印刷用於在囊封體170中形成導電柱162。
在圖2e中,選擇性屏蔽層180藉由金屬墨水之噴射印刷形成於半導體晶粒104及導電柱162上方。噴射印刷由圖2e中之噴嘴182表示。噴嘴182可用以形成呈任何任意圖案之選擇性屏蔽層180。導電墨水印刷可為電流體動力學(electrohydrodynamic;EHD)噴射印刷,其中在製造期間用作封裝150之載體的噴嘴與導電板之間的電場用於導引經印刷之導電墨水。在一些具體實例中,雷射轉印用於形成選擇性屏蔽層180。在雷射轉印中,金屬塗佈之透明膜安置於其中金屬朝向封裝定向的半導體封裝150上方。藉由將雷射聚焦至需要印刷選擇性屏蔽層180之膜上而將金屬自膜轉移至半導體封裝150。在其他具體實例中使用氣凝膠噴塗或另一類型之導電材料印刷。印刷材料為銅、鋼、鋁、金、鈦、其組合或任何其他適合之材料。
選擇性屏蔽層180形成為延伸至各導電柱162且填充導電柱之間的表面174的區域的材料薄片。選擇性屏蔽層180直接形成於導電柱162之頂表面176上。選擇性屏蔽層180結合導電柱162形成特定用於半導體晶粒104之EMI屏蔽件或對EMI尤其敏感之一或多個其他組件。選擇性屏蔽層180可完全填充導電柱162之間的覆蓋面積,或可形成有孔洞、條帶或其他不連續性。
選擇性屏蔽層180僅形成於導電柱162之間定位有敏感組件之區域上方且不形成於所討論之區域外部。具有特定於半導體晶粒104之屏蔽層的目的為減少在選擇性屏蔽層180中自封裝150中之其他處誘發且導致半導體晶粒中之干擾的EMI迴路電流,或反之亦然。選擇性屏蔽層180可出於多種原因在導電柱162之間的區域外部延伸,但使選擇性屏蔽層180在其他組件上方延伸可藉由增大選擇性屏蔽內及外部的組件之間的EMI迴路電流而降低選擇性屏蔽層的功效。
在圖2f中,絕緣層190形成於選擇性屏蔽層180上方。絕緣層190用噴嘴182或第二噴嘴噴射印刷以分離導電材料及絕緣材料之印刷。在其他具體實例中,絕緣層190藉由雷射轉印或另一類型之絕緣層印刷而印刷。絕緣層190含有二氧化矽(SiO
2)、氮化矽(Si
3N
4)、氮氧化矽(SiON)、五氧化二鉭(Ta
2O
5)、氧化鋁(Al
2O
3)、阻焊劑、聚醯亞胺(PI)、苯并環丁烯(BCB)、聚苯并唑(PBO)或具有類似絕緣及結構特性之其他材料的一或多個層。絕緣層190完全覆蓋選擇性屏蔽層180且向下延伸以在選擇性屏蔽層周圍實體地接觸囊封體170。
選擇性屏蔽層180及絕緣層190典型地在條帶級(strip level)形成,意謂封裝150保留為一起形成於基板152上之封裝條帶,以作為大的未單體化條帶,或作為單體化封裝於共用條帶載體上。噴射印刷相對於運用材料覆蓋單元之整個面板且接著使用光微影或另一合適機制來圖案化層的先前技術方法降低在僅導電柱162之間的區域上方形成選擇性屏蔽層180及絕緣層190的複雜度及成本。
若半導體封裝150形成為單元條帶,則在圖2g中之整個封裝上方形成保形屏蔽層200之前對條帶進行單體化。使用任何適合之金屬沉積技術來形成保形屏蔽層200,例如,化學氣相沉積、物理氣相沉積、其他濺鍍方法、噴塗或電鍍。濺鍍材料可為銅、鋼、鋁、金、其組合或任何其他合適材料。保形屏蔽層200完全覆蓋囊封體170、基板152及絕緣層190之暴露表面。導電層156可在基板152之側面處暴露以經由基板將屏蔽層200連接至地面。
絕緣層190實體上且電隔離選擇性屏蔽層180與保形屏蔽層200。保持選擇性屏蔽層180與保形屏蔽件200實體上隔離減少由離散組件160或選擇性屏蔽件外部之其他組件產生之保形屏蔽件200中的EMI迴路電流歸因於特定針對於半導體晶粒之額外選擇性屏蔽而對半導體晶粒104具有的效應。相反,藉由選擇性屏蔽層180中之半導體晶粒104產生的EMI迴路電流藉由直接分流至接地而非保形屏蔽層200而對離散組件160具有減少之效應。噴射印刷選擇性屏蔽層180及絕緣層190降低製造之成本及複雜度。
圖3將另一具體實例展示為半導體封裝210。除了絕緣層190並不形成於選擇性屏蔽層180與保形屏蔽層200之間以外,半導體封裝210以與半導體封裝150實質上相同的方法形成。在無絕緣層190之情況下,保形屏蔽層200直接形成於選擇性屏蔽層180上。在屏蔽層之間無實體隔離之情況下,EMI迴路電流在兩者之間流動。然而,與僅具有保形屏蔽層200相比,至導電柱162之接地的額外路徑仍有助於在較大程度上將EMI迴路電流分流至接地。選擇性屏蔽層180結合保形屏蔽層200之額外厚度亦有助於屏蔽半導體晶粒104,尤其即使在不存在絕緣層190之實體隔離的情況下亦如此。
圖4a至圖4e說明形成凹陷於半導體封裝220內之選擇性屏蔽層。在圖4a中,囊封體170如在圖2b中沉積於導電柱162上方。凹部222藉由雷射切除、化學蝕刻或另一合適的製程形成至圖4b中之囊封體170中。凹部222向下形成至導電柱162,使得各導電柱之頂表面176暴露於凹部內。凹部222遵循與上文針對選擇性屏蔽層180所論述相同之佔據面積。
在圖4c中,選擇性屏蔽層230形成於凹部222內。選擇性屏蔽層230藉由噴射印刷、藉由濺鍍穿過光阻遮罩或藉由另一合適製程形成。可使用上文針對選擇性屏蔽層180所論述之方法及材料中的任一者來形成選擇性屏蔽層230。選擇性屏蔽層230在一個具體實例中填充凹部222之佔據面積,且實體地接觸各導電柱162之頂表面176。在選擇性屏蔽層230並不完全填充導電柱162之間的覆蓋面積之具體實例中,凹部222仍可藉由視需要形成有條帶、孔洞或其他不連續性之選擇性屏蔽層230完全填充覆蓋面積。替代地,凹部222可形成有用於選擇性屏蔽層230之所要最終形狀,且接著使其佔據面積完全由噴射印刷導電材料填充。選擇性屏蔽層230凹陷於囊封體170之頂表面232下方。
在圖4d中,凹部222中之剩餘體積填充有絕緣層240。絕緣層240以與上述絕緣層190類似之方式且由與上述絕緣層190類似之材料形成。絕緣層240可經噴射印刷以藉由與囊封體170之頂表面232共面之表面填充凹部222。在一些具體實例中,凹部222由絕緣層240過度填充,且接著封裝222經背部研磨以使囊封體170與絕緣層240共面。在其他具體實例中,凹部222未完全被填充。
在圖4e中,保形屏蔽層250形成於封裝220上方,從而完全覆蓋封裝之頂表面及側表面,在封裝220形成為裝置之面板具體實例中,面板經單體化以使封裝彼此分離且暴露封裝之側表面以用於屏蔽。屏蔽層250以與上述保形屏蔽層200類似之方式且由與上述保形屏蔽層200類似之材料形成。封裝220在僅半導體晶粒104或其他敏感組件上方提供選擇性屏蔽層230,以及在整個封裝上方提供保形屏蔽層250。選擇性屏蔽層230減少封裝220之不同區域之間的EMI迴路電流之效應。選擇性屏蔽層230凹陷於囊封體170內,使得封裝220之頂表面在封裝之整個佔據面積上為平坦的。在另一個具體實例中,並不使用絕緣層240,且保形屏蔽層250直接形成於選擇性屏蔽層230上,類似於圖3之具體實例但選擇性屏蔽層凹陷。選擇性屏蔽層230可視需要形成有與囊封體170共面之表面以保持封裝220之頂表面平坦。
圖5a及圖5b說明將例如半導體封裝150之上文所描述的半導體封裝整合至較大電子裝置340中。圖5a說明作為電子裝置340之部分安裝至印刷電路板(printed circuit board;PCB)或其他基板342上之半導體封裝150的部分橫截面。凸塊346在任何所需製造階段類似於上述凸塊114之描述而形成,且經回焊至PCB 342之導電層344上以將半導體封裝150實體地附接且電連接至PCB。在其他具體實例中,使用熱壓縮或其他合適之附接及連接方法。在一些具體實例中,在半導體封裝150與PCB 342之間使用黏著劑或底部填充層。半導體晶粒104經由基板152電耦接至導電層344。
圖5b說明包括PCB 342之電子裝置340,其中複數個半導體封裝(包括半導體封裝150)安裝於PCB之表面上。視應用而定,電子裝置340可具有一種類型之半導體封裝或多種類型之半導體封裝。電子裝置340可為使用半導體封裝執行一或多個電功能之獨立系統。替代地,電子裝置340可為較大系統之子組件。舉例而言,電子裝置340可為平板電腦、蜂巢式電話、數位攝影機、通信系統或其他電子裝置之部分。電子裝置340亦可為圖形卡、網路介面卡或插入至電腦中之另一信號處理卡。半導體封裝可包括微處理器、記憶體、ASIC、邏輯電路、類比電路、RF電路、離散主動或被動裝置或其他半導體晶粒或電組件。
在圖5b中,PCB 342提供通用基板以用於安裝於PCB上之半導體封裝的結構支撐及電互連。使用蒸鍍、電解電鍍、無電極電鍍、網版印刷或其他合適之金屬沉積製程在PCB 342之表面上方或層內形成導電信號跡線344。信號跡線344提供半導體封裝、經安裝組件及其他外部系統或組件之間的電通信。視需要,跡線344亦將電力連接及接地連接提供至半導體封裝。
在一些具體實例中,半導體裝置具有兩個封裝級。第一級封裝為用於將半導體晶粒機械及電附接至中間基板之技術。第二級封裝涉及將中間基板機械及電附接至PCB 342。在其他具體實例中,半導體裝置可僅具有第一級封裝,其中晶粒直接機械地且電安裝至PCB 342。
出於說明之目的,包括接合線封裝346及倒裝晶片348之若干類型的第一級封裝展示於PCB 342上。另外,若干類型的第二級封裝,包括球狀柵格陣列(ball grid array;BGA)350、凸塊晶片載體(bump chip carrier;BCC)352、平台柵格陣列(land grid array;LGA)356、多晶片模組(multi-chip module;MCM)358、四邊扁平無引腳封裝(quad flat non-leaded;QFN)360、四邊扁平封裝件362及嵌入式晶圓級球狀柵格陣列(embedded wafer level ball grid array;eWLB)364,經展示為連同半導體封裝150一起安裝在PCB 342上。導電跡線344將安置在PCB 342上之各種封裝及組件電耦接至半導體封裝150,從而使半導體封裝150內之組件可用於PCB上之其他組件。
視系統要求而定,經組態以具有第一級封裝式樣及第二級封裝式樣以及其他電子組件之任何組合的半導體封裝之任何組合可連接至PCB 342。在一些具體實例中,電子裝置340包括單一附接之半導體封裝,而其他具體實例需要多個互連之封裝。藉由在單個基板上方組合一或多個半導體封裝,製造商可將預製組件併入至電子裝置及系統中。由於半導體封裝包括複雜功能性,因此可使用較不昂貴組件及流線型的製造製程來製造電子裝置。所得裝置不大可能發生故障且製造起來不太昂貴,由此降低了消費者成本。
儘管已詳細說明本發明之一或多個具體實例,但所屬領域中具有通常知識者將瞭解,可在不脫離如以下申請專利範圍表中所闡述之本發明之範疇的情況下對所述具體實例作出修改及調適。
100:半導體晶圓
102:基底基板材料
104:半導體晶粒
106:鋸切道
108:非主動表面
110:主動表面
112:導電層
114:導電凸塊
118:雷射切割工具
150:半導體封裝
152:基板
154:絕緣層
156:導電層
160:離散組件
162:導電柱
170:囊封體
172:機械研磨機
174:頂表面
176:頂表面
180:選擇性屏蔽層
182:噴嘴
190:絕緣層
200:保形屏蔽層
210:半導體封裝
222:凹部
230:選擇性屏蔽層
232:頂表面
240:絕緣層
250:保形屏蔽層
340:電子裝置
342:基板/PCB
344:導電層/導電信號跡線
346:接合線封裝
346:凸塊
348:倒裝晶片
350:球狀柵格陣列
352:凸塊晶片載體
356:平台柵格陣列
358:多晶片模組
360:四邊扁平無引腳封裝
362:四邊扁平封裝
364:嵌入式晶圓級球狀柵格陣列
[圖1a]至[圖1c]說明具有由鋸切道分隔開之複數個半導體晶粒的半導體晶圓;
[圖2a]至[圖2g]說明形成具有選擇性屏蔽之雙重屏蔽層;
[圖3]說明在屏蔽層之間無隔離的情況下的雙重屏蔽之具體實例;
[圖4a]至[圖4e]說明在凹部中形成選擇性EMI屏蔽;且
[圖5a]及[圖5b]說明將雙重屏蔽半導體封裝整合至電子裝置中。
104:半導體晶粒
112:導電層
114:導電凸塊
150:半導體封裝
152:基板
154:絕緣層
156:導電層
160:離散組件
162:導電柱
170:囊封體
176:頂表面
180:選擇性屏蔽層
190:絕緣層
200:保形屏蔽層
Claims (15)
- 一種製造半導體裝置之方法,其包含: 提供基板; 將第一電組件及第二電組件安置於該基板上方; 在該第一電組件與該第二電組件之間將導電柱安置於該基板上方; 藉由噴射印刷導電材料而在該第一電組件及該導電柱上方形成第一屏蔽層;及 藉由濺鍍、噴塗或電鍍導電材料而在該第一電組件及該第二電組件上方形成第二屏蔽層。
- 如請求項1之方法,其進一步包括在該第一屏蔽層與該第二屏蔽層之間形成絕緣層。
- 如請求項2之方法,其進一步包括藉由噴射印刷形成該絕緣層。
- 如請求項1之方法,其進一步包括: 將囊封體沉積於該基板、該第一電組件及該第二電組件上方;及 在該囊封體之凹部中形成該第一屏蔽層。
- 如請求項1之方法,其進一步包括直接在該第一屏蔽層上形成該第二屏蔽層。
- 如請求項1之方法,其進一步包括在形成該第一屏蔽層之後且在形成該第二屏蔽層之前單體化該基板。
- 一種製造半導體裝置之方法,其包含: 提供基板; 將電組件安置於該基板上方; 在該基板上方安置導電柱; 在該電組件及該導電柱上方形成第一屏蔽層;及 在該第一屏蔽層上方形成第二屏蔽層。
- 如請求項7之方法,其進一步包括在該第一屏蔽層與該第二屏蔽層之間形成絕緣層。
- 如請求項7之方法,其進一步包括藉由噴射印刷形成該第一屏蔽層。
- 如請求項9之方法,其進一步包括藉由濺鍍、噴塗或電鍍形成該第二屏蔽層。
- 一種半導體裝置,其包含: 基板; 電組件,其安置於該基板上方; 導電柱,其安置於該基板上方; 第一屏蔽層,其形成於該電組件及該導電柱上方;及 第二屏蔽層,其形成於該第一屏蔽層上方。
- 如請求項11之半導體裝置,其進一步包括形成於該第一屏蔽層與該第二屏蔽層之間的絕緣層。
- 如請求項11之半導體裝置,其中該第一屏蔽層選擇性地形成於該電組件及該導電柱上方。
- 如請求項13之半導體裝置,其中該第二屏蔽層為保形屏蔽層。
- 如請求項11之半導體裝置,其中該第二屏蔽層在該基板之一側表面上方延伸。
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