JP5350745B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
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- JP5350745B2 JP5350745B2 JP2008270530A JP2008270530A JP5350745B2 JP 5350745 B2 JP5350745 B2 JP 5350745B2 JP 2008270530 A JP2008270530 A JP 2008270530A JP 2008270530 A JP2008270530 A JP 2008270530A JP 5350745 B2 JP5350745 B2 JP 5350745B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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Description
図2は、本発明の第1の実施の形態に係る半導体装置の断面図である。
貫通溝47は、第1の実装領域と第2の実装領域との間に位置する部分の基板21を貫通するように形成されている。貫通溝47は、熱遮断部材32を配設するための溝である。貫通溝47の幅Aは、例えば、200μmとすることができる。
図22は、本発明の第2の実施の形態に係る半導体装置の断面図である。図22において、第1の実施の形態の半導体装置10と同一構成部分には同一符号を付す。
図33は、本発明の第3の実施の形態に係る半導体装置の断面図である。図33において、第1の実施の形態の半導体装置10と同一構成部分には同一符号を付す。
図49は、本発明の第4の実施の形態に係る半導体装置の断面図である。図49において、第3の実施の形態の半導体装置90と同一構成部分には同一符号を付す。
図58は、本発明の第5の実施の形態に係る半導体装置の断面図である。図58において、第2の実施の形態の半導体装置80と同一構成部分には同一符号を付す。
11,71,81,91,111,131 配線基板
12,13 電子部品
15,16 外部接続端子
17,18 アンダーフィル樹脂
21 基板
21A,22A,55A,94B,115A,116B 上面
21B,23A,55B,94A,115B,116A 下面
22,23,93,94,115,116 絶縁膜
25,26 貫通電極
25A,25B,26A,26B,32A,32B,135A 端面
28,29 パッド
28A,29A,36A,37A 接続面
31 配線
32,74,135 熱遮断部材
33,34,96,97 ビア
36,37 外部接続用パッド
39,41 ソルダーレジスト層
39A,39B,48,49,57,58,93A,93B 開口部
45,46,118,119 貫通孔
47,61A,73 貫通溝
55 基材
59,133 溝
61 マスク
65 導電部材
101 フィルム
A,B,E,I,K 幅
C 基板形成領域
D 切断領域
F 第1の実装領域
G 第2の実装領域
J 深さ
Claims (8)
- 半導体材料からなる基板と、前記基板の第1の面側に設けられ、第1の電子部品が実装される第1のパッドと、前記基板の第1の面側に設けられ、前記第1の電子部品より動作時の発熱量が大きい第2の電子部品が実装される第2のパッドと、
前記基板を貫通すると共に、一方の端部が前記第1のパッドと電気的に接続された第1の貫通電極と、
前記基板を貫通すると共に、一方の端部が前記第2のパッドと電気的に接続された第2の貫通電極と、を有する配線基板であって、
前記第1の電子部品が実装される第1の実装領域と前記第2の電子部品が実装される第2の実装領域との間に位置する部分の前記基板に、該基板を貫通する貫通溝を設けると共に、前記貫通溝に熱遮断部材を設け、
前記貫通溝を、前記第2の実装領域に対応する部分の前記基板を囲むように設け、
前記貫通溝の前記基板の第1の面側の端部又は第1の面側とは反対側の端部の少なくとも一方は、前記基板の第1の面及びその反対面並びに前記貫通溝の内側面に設けられ前記貫通溝上に延在する絶縁膜により塞がれていることを特徴とする配線基板。 - 前記絶縁膜は、前記基板の表面及び前記熱遮断部材上に形成され、
前記絶縁膜を介して、前記第1のパッド、前記第2のパッド、及び前記第1のパッドと前記第2のパッドと接続された配線が形成されていることを特徴とする請求項1記載の配線基板。 - 前記基板には、前記基板を貫通する貫通孔が形成され、
前記絶縁膜は、前記貫通孔の内側面にも形成され、
前記貫通電極は、前記貫通孔内に前記絶縁膜を介して設けられていることを特徴とする請求項1又は2記載の配線基板。 - 前記貫通溝は、前記第2の実装領域に対応する部分の前記基板を囲むよう、連続した額縁形状に形成されていることを特徴とする請求項1ないし3のうち、いずれか1項記載の配線基板。
- 前記貫通溝は、前記第2の実装領域に対応する部分の前記基板を囲むよう、複数配置されていることを特徴とする請求項1ないし3のうち、いずれか1項記載の配線基板。
- 前記絶縁膜は酸化膜からなることを特徴とする請求項1ないし5のうち、いずれか1項記載の配線基板。
- 前記熱遮断部材の熱伝導率は、0.1〜1.0W/m・Kであることを特徴とする請求項1ないし6のうち、いずれか1項記載の配線基板。
- 前記熱遮断部材の材料は、樹脂であることを特徴とする請求項1ないし7のうち、いずれか1項記載の配線基板。
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US9048233B2 (en) * | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
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US10192810B2 (en) * | 2013-06-28 | 2019-01-29 | Intel Corporation | Underfill material flow control for reduced die-to-die spacing in semiconductor packages |
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