TWI590726B - 電子封裝件、封裝載板及此封裝載板的製造方法 - Google Patents

電子封裝件、封裝載板及此封裝載板的製造方法 Download PDF

Info

Publication number
TWI590726B
TWI590726B TW103139744A TW103139744A TWI590726B TW I590726 B TWI590726 B TW I590726B TW 103139744 A TW103139744 A TW 103139744A TW 103139744 A TW103139744 A TW 103139744A TW I590726 B TWI590726 B TW I590726B
Authority
TW
Taiwan
Prior art keywords
layer
pattern
support plate
package carrier
manufacturing
Prior art date
Application number
TW103139744A
Other languages
English (en)
Other versions
TW201524292A (zh
Inventor
卓恩民
康政畬
Original Assignee
群成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 群成科技股份有限公司 filed Critical 群成科技股份有限公司
Publication of TW201524292A publication Critical patent/TW201524292A/zh
Application granted granted Critical
Publication of TWI590726B publication Critical patent/TWI590726B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145Organic substrates, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

電子封裝件、封裝載板及此封裝載板的製造方法
本發明乃是關於一種電子封裝件、封裝載板及此封裝載板的製造方法。
在一般的半導體元件製造流程中,當晶圓內部製作好微型化電路之後,晶圓會被切割成多塊裸晶(die)。之後,這些裸晶會進行封裝,並分別裝設(mounted)在多塊封裝載板上,以形成多個電子封裝件。一般而言,上述封裝載板的結構與電路板相似,即封裝載板通常包括至少兩層線路層以及至少一層夾合在兩層線路層之間的核心層(core),其中核心層例如是已固化的膠片。因此,在目前常見的電子封裝件中,除了裸晶之外,電子封裝件一般會具有至少兩層線路層以及至少一層絕緣層(即核心層)。
本發明提供一種封裝載板,其能裝設至少一個電子元件。
本發明提供一種製造方法,其用來製造上述封裝載板。
本發明提供一種電子封裝件,其包括上述封裝載板。
本發明提出一種封裝載板的製造方法。在此製造方法中,提供一承載板與一導體層,其中導體層位在承載板上。接著,在導體層上形成一絕緣圖案,其中絕緣圖案暴露部分導體層。另外,提供一支撐板。接著,固定絕緣圖案於支撐板內。在絕緣圖案固定在支撐板之後,移除承載板,並保留導體層。在移除承載板之後,圖案化導體層,以形成一線路層。
本發明提出一種封裝載板,包括一線路層以及一絕緣圖案。線路層包括至少一連接墊與一裝設墊,其中裝設墊用於供一電子元件裝設,而連接墊用於電性連接電子元件。絕緣圖案與線路層堆疊及連接。
本發明提出一種電子封裝件,包括上述封裝載板、一電子元件以及一模封層。電子元件裝設於裝設墊上,並且電性連接至少一連接墊,其中線路層位於電子元件與絕緣圖案之間。模封層覆蓋線路層與電子元件。
基於上述,本發明利用支撐板與承載板來製作封裝載板。不同於習知技術而言,本發明的製造方法可以製造出不具核心層的封裝載板與電子封裝件。
為了瞭解本發明的技術特徵,請參閱以下實施方式與圖式。利用圖式與實施方式的內容,本發明所屬技術領域中具有通常知識者應可瞭解本發明的技術特徵。然而,以下實施方式與圖式僅提供舉例說明,並非用來限制本發明的申請專利範圍。
20‧‧‧壓印模板
40‧‧‧刀具
110‧‧‧導體層
110s、111s‧‧‧表面
111‧‧‧線路層
112‧‧‧連接墊
113‧‧‧裝設墊
120‧‧‧承載板
121‧‧‧離型層
122、124、211、212‧‧‧金屬層
123‧‧‧介電層
131‧‧‧絕緣圖案
131a、131b‧‧‧開口
132‧‧‧接合材料
140‧‧‧保護層
200、200’‧‧‧支撐板
210‧‧‧板材
213‧‧‧接合層
220‧‧‧可塑性板材
300、500‧‧‧工作板材
301、501‧‧‧基板條
311、312、511、512‧‧‧封裝載板
400、401、600、601‧‧‧電子封裝件
410‧‧‧電子元件
420‧‧‧黏著層
430‧‧‧模封層
D1‧‧‧深度
P1‧‧‧壓印圖案
P2‧‧‧凹陷圖案
T1、T2、T3‧‧‧厚度
圖1A至圖3E繪示本發明一實施例的封裝載板的製造方法的示意圖。
圖4A至圖4C繪示本發明其中一實施例的電子封裝件的製造方法的示意圖。
圖5A至圖5F繪示本發明另一實施例的封裝載板的製造方法的示意圖。
圖6A至圖6C繪示本發明其中一實施例的電子封裝件的製造方法的示意圖。
圖1A至圖3E繪示本發明一實施例的封裝載板的製造方法的示意圖,而圖1A至圖1C繪示絕緣圖案在導體層上的形成。請參閱圖1A與圖1B,其中圖1B是圖1A中沿線I-I剖面所繪示的剖 面示意圖。在本實施例的封裝載板的製造方法中,提供導體層110以及承載板120,其中導體層110堆疊在承載板120上,並且可為金屬箔片,其例如是銅箔、銀箔、鋁箔或合金箔。
承載板120包括主體板(未標示)與離型層121,而離型層121配置在導體層110與主體板之間,其中主體板可以是陶瓷板、金屬板或是含有多種材料的複合材料板。在圖1B的實施例中,主體板為複合材料板,並且具有多層結構(multilayer)。具體而言,主體板可以包括介電層123、金屬層122與124,其中介電層123配置並連接在金屬層122與124之間,而離型層121配置在金屬層122與導體層110之間。
主體板可以是銅箔基板(Copper Clad Laminate,CCL),而導體層110可以是銅箔、銀箔、鋁箔或合金箔等金屬箔片,介電層123可以是已經固化的膠片(prepreg)、樹脂層或陶瓷層。此外,在本實施例中,導體層110的厚度T1可以大於金屬層122的厚度T2。舉例而言,導體層110可以是厚度為18微米的銅箔,而金屬層122則可以是厚度為3微米的銅箔。
導體層110可經由離型層121連接承載板120。不過,導體層110與離型層121之間的結合力偏弱,以至於導體層110容易受外力的施加而從離型層121分離。舉例而言,導體層110可以用手從離型層121剝離。另外,離型層121可以是金屬片或高分子膜層,其中此金屬片例如是合金片。
請參閱圖1C,接著,在導體層110上形成絕緣圖案131,而絕緣圖案131的厚度T3可以介於10微米至50微米之間。絕緣圖案131局部覆蓋導體層110的表面110s,並且暴露部分導體層110。此外,絕緣圖案131具有至少一個開口。以圖1C為例,絕緣圖案131具有開口131a與開口131b,其中開口131a與131b皆延伸至表面110s。絕緣圖案131可為防焊層,其例如是防焊濕膜或防焊乾膜,且絕緣圖案131可經由噴墨(inkjet)或貼片 (lamination)而形成。此外,防焊層可具有感光性,而開口131a與131b可經由曝光(exposure)及顯影(development)而形成。
在形成絕緣圖案131之後,接著,在絕緣圖案131所暴露的部分導體層110的表面110s上形成接合材料132,其中接合材料132可以是焊料、金屬層或有機助焊層(Organic Solderability Preservatives,OSP)。焊料例如是錫膏、銀膠或銅膏,而金屬層例如是鎳層、金層、銀層、鈀層、鎳金層或鎳鈀金層,其中鎳金層與鎳鈀金層兩者皆為多層膜。
焊料的形成方法可以是塗佈(applying)或點膠(dispensing)。金屬層的形成方法可以是沉積(deposition),其例如是化學氣相沉積(Chemical Vapor Deposition,CVD)、物理氣相沉積(Physical Vapor Deposition,PVD)、電鍍(electroplating)或無電電鍍(electroless plating),其中物理氣相沉積例如是蒸鍍(evaporation)或濺鍍(sputtering)。有機助焊層的形成方法可以是浸泡(dipping)。
圖2A至圖2C繪示本實施例的封裝載板的製造方法所提供的支撐板200(請參閱圖2C),並且更進一步地繪示形成支撐板200的方法。請參閱圖2A與圖2B,在形成支撐板200的方法中,首先,提供具有壓印圖案P1的壓印模板(imprint template)20。接著,利用壓印模板20,將金屬層211壓合於可塑性板材220上,以使金屬層211連接可塑性板材220。壓印圖案P1會在金屬層211上壓印出凹陷圖案P2。
可塑性板材220可具有熱固性(thermal-curing),而在金屬層211沒有壓合於可塑性板材220之前,可塑性板材220可以是未固化的膠片,也就是處於B狀態(B stage)的膠片。因此,在金屬層211壓合於可塑性板材220上的期間,可以加熱可塑性板材220,以固化可塑性板材220。
此外,在壓合金屬層211的過程中,也可以一起壓合另一片金屬層212,其中可塑性板材220夾合於金屬層211與金屬層212 之間,而金屬層211與212兩者可為金屬箔片,其例如是銅箔、銀箔、鋁箔或合金箔。不過,在其他實施例中,也可只壓合金屬層211於可塑性板材220上,而不壓合金屬層212等其他金屬層。
請參閱圖2B與圖2C,在壓合金屬層211與212於可塑性板材220上之後,移除壓印模板20,以暴露具有凹陷圖案P2的金屬層211。至此,包括可塑性板材220以及金屬層211與212的支撐板200基本上已完成。凹陷圖案P2會對應(aligned to)絕緣圖案131,並能容置絕緣圖案131。此外,在本實施例中,壓印圖案P1的一部分或是整個壓印圖案P1可以相同於絕緣圖案131。
須說明的是,圖2A至圖2C所揭露的支撐板200為包括可塑性板材220以及金屬層211與212的複合材料板,其具有多層結構。不過,在其他實施例中,支撐板200也可以是一塊陶瓷板、金屬板、塑膠板,或是沒有多層結構的複合材料板,其中此塑膠板例如是聚甲基丙烯酸甲酯板,也就是壓克力板,而金屬板可由單一金屬材料或合金材料所構成。因此,支撐板200並不限定只能是如圖2C所示的複合材料板。
圖3A至圖3D繪示本實施例封裝載板的線路層製造方法。請先參閱圖3A,其中圖3A的支撐板200為倒置後的圖2C的支撐板200。在支撐板200製造完成之後,固定絕緣圖案131於凹陷圖案P2內,以使導體層110、承載板120、絕緣圖案131以及支撐板200組合成一體。此時,金屬層211會配置在絕緣圖案131以及可塑性板材220之間,如圖3A所示。
在本實施例中,固定絕緣圖案131於凹陷圖案P2內的方法可以包括將絕緣圖案131壓合於凹陷圖案P2內。具體而言,可將支撐板200壓合於絕緣圖案131。由於凹陷圖案P2對應(aligned to)絕緣圖案131,並能容置絕緣圖案131,因此在支撐板200壓合於絕緣圖案131之後,絕緣圖案131會配置在凹陷圖案P2內。
絕緣圖案131與凹陷圖案P2之間可以設計適當的公差 (tolerance),以使絕緣圖案131在配置於凹陷圖案P2之後,絕緣圖案131與凹陷圖案P2側壁(sidewall)能彼此接觸,以產生足夠強度的摩擦力,從而使得絕緣圖案131與凹陷圖案P2不容易分離。如此,絕緣圖案131能固定在凹陷圖案P2內。此外,絕緣圖案131的厚度T3可以大於或等於凹陷圖案P2的深度D1。或者,絕緣圖案131的厚度T3也可以小於凹陷圖案P2的深度D1。
上述壓合可以是在真空環境下進行,以在凹陷圖案P2內產生負壓,從而讓外界的大氣壓力能壓迫支撐板200與導體層110。這樣可加強支撐板200與導體層110之間的結合,讓支撐板200不易從絕緣圖案131脫落。不過,須要一提的是,絕緣圖案131也可以是利用膠黏(adhering)的方法固定於凹陷圖案P2內。
舉例而言,在壓合期間,可對支撐板200與絕緣圖案131進行加熱,以使絕緣圖案131軟化並產生黏性。如此,絕緣圖案131能黏住支撐板200,從而將絕緣圖案131固定於凹陷圖案P2內。此外,也可使用絕緣圖案131以外的膠材來黏合支撐板200與絕緣圖案131,其中此膠材可以是能重複黏貼的感壓膠(pressure sensitive adhesives),其例如是橡膠系感壓膠、壓克力系感壓膠或矽氧樹脂(silicone)系感壓膠,其中此膠材也可由矽氧樹脂、橡膠、聚二甲基矽氧烷(Polydimethylsiloxane,PDMS)、聚甲基丙烯酸甲酯(Polymethylmethacrylate,PMMA,又稱壓克力)或樹脂所製成。
請參閱圖3A與圖3B,在絕緣圖案131固定在凹陷圖案P2內之後,移除承載板120,並保留導體層110,以暴露導體層110。移除承載板120的方法有多種,而在本實施例中,可以利用離型層121從導體層110剝離承載板120,其中承載板120可以採用徒手或機器來剝離。此外,在其他實施例中,當承載板120為一整塊金屬板時,移除承載板120的方法可以是蝕刻。所以,移除承載板120的方法不限制只能是剝離。
請參閱圖3B與圖3C,接著,圖案化導體層110,以形成線 路層111,其中形成線路層111的方法可以是微影(photolithography)與蝕刻(etching)。線路層111包括至少一個連接墊112與至少一個裝設墊113,其中裝設墊113用於供電子元件410(請參閱圖4B)裝設,而連接墊112用於電性連接電子元件410。此外,圖3C所示的裝設墊113的數量僅為一個,而連接墊112的數量為兩個,但在其他實施例中,裝設墊113的數量可以是多個,而連接墊112的數量可以是一個、三個或三個以上。所以,裝設墊113與連接墊112兩者的數量不受限於圖3C所示。
請參閱圖3D,在形成線路層111之後,可以改變線路層111表面的粗糙度(roughness)。詳細而言,根據產品需求,線路層111的表面111s可以經過表面處理(surface treatment),以使表面111s獲得能滿足產品需求的粗糙度,其中此表面處理例如是粗糙化(roughening)或拋光(polishing)。粗糙化可以是一般電路板製造技術中的黑化或棕化,而在線路層111經過此粗糙化之後,表面111s會形成一層粗糙氧化層,其例如是氧化銅層。如此,可以增加表面111s原本的粗糙度。
上述拋光可以是刷磨(brushing)或電拋光(electropolishing),而在導體層110經過拋光之後,可以降低表面110s原本的粗糙度。另外,線路層111的表面111s也可以預先形成粗糙氧化層,例如氧化銅層,而上述表面處理可以是去除部分粗糙氧化層,以降低表面111s原本的粗糙度,其中此表面處理可以是刷磨、照射雷射或電漿蝕刻。
在改變線路層111表面的粗糙度之後,可以在線路層111上形成保護層140。至此,一種包括支撐板200、線路層111、與線路層111堆疊及連接的絕緣圖案131、接合材料132以及保護層140的封裝載板311基本上已製造完成。保護層140可以相同於接合材料132。也就是說,保護層140也可以是焊料、金屬層或有機助焊層(OSP)。此外,須注意的是,本實施例的製造方法可以包 括改變線路層111表面的粗糙度以及形成保護層140這兩個步驟,但其他實施例的製造方法也可以不包括上述兩個步驟,所以封裝載板311也可以不包括保護層140。
請參閱圖3E,其為圖3D的俯視示意圖。在本實施例中,多塊封裝載板311會先直接形成在工作板材(working panel,簡稱panel)300中。具體而言,工作板材300包括多塊基板條301,而各個基板條301可具有一塊或多塊封裝載板311。在完成圖3D所示的製造流程之後,多塊封裝載板311可以一次形成在這些基板條301中。請參閱圖3D與圖3E,接著,切割支撐板200、絕緣圖案131與線路層111,以將工作板材300切割成多塊基板條301。
圖4A至圖4C繪示本發明一實施例的電子封裝件的製造方法的示意圖。請參閱圖4A與圖4B,其中圖4B是圖4A中沿線II-II剖面所繪示的剖面示意圖。在切割工作板材300,以形成多塊基板條301之後,將一個或多個電子元件410裝設於其中一塊基板條301上。電子元件410可以採用打線(wire-bonding)或覆晶(flip chip)而裝設於基板條301上,而電子元件410可以是裸晶或離散元件(discrete component)。電子元件410會裝設於裝設墊113上,而線路層111會位於電子元件410與絕緣圖案131之間。
接著,在線路層111上形成覆蓋線路層111與電子元件410的模封層430,其中模封層430更包覆電子元件410。至此,一種包括封裝載板311、電子元件410以及模封層430的電子封裝件400基本上已製作完成。
在圖4B的實施例中,電子元件410是採用打線而裝設於基板條301上,其中電子元件410可經由黏著層420而貼附在裝設墊113上,而黏著層420可為銀膠或高分子膠。當黏著層420為銀膠時,黏著層420會受到裝設墊113的粗糙度影響而擴散。然而,由於線路層111的表面111s可先經過表面處理而改變粗糙度,因此黏著層420的擴散程度可受到控制,以使電子元件410能穩 固地貼附在裝設墊113上。同理,模封層430與線路層111之間的接合力(bonding force)也與此粗糙度有關,所以線路層111也可利用上述表面處理來提高模封層430與線路層111之間的接合力,以避免模封層430脫落。
請參閱圖4B與圖4C,之後,將絕緣圖案131從凹陷圖案P2脫離,以分開支撐板200與絕緣圖案131。具體而言,支撐板200與絕緣圖案131之間的接合力小於或遠小於絕緣圖案131與線路層111之間的接合力,而絕緣圖案131壓合於凹陷圖案P2內,可對支撐板200施加外力,例如用手或機器將支撐板200從絕緣圖案131拉開。
分開支撐板200與絕緣圖案131之後,絕緣圖案131會裸露出來,特別由此可見線路層111不覆蓋絕緣圖案131的側壁,其中開口131a對應(aligned to)連接墊112,而與開口131b對應裝設墊113。此外,位於開口131a處的接合材料132可用來連接焊料,例如錫球,而位於開口131b處的接合材料132可用來連接散熱器(heat sink),以幫助電子元件410散熱。接著,利用刀具40,對基板條301(請參考圖4A)切塊(dicing),以形成不含支撐板200的電子封裝件401及其封裝載板312。
請參照圖5A至圖5F。圖5A至圖5F繪示本發明另一實施例的封裝載板的製造方法的示意圖。與前一實施例相似,在本實施例的封裝載板的製造方法中,提供前一實施例中所述的承載板120以及導體層110,並且在導體層110上形成絕緣圖案131與接合材料132,如圖1C所示。
和前一實施例不同的是,本實施例所提供的支撐板200’包括一接合層213。詳細而言,本實施例的支撐板200’包括一板材210、金屬層211與212以及接合層213的複合材料板。金屬層211與212分別壓合在板材210的兩相反面,而接合層213則形成於其中一金屬層211上。
板材210可以是具有熱固性的材料,也就是在金屬層211與212尚未壓合至板材210之前,板材210為未固化的膠片。因此,在金屬層211壓合於板材210的過程中,可藉由一加熱製程以固化板材210。如前一實施例所述,金屬層211與212可為金屬箔片,其例如是銅箔、銀箔、鋁箔或合金箔。在其他實施例中,也可只壓合金屬層211於板材210上,而不壓合金屬層212等其他金屬層。
在其他實施例中,也可以直接在板材210上形成接合層213。在這個實施例中,板材210也可以是一塊陶瓷板、金屬板、塑膠板,或是沒有多層結構的複合材料板,其中此塑膠板例如是聚甲基丙烯酸甲酯板,也就是壓克力板,而金屬板可由單一金屬材料或合金材料所構成。
接合層213為可剝離膠,其可以是紫外光固化膠、熱固化膠或金屬膠帶。在其他實施例中,接合層213可以是能重複黏貼的感壓膠(pressure sensitive adhesives),其例如是橡膠系感壓膠、壓克力系感壓膠或矽氧樹脂(silicone)系感壓膠,其中此膠材也可由矽氧樹脂、橡膠、聚二甲基矽氧烷(Polydimethylsiloxane,PDMS)、聚甲基丙烯酸甲酯(Polymethylmethacrylate,PMMA,又稱壓克力)或樹脂所製成。另外,接合層213可利用塗佈、網印或者直接貼附的方式形成於金屬層211或板材210上。
圖5B至圖5E繪示本實施例封裝載板的線路層製造方法。請先參閱圖5B,在圖5B中的支撐板200’為倒置後的圖5A的支撐板200’。在支撐板200’製造完成後,將絕緣圖案131固定於接合層213,以使導體層110、承載板120、絕緣圖案131以及支撐板200’組合成一體。
在一實施例中,接合層213形成於金屬層211或板材210上時呈膠狀。當絕緣圖案131被固定於接合層213時,絕緣圖案131會陷入接合層213中。另外,在將絕緣圖案131固定於接合層213 的過程中,可施以一固化製程,以固化接合層213,從而將絕緣圖案131固定於接合層213中。
要特別說明的是,在本實施例中,接合層213與絕緣圖案131之間的結合力偏弱,且小於接合層213與金屬層211或板材210之間的黏著力。因此,不須施加太大的外力即可使接合層213與絕緣圖案131分離。
請參閱圖5C,在絕緣圖案131固定於接合層213之後,將承載板120移除,並保留導體層110。移除承載板120的方式如前一實施例所述,本實施例中不再加以贅述。
請參閱圖5D至圖5E,接著,圖案化導體層110,以形成線路層111,並在形成線路層111之後形成保護層140。形成線路層111與保護層140的方法以及詳細結構在圖3B至圖3D以及相關段落中已詳細敘述,本實施例中不再贅述。
接著請參照圖5F。圖5F為圖5E的俯視示意圖。與前一實施例相似,在完成圖5E的製程後,多塊封裝載板511會直接形成在工作板材500中。具體而言,工作板材500包括多塊基板條501,而在各基板條501中包括多個封裝載板511。接著,切割支撐板200’、絕緣圖案131與線路層111,以將工作板材500切割成多塊基板條501。
圖6A至6C繪示本發明另一實施例的電子封裝件的製造方法的示意圖。請參閱圖6A與圖6B,其中圖6B是圖6A中沿線H-H剖面所繪示的剖面示意圖。在切割工作板材500,以形成多塊基板條501之後,將一個或多個電子元件410裝設於其中一塊基板條501上,並形成模封層430覆蓋電子元件410,以形成電子封裝件600。前述裝設電子元件410於基板條501上的步驟,以及封裝電子元件410的步驟中的細節如前一實施例所述,本實施例中不再贅述。
請參閱圖6B與圖6C,之後,將絕緣圖案131從接合層213 脫離,以分開支撐板200’與絕緣圖案131。具體而言,支撐板200’與絕緣圖案131之間的接合力小於或遠小於絕緣圖案131與線路層111之間的接合力,而絕緣圖案131與接合層213之間的結合力又小於接合層213與板材210或金屬層211之間的結合力。因此,對支撐板200施加外力後,例如用手或機器使支撐板200’與絕緣圖案131分離。接著,利用刀具40,對基板條501(請參考圖6A)切塊(dicing),以形成不含支撐板200’的電子封裝件601及其封裝載板512。
必須說明的是,在其他實施例中,各個基板條301或501可以是一個封裝載板311或511,所以工作板材300或500(請參考圖3E與圖5F)可以直接切割成多塊含支撐板200或200’的封裝載板311或511。因此,在完成電子元件410的裝設以及模封層430的形成之後,無須再對基板條301或501進行切塊,而支撐板200或200’可以保留下來,連同電子封裝件401或601一起出貨。
綜上所述,相較於習知具有核心層的電子封裝件,電子封裝件401或601因不含支撐板200或200’而具有較薄的厚度。因此,電子封裝件401或601能滿足目前智慧手機(smart phone)、平板電腦(tablet)、個人數位助理(Personal Digital Assistant,PDA)、筆記型電腦(laptop)以及掌上遊戲機(handheld game console)等行動裝置(mobile device)朝向薄形化的發展趨勢,並適合應用於上述行動裝置中。
此外,在直接形成多塊封裝載板311或511於工作板材300或500內之後,可以先對這些封裝載板311或511進行檢查,以判別出正常及異常的封裝載板311或511。如此,可以減少電子元件410裝設在異常封裝載板311或511的機率,從而提高電子封裝件400與401或600與601的良率。
以上所述僅為本發明的實施例,其並非用以限定本發明的專利保護範圍。任何熟習相像技藝者,在不脫離本發明的精神與範 圍內,所作的更動及潤飾的等效替換,仍為本發明的專利保護範圍內。
110‧‧‧導體層
120‧‧‧承載板
121‧‧‧離型層
122、211‧‧‧金屬層
131‧‧‧絕緣圖案
132‧‧‧接合材料
200‧‧‧支撐板
220‧‧‧可塑性板材
D1‧‧‧深度
P2‧‧‧凹陷圖案
T3‧‧‧厚度

Claims (27)

  1. 一種封裝載板的製造方法,包括:提供一承載板與一導體層,其中該導體層位在該承載板上;在該導體層上形成一絕緣圖案,其中該絕緣圖案暴露部分該導體層;提供一支撐板;固定該絕緣圖案於該支撐板;在該絕緣圖案固定在該支撐板之後,移除該承載板,並保留該導體層;以及在移除該承載板之後,圖案化該導體層,以形成一線路層。
  2. 如申請專利範圍第1項所述之封裝載板的製造方法,其中該絕緣圖案為一防焊層。
  3. 如申請專利範圍第1項所述之封裝載板的製造方法,更包括在該絕緣圖案所暴露的部分該導體層上形成一接合材料。
  4. 如申請專利範圍第3項所述之封裝載板的製造方法,其中該接合材料為焊料、金屬層或有機助焊層。
  5. 如申請專利範圍第1項所述之封裝載板的製造方法,其中該支撐板具有一接合層,且固定該絕緣圖案於該支撐板的步驟更包括固定該絕緣圖案於該接合層。
  6. 如申請專利範圍第1項所述之封裝載板的製造方法,其中該支撐板具有一對應該絕緣圖案的凹陷圖案,且固定該絕緣圖案於該支撐板的步驟更包括:固定該絕緣圖案於該凹陷圖案內。
  7. 如申請專利範圍第6項所述之封裝載板的製造方法,其中固定該絕緣圖案於該凹陷圖案內的方法包括將該絕緣圖案壓合於該凹陷圖案內。
  8. 如申請專利範圍第6項所述之封裝載板的製造方法,其中該絕緣圖案的厚度大於或等於該凹陷圖案的深度。
  9. 如申請專利範圍第6項所述之封裝載板的製造方法,其中 該絕緣圖案的厚度小於該凹陷圖案的深度。
  10. 如申請專利範圍第6項所述之封裝載板的製造方法,更包括形成該支撐板,其中形成該支撐板的方法包括:提供一壓印模板,其具有一壓印圖案;以及利用該壓印模板,將一金屬層壓合於一可塑性板材上,其中該壓印圖案在該金屬層上壓印出該凹陷圖案。
  11. 如申請專利範圍第10項所述之封裝載板的製造方法,其中在該金屬層壓合於該可塑性板材上的期間,加熱該可塑性板材,以固化該可塑性板材。
  12. 如申請專利範圍第1項所述之封裝載板的製造方法,其中該承載板包括一主體板與一離型層,該離型層配置在該導體層與該主體板之間。
  13. 如申請專利範圍第1項所述之封裝載板的製造方法,在形成該線路層之後,更包括在該線路層上形成一保護層。
  14. 如申請專利範圍第1項所述之封裝載板的製造方法,在形成該線路層之後,更包括改變該線路層的表面粗糙度。
  15. 如申請專利範圍第1項所述之封裝載板的製造方法,更包括:裝設一電子元件於該線路層上;在該線路層上形成一包覆該電子元件的模封層;以及在形成該模封層之後,將該絕緣圖案從該支撐板分開。
  16. 如申請專利範圍第15項所述之封裝載板的製造方法,更包括:在裝設該電子元件於該線路層上之前,切割該支撐板、該絕緣圖案與該線路層,以形成多塊基板條,其中該電子元件裝設於其中一塊基板條上。
  17. 如申請專利範圍第16項所述之封裝載板的製造方法,更包括: 在分開該支撐板與該絕緣圖案之後,對該基板條切塊。
  18. 一種封裝載板,包括:一線路層,包括至少一連接墊與一裝設墊,其中該裝設墊用於供一電子元件裝設,而該連接墊用於電性連接該電子元件;以及一絕緣圖案,與該線路層堆疊及連接,其中該線路層不覆蓋該絕緣圖案的側壁。
  19. 如申請專利範圍第18項所述之封裝載板,其中該絕緣圖案具有至少一對應該至少一連接墊的開口。
  20. 如申請專利範圍第18項所述之封裝載板,更包括一支撐板,該支撐板具有一接合層,而該絕緣圖案固定於該接合層。
  21. 如申請專利範圍第18項所述之封裝載板,更包括一支撐板,該支撐板具有一對應該絕緣圖案的凹陷圖案,而該絕緣圖案壓合於該凹陷圖案內。
  22. 如申請專利範圍第21項所述之封裝載板,其中該支撐板包括:一可塑性板材;以及一金屬層,連接該可塑性板材,並具有該凹陷圖案,其中該金屬層配置在該絕緣圖案與該可塑性板材之間。
  23. 一種電子封裝件,包括:一封裝載板,包括:一線路層,包括至少一連接墊與一裝設墊;一絕緣圖案,與該線路層堆疊及連接,其中該線路層不覆蓋該絕緣圖案的側壁;一電子元件,裝設於該裝設墊上,並且電性連接該至少一連接墊,其中該線路層位於該電子元件與該絕緣圖案之間;以及一模封層,覆蓋該線路層與該電子元件。
  24. 如申請專利範圍第23項所述之電子封裝件,其中該絕緣圖案更具有一對應該連接墊的開口。
  25. 如申請專利範圍第23項所述之電子封裝件,其中該封裝載板更包括一支撐板,該支撐板具有一接合層,而該絕緣圖案固定於該接合層。
  26. 如申請專利範圍第23項所述之電子封裝件,其中該封裝載板更包括一支撐板,該支撐板具有一對應該絕緣圖案的凹陷圖案,而該絕緣圖案壓合於該凹陷圖案內。
  27. 如申請專利範圍第26項所述之電子封裝件,其中該支撐板包括:一可塑性板材;以及一金屬層,連接該可塑性板材,並具有該凹陷圖案,其中該金屬層配置在該絕緣圖案與該可塑性板材之間。
TW103139744A 2013-12-09 2014-11-17 電子封裝件、封裝載板及此封裝載板的製造方法 TWI590726B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361913423P 2013-12-09 2013-12-09
US201461939306P 2014-02-13 2014-02-13

Publications (2)

Publication Number Publication Date
TW201524292A TW201524292A (zh) 2015-06-16
TWI590726B true TWI590726B (zh) 2017-07-01

Family

ID=53271935

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103139744A TWI590726B (zh) 2013-12-09 2014-11-17 電子封裝件、封裝載板及此封裝載板的製造方法

Country Status (3)

Country Link
US (2) US9603246B2 (zh)
CN (1) CN104701188A (zh)
TW (1) TWI590726B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015156891A2 (en) * 2014-01-23 2015-10-15 Arizona Board Of Regents, Acting For And On Behalf Of Arizona State University Method of providing a flexible semiconductor device and flexible semiconductor device thereof
DE102014017886A1 (de) * 2014-12-04 2016-06-09 Auto-Kabel Management Gmbh Verfahren zum Herstellen eines elektrischen Anschlussteils
EP3933914A4 (en) * 2020-04-16 2023-07-19 Huawei Digital Power Technologies Co., Ltd. PACKAGING STRUCTURE, ELECTRICAL VEHICLE AND ELECTRONIC DEVICE
WO2023073395A1 (en) * 2021-10-29 2023-05-04 At&S Austria Technologie & Systemtechnik Manufacturing a component carrier by a nano imprint lithography process

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5573632A (en) * 1989-02-23 1996-11-12 Fuji Xerox Co., Ltd. Multilayer printed-circuit substrate, wiring substrate and process of producing the same
US5172213A (en) * 1991-05-23 1992-12-15 At&T Bell Laboratories Molded circuit package having heat dissipating post
US5339217A (en) * 1993-04-20 1994-08-16 Lambda Electronics, Inc. Composite printed circuit board and manufacturing method thereof
DE4405710A1 (de) * 1994-02-23 1995-08-24 Bosch Gmbh Robert Vorrichtung mit einer Trägerplatte und Verfahren zum Aufbringen eines Passivierungsgels
US5534466A (en) * 1995-06-01 1996-07-09 International Business Machines Corporation Method of making area direct transfer multilayer thin film structure
US6218202B1 (en) * 1998-10-06 2001-04-17 Texas Instruments Incorporated Semiconductor device testing and burn-in methodology
US6294840B1 (en) * 1999-11-18 2001-09-25 Lsi Logic Corporation Dual-thickness solder mask in integrated circuit package
US6800169B2 (en) * 2001-01-08 2004-10-05 Fujitsu Limited Method for joining conductive structures and an electrical conductive article
JP3692067B2 (ja) * 2001-11-30 2005-09-07 株式会社東芝 銅のcmp用研磨スラリーおよびそれを用いた半導体装置の製造方法
TWI268581B (en) * 2002-01-25 2006-12-11 Advanced Semiconductor Eng Stack type flip-chip package including a substrate board, a first chip, a second chip, multiple conductive wire, an underfill, and a packaging material
JP5350745B2 (ja) * 2008-10-21 2013-11-27 新光電気工業株式会社 配線基板
JP5238598B2 (ja) * 2009-04-30 2013-07-17 昭和電工株式会社 回路基板の製造方法
US9863616B2 (en) * 2012-01-30 2018-01-09 Bridgelux Inc. Circuit board for LED applications

Also Published As

Publication number Publication date
US20150162275A1 (en) 2015-06-11
US9603246B2 (en) 2017-03-21
TW201524292A (zh) 2015-06-16
US20170170138A1 (en) 2017-06-15
US9865561B2 (en) 2018-01-09
CN104701188A (zh) 2015-06-10

Similar Documents

Publication Publication Date Title
TWI588912B (zh) 電子封裝件、封裝載板及兩者的製造方法
US9425122B2 (en) Electronic component package and method for manufacturing the same
US9368469B2 (en) Electronic component package and method of manufacturing same
US20090223046A1 (en) Method of manufacturing wiring board and method of manufacturing semiconductor package
JP2012191204A (ja) プリント配線板の製造方法
JP2010118373A (ja) 半導体装置の製造方法
KR20130063475A (ko) 배선 기판 제조 방법, 배선 기판 제조용 지지체 및 배선 기판용 구조체
US20150206819A1 (en) Electronic component package and method for manufacturing the same
US9865561B2 (en) Electronic package having a supporting board and package carrier thereof
US9236364B2 (en) Package carrier and manufacturing method thereof
JP2014130856A (ja) 配線基板の製造方法
JP5998792B2 (ja) 半導体ic内蔵基板及びその製造方法
TWI429043B (zh) 電路板結構、封裝結構與製作電路板的方法
JP2009272512A (ja) 半導体装置の製造方法
JP5302920B2 (ja) 多層配線基板の製造方法
TW201401439A (zh) 半導體封裝基板,使用其之封裝系統及其製造方法
KR20090065622A (ko) 코어리스 기판 가공을 위한 캐리어 제작 방법 및 이를이용한 코어리스 기판
KR101054565B1 (ko) 반도체 패키지 및 그의 제조방법
TWI433622B (zh) 具平滑表面的電路基板結構的製造方法
KR101044133B1 (ko) 인쇄회로기판 제조용 캐리어와 그 제조방법 및 이를 이용한 인쇄회로기판의 제조방법
JP6036434B2 (ja) コアレス配線基板の製造方法、配線基板製造用キャリア部材及びその製造方法
JP2005191234A (ja) 半導体装置およびその製造方法
JP5610039B2 (ja) 配線基板の製造方法
TWI507109B (zh) A supporting substrate for manufacturing a multilayer wiring board, and a method for manufacturing the multilayer wiring board
JP2003209355A (ja) 配線基板の製造方法および配線基板

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees