TWI429043B - 電路板結構、封裝結構與製作電路板的方法 - Google Patents

電路板結構、封裝結構與製作電路板的方法 Download PDF

Info

Publication number
TWI429043B
TWI429043B TW099113040A TW99113040A TWI429043B TW I429043 B TWI429043 B TW I429043B TW 099113040 A TW099113040 A TW 099113040A TW 99113040 A TW99113040 A TW 99113040A TW I429043 B TWI429043 B TW I429043B
Authority
TW
Taiwan
Prior art keywords
conductive pattern
pattern
release film
patterned
sealant
Prior art date
Application number
TW099113040A
Other languages
English (en)
Other versions
TW201138043A (en
Inventor
Lee Sheng Yen
Original Assignee
Advance Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advance Materials Corp filed Critical Advance Materials Corp
Priority to TW099113040A priority Critical patent/TWI429043B/zh
Priority to US12/835,746 priority patent/US8836108B2/en
Priority to KR1020100071315A priority patent/KR101085185B1/ko
Publication of TW201138043A publication Critical patent/TW201138043A/zh
Priority to US13/532,723 priority patent/US8748234B2/en
Priority to US13/531,608 priority patent/US8742567B2/en
Priority to US13/863,401 priority patent/US8987060B2/en
Application granted granted Critical
Publication of TWI429043B publication Critical patent/TWI429043B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48639—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48655—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48839—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48844—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48855—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Description

電路板結構、封裝結構與製作電路板的方法
本發明係關於一種製作電路板的方法、所製得之電路板結構與封裝結構。特定言之，本發明係關於一種透過貼合有離型膜之載板，以支持覆蓋有防焊層之銅箔，進而製得電路板結構與封裝結構的方法。
電路板是電子裝置中一種重要的元件。在電子裝置不斷追求尺寸縮小的趨勢下，遂發展出多種不同支撐晶粒的載具(carrier)結構，並以接腳(pin)向外延伸與位於電路板四周的其他電路形成適當的電連接。
就目前的技術而言，已知有一種稱為導線架(lead frame)的電路板結構。第1-4圖例示傳統上製作導線架的方法。請參考第1圖，首先提供一金屬基板101。其次，請參考第2圖，將提供金屬基板101圖案化，以形成預計對應晶粒(圖未示)之電路圖案110，與晶粒座111。繼續，形成介層洞122、將接腳120連接至金屬基板101上、並將接腳120與晶粒座111鍍銀121。再來，請參考第3圖，將晶粒130黏至晶粒座111上後，續以打線封裝與鍍錫步驟。然後，請參考第4圖，接下來要完成接腳成型，而得到一個晶粒的封裝結構102。晶粒的資料即透過接腳120向外界的電路連絡。
然而，當晶粒所處理的資料量增大及處理速度變快時，以上所例示之導線架，卻因為晶粒週邊空間有限，而無法對應地增加更多的接腳120以配合需求。如此一來，便使得傳統導線架封裝結構102的應用受到限制。
第5圖例示另外一種支撐晶粒的載具結構201。在載具結構201中，電路圖案220分別位於基板210之兩側。另外，防焊層230則選擇性地位於基板210之兩側，適當地保護電路圖案220。除此以外，又暴露出部份的電路圖案220。在此載具結構201中，需要在基板210之兩側形成獨立的防焊層圖案231/232。防焊層圖案231/232通常各不相同，才能以應付晶粒座(圖未示)位置與焊球(圖未示)位置之不同需求。
當第5圖所例示之支撐晶粒的載具結構201在進行過封裝步驟之後，就可以得到第6圖所例示之封裝結構202。在第6圖所例示之封裝結構202中，除了第5圖所例示之基板210、電路圖案220、防焊層230與防焊層圖案231/232，還因為後來之封裝步驟增加了晶粒座221、晶粒240、接合導線250、封膠260與焊球270。
晶粒240位於電路圖案220中之晶粒座221上，還同時被防焊層圖案231所圍繞，並以接合導線250與電路圖案220之其他部份電連接。封膠260即完全包覆晶粒座221、晶粒240、接合導線250，與覆蓋部份之基板210與防焊層230。焊球270則被防焊層圖案232所圍繞。在第5圖所例示之載具結構201與第6圖所例示之封裝結構202中都可以觀察到，位在基板210兩側獨立的防焊層圖案231/232，並且延伸至基板210的側邊。
有鑑於以上之載具結構、封裝結構與傳統上製作導線架的方法尚未臻完善，仍然希望有其他新穎的電路板結構、封裝結構及其製作方法，能夠在結構上更加簡化，並且還能一舉突破傳統上的限制。
本發明於是提出一種新穎的電路板結構、封裝結構及其製作方法。本發明所提出的電路板結構與封裝結構，由於只需單面的圖案化防焊層，在整體結構上因為更加簡化，所以可以同時使得其製作方法亦能因此一併簡化。除此之外，本發明的電路板結構與封裝結構，還能一舉突破傳統結構上接腳數目不足的限制，足以配合當晶粒所處理的資料量增大及處理速度變快時，對於接腳數目增加的硬體需求。
本發明一方面提出一種製作電路板的方法。首先，分別提供第一基板與第二基板。第一基板包含貼合有離型膜之載板，而第二基板則包含覆蓋有第一防焊層之銅箔。其次，單面圖案化第一防焊層。再來，將離型膜與圖案化第一防焊層壓合，使得第一基板貼合至第二基板。然後，圖案化銅箔，使得銅箔形成第一圖案與第二圖案，其中第一圖案直接接觸離型膜，而第二圖案直接接觸圖案化第一防焊層。繼續，形成第一保護層，分別覆蓋第一圖案與第二圖案，得到一電路板結構。
在本發明一實施態樣中，第一圖案為晶粒座，而第二圖案則為受到圖案化防焊層保護之電路圖案。在本發明另一實施態樣中，還可以形成第二防焊層，以選擇性覆蓋第二圖案。在本發明又一實施態樣中，還可以形成位於載板上之封裝體。在本發明又一實施態樣中，則可以繼續移除離型膜與載板，而暴露出第一圖案與圖案化防焊層，於是又得到一封裝結構。
本發明其次提出一種電路板結構。本發明之電路板結構，包含載板、離型膜、圖案化防焊層、第一導電圖案、第二導電圖案與保護層。離型膜貼合至載板上。單面圖案化之防焊層則位於離型膜上並直接接觸離型膜。第一導電圖案位於離型膜上，並直接接觸離型膜。第二導電圖案位於離型膜上、鄰近第一導電圖案並直接接觸圖案化防焊層。保護層則分別覆蓋第一導電圖案與第二導電圖案。
本發明還提出另一種電路板結構。本發明之電路板結構，包含載板、離型膜、圖案化防焊層、第一導電圖案、第二導電圖案、覆蓋防焊層與保護層。離型膜貼合至載板上。單面圖案化之防焊層則位於離型膜上並直接接觸離型膜。第一導電圖案位於離型膜上，並直接接觸離型膜。第二導電圖案位於離型膜上、鄰近第一導電圖案並直接接觸圖案化防焊層。覆蓋防焊層係選擇性覆蓋第二導電圖案。保護層則分別覆蓋第一導電圖案與第二導電圖案。
本發明又繼續提出一種封裝結構。本發明之封裝結構，包含封膠、單面圖案化防焊層、第一導電圖案、第二導電圖案、第一保護層、第二保護層、晶粒與接合導線。圖案化防焊層位於封膠之一表面上。第一導電圖案位於封膠之相同表面上。第二導電圖案位於封膠中、鄰近第一導電圖案並直接接觸圖案化防焊層。第一保護層完全位於封膠中，且分別覆蓋第一導電圖案與第二導電圖案。第二保護層則完全覆蓋第一導電圖案。晶粒完全位於封膠中與第一圖案上。接合導線亦完全位於封膠中，並選擇性地電連接晶粒與第一導電圖案。
本發明再繼續提出一種封裝結構。本發明之封裝結構，包含封膠、單面圖案化防焊層、第一導電圖案、第二導電圖案、覆蓋防焊層、第一保護層、第二保護層、晶粒與接合導線。圖案化防焊層位於封膠之一表面上。第一導電圖案位於封膠之相同表面上。第二導電圖案位於封膠中、鄰近第一導電圖案並直接接觸圖案化防焊層。覆蓋防焊層則直接覆蓋第二導電圖案。第一保護層完全位於封膠中，且覆蓋第一導電圖案。第二保護層則完全位於封膠外，並覆蓋第一導電圖案。晶粒完全位於封膠中與第一圖案上。接合導線亦完全位於封膠中，並選擇性地電連接晶粒與第一導電圖案。
本發明第一方面提出一種製作電路板的方法第一實施方式。第7-11圖例示本發明製作電路板的方法。請參考第7圖，首先分別提供第一基板310與第二基板320。第一基板310與第二基板320可以先分開製作，而當需要時才進行壓合成單一之基板(圖未示)。第一基板310中包含有載板311，載板311上之一面貼合有離型膜312。第二基板320則包含有銅箔321，其可以具有10-70μm之厚度，較佳為10-35μm之厚度。銅箔321僅有一面覆蓋有防焊層322。
載板311可以為任何材料，例如聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚甲基丙烯酸甲酯(PMMA)與無銅基板等等。離型膜312可以為一種具有可塑性之黏性材料，並與載板311間產生較強之黏著力。因此離型膜312即藉此黏著力貼合在載板311之一面上。當少量生產時，可以使用例如網印法，來將離型膜312塗佈在載板311上。另一方面，當大量生產時，則可以使用例如滾輪法，來將離型膜312塗佈在載板311上。
其次，請參考第8圖，在壓合第一基板310與第二基板320之前，先圖案化防焊層322。可以使用習知之光學微影法或是雷射開口法...等等，來圖案化防焊層322。防焊層322上之圖案可以預先經過設計，好配合後續製程之需要。例如，只在防焊層322的單面上進行圖案化製程，而得到單面圖案化的防焊層322。
然後，請參考第9圖，此時離型膜312與經過圖案化之防焊層322就可以進行壓合，使得第一基板310貼合至第二基板320。因為離型膜312可以為一種具有可塑性之黏性材料，在本發明一實施態樣中，在第一基板310貼合至第二基板320時，會使得圖案化之防焊層322嵌入離型膜312中。因此，銅箔321即會直接接觸離型膜312。另外，由於離型膜312與載板311間之黏著力較強，所以離型膜312與經過圖案化之防焊層322間之黏著力則相對較弱。此時，銅箔321的一面會暴露在外。
接下來，請參考第10圖，在第一實施方式中，由於銅箔321的一面仍然暴露在外，所以當圖案化銅箔321之後，就會使得銅箔321形成有圖案，例如第一圖案325、晶粒座328(die pad)與第二圖案326。可以使用例如乾膜法或是濕膜法，來圖案化銅箔321。第一圖案325與第二圖案326之功能各自不同。在本發明一實施態樣中，第一圖案325中可以為電連接墊(connecting pad)，而第二圖案326則可以為受到圖案化防焊層322所保護之電路圖案326。換句話說，第二圖案326會對應圖案化防焊層322。於是，如第10圖所示，第一圖案325會直接接觸離型膜312，而第二圖案326則直接接觸圖案化防焊層322。
在本發明另一種製作電路板的方法第二實施方式中，請參考第10A圖，還可以形成覆蓋防焊層327，來完全覆蓋第一圖案325、晶粒座328與第二圖案326。覆蓋防焊層327可以作為第二圖案326的保護層之用。接下來，請參考第10B圖，圖案化覆蓋防焊層327，來暴露出所需的元件。例如，圖案化覆蓋防焊層327，來暴露出第一圖案325與晶粒座328，並覆蓋第二圖案326。覆蓋防焊層327可以作為第二圖案326的保護層之用。
繼續，請參考第11圖，為了保護脆弱的銅箔321，需要在銅箔321的表面形成第一保護層323。由於圖案化銅箔321上會有功能各自不同之第一圖案325與第二圖案326，所以第一保護層323也會分別覆蓋第一圖案325與第二圖案326。可以使用電鍍的方法，在銅箔321的表面形成第一保護層323。第一保護層323可以是一種複合材料層，例如第一保護層323會包含鎳、銀與金之至少一者，形成像是鎳/金之保護層。
或是，請參考第11A圖，為了保護脆弱的銅箔321，需要在銅箔321的表面形成第一保護層323。所以第一保護層323會覆蓋第一圖案325和晶粒座328。可以使用電鍍的方法，在銅箔321的表面形成第一保護層323。第一保護層323可以是一種複合材料層，例如第一保護層323會包含鎳、銀與金之至少一者，形成像是鎳/金之保護層。
經過以上步驟之後，壓合在一起之第一基板310與第二基板320就形成一個新穎的電路板結構301。請參考第11圖，例示本發明所提出之電路板結構301的第一實施方式。第11A圖例示本發明所提出之電路板結構301的第二實施方式。在本發明之電路板結構301中，包含載板311、離型膜312、圖案化防焊層322、第一導電圖案325、第二導電圖案326與第一保護層323。若是電路板結構301另外還包含覆蓋防焊層327，則如第11A圖所示，例示本發明所提出之電路板結構301的第二實施方式。
承前所述，離型膜312貼合至載板311上，而其間之黏著力較強。圖案化防焊層322則位於離型膜312上，並直接接觸離型膜312。在本發明一實施態樣中，在第二基板320中之圖案化之防焊層322貼合至第一基板310中之離型膜312時，較佳還會嵌入離型膜312中。第一導電圖案325與第二導電圖案326分別位於離型膜312上。第一導電圖案325會直接接觸離型膜312。另一方面，第二導電圖案326則直接接觸圖案化防焊層322。換句話說，第二圖案326會對應圖案化防焊層322。還有，第一導電圖案325與第二導電圖案326常常彼此鄰近，或是交錯。第一保護層323則分別覆蓋第一導電圖案325與第二導電圖案326。第一保護層323可以包含鎳、銀與金之至少一者，而形成像是鎳/金之複合保護層。
在本發明另一實施態樣中，第11圖所例示之電路板結構301還可以進一步經過一預封裝步驟，而得到一預封裝結構303。第12圖例示本發明製作預封裝結構的延續方法的第一實施方式。第12A圖例示本發明製作預封裝結構的延續方法的第二實施方式，電路板結構301另外還包含覆蓋防焊層327。請參考第12圖與第12A圖，第11圖與第11A圖所例示之電路板結構301還可以進一步在載板311上形成一封裝體330。例如，先將晶粒331黏在第一圖案325上，亦即晶粒座328上。例如，可以使用銀膠或可散熱之物質(圖未示)將晶粒331黏在第一圖案325上。然後，使用接合導線332，例如銅線、銀線、金線或鍍金銅線，視情況需要選擇性將晶粒331與部份之第一圖案325進行電連接。在電連接完成後，即可以使用封膠333，例如環氧樹脂，將晶粒331與接合導線332密封，以杜絕外界，例如水氣之污染。
如第12圖所例示，封膠333除了會將晶粒331與接合導線332完全密封以外，封膠333通常還會直接接觸圖案化防焊層322與離型膜312。第12A圖中，封膠333則會完全密封覆蓋防焊層327。第11圖所例示之電路板結構301在進一步載板311上形成一封裝體330後，即可得到第12圖所例示之預封裝結構303。
在本發明又一實施態樣中，第12圖所例示之預封裝結構303又可以進一步經過另一步驟，而得到另一預封裝結構305。第13圖例示本發明製作另一預封裝結構的延續方法的第一實施方式。第13A圖例示本發明製作另一預封裝結構的延續方法的第二實施方式，電路板結構301另外還包含覆蓋防焊層327。請參考第13圖與第13A圖，將第12圖與第12A圖所例示之預封裝結構303中之載板311與離型膜312分別移除之後，即可得到另一預封裝結構305。
請注意，由於離型膜312與載板311間之黏著力較強，離型膜312與經過圖案化之防焊層322間之黏著力相對較弱，所以可以很輕易的移除預封裝結構303中之載板311與離型膜312，而不影響預封裝結構303中之其他部份。此時，圖案化防焊層322會選擇性地位於第一圖案325之間。封裝結構305在移除預封裝結構303中之載板311與離型膜312之後，經過圖案化之防焊層322與第一圖案325便會暴露出來。
為了保護第一圖案325的脆弱銅箔，在本發明再一實施態樣中，第13圖所例示之另一預封裝結構305可以再進一步經過保護步驟，而得到封裝結構307。第14圖例示本發明製作封裝結構的延續方法。請參考第14圖，第13圖所例示之預封裝結構305，還可以進一步在第一圖案325上形成第二保護層324，來完全覆蓋住第一圖案325。第二保護層324可以包含鎳、銀與金之至少一者(或使用OSP(有機保焊膜))，而形成像是鎳/金之複合保護層。
經過以上步驟之後，就可以得到一個新穎的封裝結構307。請參考第14圖，例示本發明所提供之封裝結構307的第一實施方式。第14A圖例示本發明所提供之封裝結構307的的第二實施方式，電路板結構301另外還包含覆蓋防焊層327。在本發明之封裝結構307中，包含圖案化防焊層322、第一導電圖案325、第二導電圖案326、第一保護層323、第二保護層324、晶粒331、接合導線332與封膠333。
在本發明所提出之封裝結構307中，如第14圖所示，首先可以觀察到圖案化防焊層322位於封膠333之一表面上。圖案化防焊層322部分接觸封膠333並部分曝露出來。封膠333通常為一密封材料，例如環氧樹脂。第一導電圖案325位於與圖案化防焊層322所在之封膠333之相同表面上。第一導電圖案312通常定義出供晶粒331所使用之晶粒座。第二導電圖案326亦位於封膠333中，並定義出一電路圖案。還有，第二導電圖案326會直接接觸圖案化防焊層322，而受到該圖案化防焊層322之保護。換句話說，第二圖案326會對應圖案化防焊層322。除此以外，第二導電圖案326也鄰近第一導電圖案312，同時又直接接觸圖案化防焊層322。在第14A圖中，覆蓋防焊層327直接覆蓋第二導電圖案326。
一方面，第一保護層323完全位於封膠333中，而分別覆蓋第一導電圖案325與第二導電圖案326。另一方面，第二保護層324則完全位於封膠333外，並完全覆蓋第一導電圖案312。第一保護層323與第二保護層324可以分別獨立地包含鎳、銀與金之至少一者，而形成像是鎳/金之複合保護層(或OSP(有機保焊膜))。晶粒331位於第一導電圖案325上，又經由接合導線332選擇性地與部份之第一導電圖案325電連接。晶粒333與接合導線332同時完全位於封膠中333，而形成一封裝體。本發明封裝結構307之其他特徵，可以參考前述而不再重複。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
101．．．金屬基板
102．．．封裝結構
110．．．電路圖案
111．．．晶粒座
120．．．接腳
121．．．鍍銀
130．．．晶粒
201．．．載具結構
210．．．基板
220．．．電路圖案
221．．．晶粒座
230．．．防焊層
231．．．防焊層圖案
232．．．防焊層圖案
240．．．晶粒
250．．．接合導線
260．．．封膠
270．．．焊球
301．．．電路板結構
303．．．預封裝結構
305．．．預封裝結構
307．．．封裝結構
310．．．第一基板
311．．．載板
312．．．離型膜
320．．．第二基板
321．．．銅箔
322．．．防焊層
322．．．圖案化防焊層
323．．．第一保護層
324．．．第二保護層
325．．．第一圖案
325．．．第一導電圖案
326．．．第二圖案
326．．．第二導電圖案
326．．．電路圖案
327．．．覆蓋防焊層
328．．．晶粒座
330．．．封裝體
331．．．晶粒
332．．．接合導線
333．．．封膠
第1-4圖例示傳統上製作導線架的方法。
第5圖例示傳統上支撐晶粒的載具結構。
第6圖例示傳統上之封裝結構。
第7-10B圖例示本發明製作電路板的方法。
第11圖與第11A圖例示本發明所提出之電路板結構。
第12圖與第12A圖例示本發明製作預封裝結構的延續方法。
第13圖與第13A圖例示本發明製作另一預封裝結構的延續方法。
第14圖與第14A圖例示本發明所提出之封裝結構。
301．．．電路板結構
310．．．第一基板
311．．．載板
312．．．離型膜
320．．．第二基板
321．．．銅箔
322．．．圖案化防焊層
323．．．第一保護層
328．．．晶粒座
326．．．第二圖案

Claims (15)

  1. 一種製作電路板的方法，包含：分別提供一第一基板與一第二基板，其中該第一基板包含貼合有一離型膜之一載板，而該第二基板包含覆蓋有一第一防焊層之一銅箔；圖案化該第一防焊層；將該離型膜與該圖案化第一防焊層壓合，使得該第一基板貼合至該第二基板；圖案化該銅箔，使得該銅箔形成一第一圖案、一晶粒座與一第二圖案，其中該第一圖案直接接觸該離型膜，而該第二圖案直接接觸該圖案化第一防焊層；以及形成一第一保護層，分別覆蓋該第一圖案與該第二圖案，以形成一電路板。
  2. 如請求項1製作電路板的方法，其中該第二圖案為一電路圖案，而受到該圖案化第一防焊層之保護。
  3. 如請求項1製作電路板的方法，其中該第二圖案對應該圖案化第一防焊層。
  4. 如請求項2製作電路板的方法，更包含：形成一第二防焊層，以選擇性覆蓋該第二圖案。
  5. 如請求項1製作電路板的方法，更包含：形成位於該載板上之一封裝體。
  6. 如請求項5製作電路板的方法，其中該封裝體包含：一晶粒，位於該晶粒座上；一接合導線，選擇性電連接該晶粒與該第一圖案；以及一封膠，密封該晶粒與該接合導線並直接接觸該圖案化第一防焊層與該離型膜。
  7. 如請求項5製作電路板的方法，更包含：同時移除該離型膜與該載板，以暴露出該第一圖案與該圖案化第一防焊層。
  8. 一種電路板結構，包含：一載板；一離型膜，貼合至該載板；一圖案化防焊層，位於該離型膜上並直接接觸該離型膜；一第一導電圖案，位於該離型膜上並直接接觸該離型膜；一第二導電圖案，位於該離型膜上、鄰近該第一導電圖案並直接接觸該圖案化防焊層；以及一保護層，分別覆蓋該第一導電圖案與該第二導電圖案。
  9. 一種電路板結構，包含：一載板；一離型膜，貼合至該載板；一圖案化防焊層，位於該離型膜上並直接接觸該離型膜；一第一導電圖案，位於該離型膜上並直接接觸該離型膜；一第二導電圖案，位於該離型膜上、鄰近該第一導電圖案並直接接觸該圖案化防焊層；一覆蓋防焊層，以選擇性覆蓋該第二導電圖案；以及一保護層，分別覆蓋該第一導電圖案與該第二導電圖案。
  10. 一種封裝結構，包含：一封膠；一圖案化防焊層，位於該封膠之一表面上；一第一導電圖案，位於該封膠之該表面上；一晶粒座，位於該封膠中；一第二導電圖案，位於該封膠中、鄰近該第一導電圖案並直接接觸該圖案化防焊層；一第一保護層，完全位於該封膠中且分別覆蓋該第一導電圖案與該第二導電圖案；一第二保護層，完全覆蓋該第一導電圖案；一晶粒，完全位於該封膠中與該晶粒座上；以及一接合導線，完全位於該封膠中並選擇性電連接該晶粒與該第一導電圖案。
  11. 如請求項10之封裝結構，其中該圖案化防焊層部分接觸該封膠並部分曝露出來。
  12. 如請求項10之封裝結構，其中該第二導電圖案為一電路圖案，而受到該圖案化防焊層之保護。
  13. 一種封裝結構，包含：一封膠；一圖案化防焊層，位於該封膠之一表面上；一第一導電圖案，位於該封膠之該表面上；一晶粒座，位於該封膠中；一第二導電圖案，位於該封膠中、鄰近該第一導電圖案並直接接觸該圖案化防焊層；一覆蓋防焊層，直接覆蓋該第二導電圖案；一第一保護層，完全位於該封膠中且覆蓋該第一導電圖案；一第二保護層，完全位於該封膠外且覆蓋該第一導電圖案；一晶粒，完全位於該封膠中與該晶粒座上；以及一接合導線，完全位於該封膠中並選擇性電連接該晶粒與該第一導電圖案。
  14. 如請求項13之封裝結構，其中該圖案化防焊層部分接觸該封膠並部分曝露出來。
  15. 如請求項13之封裝結構，其中該第二導電圖案為一電路圖案，而受到該圖案化防焊層之保護。
TW099113040A 2010-04-26 2010-04-26 電路板結構、封裝結構與製作電路板的方法 TWI429043B (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
TW099113040A TWI429043B (zh) 2010-04-26 2010-04-26 電路板結構、封裝結構與製作電路板的方法
US12/835,746 US8836108B2 (en) 2010-04-26 2010-07-14 Circuit board structure and package structure
KR1020100071315A KR101085185B1 (ko) 2010-04-26 2010-07-23 회로 기판 구조, 패키징 구조 및 이들의 제조 방법
US13/532,723 US8748234B2 (en) 2010-04-26 2012-06-25 Method for making circuit board
US13/531,608 US8742567B2 (en) 2010-04-26 2012-06-25 Circuit board structure and packaging structure comprising the circuit board structure
US13/863,401 US8987060B2 (en) 2010-04-26 2013-04-16 Method for making circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW099113040A TWI429043B (zh) 2010-04-26 2010-04-26 電路板結構、封裝結構與製作電路板的方法

Publications (2)

Publication Number Publication Date
TW201138043A TW201138043A (en) 2011-11-01
TWI429043B true TWI429043B (zh) 2014-03-01

Family

ID=44815101

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099113040A TWI429043B (zh) 2010-04-26 2010-04-26 電路板結構、封裝結構與製作電路板的方法

Country Status (3)

Country Link
US (4) US8836108B2 (zh)
KR (1) KR101085185B1 (zh)
TW (1) TWI429043B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9668351B2 (en) 2015-01-13 2017-05-30 Subtron Technology Co., Ltd. Package carrier and manufacturing method thereof

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI429043B (zh) * 2010-04-26 2014-03-01 Advance Materials Corp 電路板結構、封裝結構與製作電路板的方法
KR101144610B1 (ko) * 2011-08-02 2012-05-11 한국기계연구원 투명 전극의 전도성 메쉬 매설 방법
US9177897B1 (en) 2013-06-28 2015-11-03 Stats Chippac Ltd. Integrated circuit packaging system with trace protection layer and method of manufacture thereof
US9190349B1 (en) 2013-06-28 2015-11-17 Stats Chippac Ltd. Integrated circuit packaging system with leadframe and method of manufacture thereof
US9620480B1 (en) * 2013-06-28 2017-04-11 STATS ChipPAC Pte. Ltd Integrated circuit packaging system with unplated leadframe and method of manufacture thereof
US9595455B1 (en) * 2016-06-09 2017-03-14 Nxp B.V. Integrated circuit module with filled contact gaps

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5480503A (en) 1993-12-30 1996-01-02 International Business Machines Corporation Process for producing circuitized layers and multilayer ceramic sub-laminates and composites thereof
US6962829B2 (en) * 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
US7247526B1 (en) 1998-06-10 2007-07-24 Asat Ltd. Process for fabricating an integrated circuit package
KR100293177B1 (ko) 1998-12-21 2001-08-07 이형도 연성볼그리드어레이기판및그제조방법
TW552694B (en) 2001-08-31 2003-09-11 Hitachi Chemical Co Ltd Wiring substrate, semiconductor device and the manufacturing method thereof
US6569712B2 (en) 2001-10-19 2003-05-27 Via Technologies, Inc. Structure of a ball-grid array package substrate and processes for producing thereof
US6769174B2 (en) 2002-07-26 2004-08-03 Stmicroeletronics, Inc. Leadframeless package structure and method
JP2004094502A (ja) 2002-08-30 2004-03-25 Dainippon Printing Co Ltd アンテナ配線パターンの形成方法
US6853060B1 (en) 2003-04-22 2005-02-08 Amkor Technology, Inc. Semiconductor package using a printed circuit board and a method of manufacturing the same
JP4842812B2 (ja) 2004-07-15 2011-12-21 大日本印刷株式会社 半導体装置用基板の製造方法
DE102004058879B4 (de) * 2004-12-06 2013-11-07 Austriamicrosystems Ag MEMS-Mikrophon und Verfahren zur Herstellung
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
US7504716B2 (en) * 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
TWI288468B (en) 2005-11-10 2007-10-11 Airoha Technology Inc Packaging method
KR100850213B1 (ko) 2007-05-22 2008-08-04 삼성전자주식회사 몰딩된 볼을 구비한 반도체 패키지 및 그 제조방법
KR101469770B1 (ko) 2007-11-21 2014-12-09 페어차일드코리아반도체 주식회사 전력 소자 패키지 및 그 제조 방법
KR100930965B1 (ko) 2008-01-17 2009-12-10 (주)아큐텍반도체기술 반도체 패키지용 기판의 제조방법 및 이를 이용하여 제조된금속 도금층
US20090230524A1 (en) 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
TWI429043B (zh) * 2010-04-26 2014-03-01 Advance Materials Corp 電路板結構、封裝結構與製作電路板的方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9668351B2 (en) 2015-01-13 2017-05-30 Subtron Technology Co., Ltd. Package carrier and manufacturing method thereof
TWI586236B (zh) * 2015-01-13 2017-06-01 旭德科技股份有限公司 封裝載板及其製作方法

Also Published As

Publication number Publication date
US20120261176A1 (en) 2012-10-18
US8836108B2 (en) 2014-09-16
KR101085185B1 (ko) 2011-11-18
US8987060B2 (en) 2015-03-24
TW201138043A (en) 2011-11-01
US20110260308A1 (en) 2011-10-27
US20130298397A1 (en) 2013-11-14
US20120260502A1 (en) 2012-10-18
US8742567B2 (en) 2014-06-03
KR20110119495A (ko) 2011-11-02
US8748234B2 (en) 2014-06-10

Similar Documents

Publication Publication Date Title
JP4171499B2 (ja) 電子装置用基板およびその製造方法、並びに電子装置およびその製造方法
TWI429043B (zh) 電路板結構、封裝結構與製作電路板的方法
JPH0936549A (ja) ベアチップ実装用プリント基板
US10002825B2 (en) Method of fabricating package structure with an embedded electronic component
TWI588912B (zh) 電子封裝件、封裝載板及兩者的製造方法
TWI474449B (zh) 封裝載板及其製作方法
JP4070470B2 (ja) 半導体装置用多層回路基板及びその製造方法並びに半導体装置
TW201515181A (zh) 無芯層封裝結構及其製造方法
TW201705426A (zh) 樹脂密封型半導體裝置及其製造方法
JP4763639B2 (ja) 電子素子パッケージの製造方法
TWI493682B (zh) 內嵌封裝體之封裝模組及其製造方法
CN102270584A (zh) 电路板结构、封装结构与制作电路板的方法
JP3624512B2 (ja) 電子部品搭載用基板の製造方法
KR101148954B1 (ko) 회로 보드 구조, 패키징 구조 및 이들을 만드는 방법
TW201446086A (zh) 封裝結構及其製作方法
CN215266271U (zh) 基于铜箔载板的正反面芯片集成封装结构
JP2011159944A (ja) 単層ボードオンチップパッケージ基板及びその製造方法
KR101130608B1 (ko) 반도체 패키지 및 그 제조방법
US20090309208A1 (en) Semiconductor device and method of manufacturing the same
TWI418006B (zh) 單層線路之封裝基板及其製法暨封裝結構
JP5429890B2 (ja) 配線用電子部品及びその製造方法、並びに該配線用電子部品を組み込んで用いる電子デバイスパッケージ及びその製造方法
KR20070079656A (ko) 자외선 경화형 코팅층을 갖는 인쇄회로기판 및 그의 제조방법
JP2006294825A (ja) 半導体集積回路装置
JP2002343818A (ja) Ｂｇａ型配線基板及びその製造方法並びに半導体装置の製造方法
JP2004119930A (ja) 半導体装置の製造方法