TWI474449B - 封裝載板及其製作方法 - Google Patents

封裝載板及其製作方法 Download PDF

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Publication number
TWI474449B
TWI474449B TW102135030A TW102135030A TWI474449B TW I474449 B TWI474449 B TW I474449B TW 102135030 A TW102135030 A TW 102135030A TW 102135030 A TW102135030 A TW 102135030A TW I474449 B TWI474449 B TW I474449B
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Taiwan
Prior art keywords
layer
metal
layers
package carrier
patterned
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TW102135030A
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English (en)
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TW201513281A (zh
Inventor
Shih Hao Sun
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Subtron Technology Co Ltd
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Publication date
Application filed by Subtron Technology Co Ltd filed Critical Subtron Technology Co Ltd
Priority to TW102135030A priority Critical patent/TWI474449B/zh
Priority to US14/086,987 priority patent/US9236364B2/en
Priority to JP2014118746A priority patent/JP5945563B2/ja
Application granted granted Critical
Publication of TWI474449B publication Critical patent/TWI474449B/zh
Publication of TW201513281A publication Critical patent/TW201513281A/zh

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    • H—ELECTRICITY
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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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Description

封裝載板及其製作方法
本發明是有關於一種封裝結構及其製作方法，且特別是有關於一種封裝載板及其製作方法。
晶片封裝的目的在於保護裸露的晶片、降低晶片接點的密度及提供晶片良好的散熱。常見的封裝方法是晶片透過打線接合(wire bonding)或覆晶接合(flip chip bonding)等方式而安裝至一封裝載板，以使晶片上的接點可電性連接至封裝載板。因此，晶片的接點分佈可藉由封裝載板重新配置，以符合下一層級的外部元件的接點分佈。
一般來說，封裝載板的製作通常是以核心(core)介電層作為蕊材，並利用全加成法(fully additive process)、半加成法(semi-additive process)、減成法(subtractive process)或其他方式，將圖案化線路層與圖案化介電層交錯堆疊於核心介電層上。如此一來，核心介電層在封裝載板的整體厚度上便會佔著相當大的比例。因此，若無法有效地縮減核心介電層的厚度，勢必會使 封裝結構於厚度縮減上產生極大的障礙。
本發明提供一種封裝載板，適於承載一晶片，且使用此封裝載板之封裝結構的封裝厚度較小。
本發明提供一種封裝載板的製作方法，用以製作上述之封裝載板。
本發明的封裝載板的製作方法包括下列步驟。首先，接合兩基底金屬層。接著，分別壓合兩支撐層於兩基底金屬層上。接著，分別設置兩離型金屬膜於兩支撐層上，其中各離型金屬膜包括可彼此分離之第一金屬箔層及第二金屬箔層。接著，分別形成兩圖案化金屬層於兩離型金屬膜上，其中各圖案化金屬層適於承載以及電性連接一晶片。之後，令兩基底金屬層分離，以形成各自獨立的兩封裝載板。
本發明的封裝載板適於承載一晶片。封裝載板包括一支撐層、一基底金屬層、一離型金屬膜以及一圖案化金屬層。支撐層包括一第一表面以及相對第一表面的一第二表面。基底金屬層設置於支撐層的第一表面上。離型金屬膜設置於支撐層的第二表面上。離型金屬膜包括可彼此分離之一第一金屬箔層以及一第二金屬箔層，且第二金屬箔層與支撐層接合。圖案化金屬層設置於第一金屬箔層上，其中晶片適於設置於圖案化金屬層上並與圖案化金屬層電性連接。
基於上述，本發明的封裝載板採用對稱的方式分別於兩彼此接合的基底金屬層上進行封裝載板的製程，因此，於拆板後，可同時得到兩個各自獨立的封裝載板，故能有效節省製程時間，並提高生產效能。此外，本發明的封裝載板是利用圖案化金屬層來承載及電性連接晶片，並且將離型金屬膜連接於支撐層以及圖案化金屬層之間，使支撐層在完成晶片的封膠製程後可透過離型金屬膜的可分離特性而輕易被移除。因此，相較於習知由多層圖案化線路層與圖案化介電層交錯堆疊於核心介電層所構成之封裝載板而言，本發明的封裝載板可使後續完成的封裝結構具有較薄的封裝厚度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10‧‧‧封裝結構
100‧‧‧封裝載板
105‧‧‧膠層
110‧‧‧基底金屬層
120‧‧‧支撐層
122‧‧‧第一表面
124‧‧‧第二表面
130‧‧‧離型金屬膜
132‧‧‧第一金屬箔層
134‧‧‧第二金屬箔層
140‧‧‧圖案化金屬層
142‧‧‧晶片接墊
144‧‧‧接合接墊
150‧‧‧圖案化光阻層
152‧‧‧開口
160‧‧‧蝕刻終止層
170‧‧‧表面處理層
200‧‧‧晶片
210‧‧‧導線
220‧‧‧封裝膠體
230‧‧‧焊球
圖1A至圖1G是依照本發明的一實施例的一種封裝載板的製作方法的剖面示意圖。
圖2A至圖2D為圖1G之封裝載板承載一晶片之製程步驟的剖面示意圖。
圖1A至圖1G是依照本發明的一實施例的一種封裝載板 的製作方法的剖面示意圖。在本實施例中，封裝載板的製作方法包括下列步驟：首先，請參照圖1A，接合兩基底金屬層110。在本實施例中，兩基底金屬層110分別可為兩銅箔層，並藉由將膠層105塗佈於兩基底金屬層110的周緣來接合兩基底金屬層110，並於兩基底金屬層110的周緣形成一密合區，使兩基底金屬層110暫時地接合在一起，以避免後續製程中所使用的藥劑滲入於兩基底金屬層110之間。
請接續參照圖1B，分別壓合兩支撐層120於兩基底金屬層110上。接著，再分別設置兩離型金屬膜130於兩支撐層120上，其中，各離型金屬膜130包括可彼此分離之第一金屬箔層132及第二金屬箔層134。在本實施例中，第二金屬箔層134的厚度實質上大於第一金屬箔層132的厚度。具體而言，第二金屬箔層134的厚度約為18微米(μm)，第一金屬箔層132的厚度約為5微米(μm)。當然，本實施例僅用以舉例說明而並不以此為限。
接著，請同時參照圖1C以及圖1D，先分別形成如圖1C所示的兩圖案化光阻層150於兩離型金屬膜130上，其中，圖案化光阻層150可包括多個開口152，以分別暴露部份離型金屬膜130。接著，再如圖1D所示，以圖案化光阻層150為罩幕，分別形成兩圖案化金屬層140於開口152內，使兩圖案化金屬層140覆蓋於開口152暴露的部份離型金屬膜130上。各圖案化金屬層140適於承載以及電性連接一晶片。在本實施例中，圖案化金屬層140可如圖1D所示包括一晶片接墊142與多個接合接墊144。晶 片可例如設置於晶片接墊142上，再透過多條導線與接合接墊144電性連接。在本實施例中，圖案化金屬層140的線寬例如是介於15微米至35微米之間。意即，本實施例的圖案化金屬層140可視為一種細線路。並且，依此方式所形成的圖案化金屬層140可依據圖案化光阻層150的厚度輕易控制圖案化金屬層140的形成厚度。因此，使用者亦可透過控制圖案化金屬層140的厚度來調整依此製程所形成的封裝載板的厚度。當然，在本發明的其他實施例中，圖案化金屬層140亦可透過蝕刻製程等減成法(subtractive process)形成。
此外，在本發明的一實施例中，亦可在形成圖案化金屬層140之前，先分別形成如圖1D所示的兩蝕刻終止層160於圖案化光阻層150的開口152所暴露的部份離型金屬膜130內。蝕刻終止層160例如為一鎳層，並可透過電鍍的方式形成於圖案化光阻層150的開口152內。
之後，可再分別形成如圖1E所示的兩表面處理層170於兩圖案化金屬層140的上表面上。在本實施例中，表面處理層170可包括一電鍍金層、一電鍍銀層、一還原金層、一還原銀層、一電鍍鎳鈀金層、一化鎳鈀金層或一有機保焊劑(organic solderability preservatives,OSP)層，當然，本實施例並不以此為限。接著，再移除圖案化光阻層150，即可形成如圖1F所示的兩圖案化金屬層140於兩離型金屬膜130上。
之後，分離兩基底金屬層110的密合區，以使兩基底金 屬層110分離，即可形成如圖1G所示的各自獨立的兩封裝載板100。如此，依上述製作方法所形成的各封裝載板100包括一基底金屬層110、一支撐層120、一離型金屬膜130以及一圖案化金屬層140。支撐層120包括一第一表面122以及相對第一表面122的一第二表面124。基底金屬層110設置於支撐層120的第一表面122上。離型金屬膜130則設置於支撐層120的第二表面124上，其中，離型金屬膜130包括可彼此分離之一第一金屬箔層132以及一第二金屬箔層134，其中，第二金屬箔層134與支撐層120接合，而圖案化金屬層140則設置於第一金屬箔層132上。也就是說，第一金屬箔層132以及第二金屬箔層134分別與圖案化金屬層140以及支撐層120接合。
在此需說明的是，由於本實施例是採用對稱的方式來形成兩個支撐層120及其上之圖案化金屬層140，因此，於壓合支撐層120的過程中，可以有效避免壓合後結構呈現彎翹的問題。再者，由於本實施例是採用對稱的方式來進行封裝載板的製程，因此於拆板後(即分離兩基底金屬層110之後)，可同時得到兩個各自獨立的封裝載板，可有效節省製程時間，並提高生產效能。
圖2A至圖2D為圖1G之封裝載板承載一晶片之製程步驟的剖面示意圖。請先參考圖2A，在本實施例中，前述製作方法所形成的封裝載板100適用於承載以及電性連接一晶片200。在本實施例中，晶片200例如是單一晶片或是一晶片模組。本實施例並不限定晶片200的種類。晶片200可透過一黏著層而配置於圖 案化金屬層140的晶片接墊142上，且晶片200可例如透過一導線210與圖案化金屬層140的接合接墊144電性連接。也就是說，本實施例之晶片200是透過打線接合而電性連接至圖案化金屬層140。
接著，如圖2B所示，進行一封膠製程，以形成封裝膠體220於封裝載板100上，其中，封裝膠體220包覆晶片200、導線210以及圖案化金屬層140，且覆蓋支撐層120的部份第一表面122。之後，再如圖2C所示，使第一金屬箔層132以及第二金屬箔層134彼此分離，以移除支撐層120，並透過蝕刻製程移除殘留於圖案化金屬層140上的離型金屬膜130(例如為第一金屬箔層132)，以暴露出圖案化金屬層140以及封裝膠體220的下表面。
在此，由於本實施例在形成圖案化金屬層140之前，先形成蝕刻終止層160於離型金屬膜130上，也就是說，蝕刻終止層160位於圖案化金屬層140與離型金屬膜130之間。因此，在透過蝕刻製程移除殘留的離型金屬膜130時，蝕刻製程會停止於蝕刻終止層160而不會傷害到圖案化金屬層140。最後，再移除蝕刻終止層160即可形成如圖2D所示的封裝結構10。在本實施例中，封裝結構10可例如透過多個焊球230與外部電子元件電性連接。
在此須說明的是，本發明並不限定晶片200與封裝載板100的接合形態，雖然此處所提及的晶片200是透過打線接合而電性連接至封裝載板100。然而，在本發明的其他實施例中，晶片 200亦可例如透過覆晶接合的方式而電性連接至圖案化金屬層140上。也就是說，上述之晶片200與封裝載板100的接合形態僅為舉例說明之用，並非用以限定本發明。
綜上所述，本發明的封裝載板採用對稱的方式分別於兩彼此接合的基底金屬層上進行封裝載板的製程，因此，於拆板後，可同時得到兩個各自獨立的封裝載板，有效節省製程時間，並提高生產效能。此外，本發明是利用圖案化金屬層來承載及電性連接晶片，並且將離型金屬膜連接於支撐層以及圖案化金屬層之間，使支撐層在完成晶片的封膠製程後可透過離型金屬膜的分離特性而輕易被移除。因此，相較於習知由多層圖案化線路層與圖案化介電層交錯堆疊於核心介電層所構成之封裝載板而言，本發明的封裝載板可使後續完成的封裝結構具有較薄的封裝厚度。再者，由於晶片是配置於圖案化金屬層上，因此晶片所產生的熱可直接透過圖案化金屬層快速地傳遞至外界。也就是說，本發明的封裝載板不但可有效減少其後續完成的封裝結構的封裝厚度，更可提高此封裝結構的散熱效果。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100‧‧‧封裝載板
110‧‧‧基底金屬層
120‧‧‧支撐層
122‧‧‧第一表面
124‧‧‧第二表面
130‧‧‧離型金屬膜
132‧‧‧第一金屬箔層
134‧‧‧第二金屬箔層
170‧‧‧表面處理層

Claims (16)

  1. 一種封裝載板的製作方法，包括：接合兩基底金屬層；分別壓合兩支撐層於該兩基底金屬層上；分別設置兩離型金屬膜於該兩支撐層上，其中各該離型金屬膜包括可彼此分離之一第一金屬箔層以及一第二金屬箔層；分別形成兩圖案化金屬層於該兩離型金屬膜上，各該圖案化金屬層適於承載以及電性連接一晶片；以及令該兩基底金屬層分離，以形成各自獨立的兩封裝載板。
  2. 如申請專利範圍第1項所述的封裝載板的製作方法，其中該第二金屬箔層的厚度實質上大於該第一金屬箔層的厚度。
  3. 如申請專利範圍第1項所述的封裝載板的製作方法，其中分別形成該兩圖案化金屬層於該兩離型金屬膜上的步驟包括：分別形成兩圖案化光阻層於該兩離型金屬膜上，該兩圖案化光阻層分別暴露部份該兩離型金屬膜；以該兩圖案化光阻層為罩幕，分別形成該兩圖案化金屬層於暴露的部份該兩離型金屬膜上；以及移除該兩圖案化光阻層。
  4. 如申請專利範圍第3項所述的封裝載板的製作方法，更包括：在分別形成該兩圖案化金屬層於暴露的部份該兩離型金屬膜上之前，分別形成兩蝕刻終止層於暴露的部份該兩離型金屬膜上。
  5. 如申請專利範圍第4項所述的封裝載板的製作方法，其中該兩蝕刻終止層包括電鍍鎳層。
  6. 如申請專利範圍第3項所述的封裝載板的製作方法，更包括：在分別形成該兩圖案化金屬層於暴露的部份該兩離型金屬膜上之後，分別形成兩表面處理層於該兩圖案化金屬層上。
  7. 如申請專利範圍第6項所述的封裝載板的製作方法，其中各該表面處理層包括電鍍金層、電鍍銀層、還原金層、還原銀層、電鍍鎳鈀金層、化鎳鈀金層或有機保焊劑(organic solderability preservatives,OSP)層。
  8. 如申請專利範圍第1項所述的封裝載板的製作方法，其中接合該兩基底金屬層的步驟包括：藉由一膠層黏合該兩基底金屬層的周緣，以於該兩基底金屬層的周緣形成一密合區。
  9. 如申請專利範圍第8項所述的封裝載板的製作方法，其中令該兩基底金屬層分離的步驟包括：分離該兩基底金屬層的該密合區。
  10. 一種封裝載板，適於承載一晶片，包括：一支撐層，包括一第一表面以及相對該第一表面的一第二表面；一基底金屬層，設置於該支撐層的該第一表面上；一離型金屬膜，設置於該支撐層的該第二表面上，該離型金 屬膜包括可彼此分離之一第一金屬箔層以及一第二金屬箔層，該第二金屬箔層與該支撐層接合；以及一圖案化金屬層，設置於該第一金屬箔層上，其中該晶片適於設置於該圖案化金屬層上並與該圖案化金屬層電性連接。
  11. 如申請專利範圍第10項所述的封裝載板，其中該第二金屬箔層的厚度實質上大於該第一金屬箔層的厚度。
  12. 如申請專利範圍第10項所述的封裝載板，其中該圖案化金屬層包括一晶片接墊以及多個接合接墊，該晶片適於設置於該晶片接墊上，並透過多條導線電性連接至該些接合接墊上。
  13. 如申請專利範圍第10項所述的封裝載板，更包括一蝕刻終止層，設置於該離型金屬膜與該圖案化金屬層之間。
  14. 如申請專利範圍第13項所述的封裝載板，其中該蝕刻終止層包括電鍍鎳層。
  15. 如申請專利範圍第10項所述的封裝載板，更包括一表面處理層，覆蓋該圖案化金屬層的一上表面。
  16. 如申請專利範圍第15項所述的封裝載板，其中該表面處理層包括電鍍金層、電鍍銀層、還原金層、還原銀層、電鍍鎳鈀金層、化鎳鈀金層或有機保焊劑(organic solderability preservatives,OSP)層。
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