JP5945563B2 - パッケージキャリアおよびその製造方法 - Google Patents

パッケージキャリアおよびその製造方法 Download PDF

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JP5945563B2
JP5945563B2 JP2014118746A JP2014118746A JP5945563B2 JP 5945563 B2 JP5945563 B2 JP 5945563B2 JP 2014118746 A JP2014118746 A JP 2014118746A JP 2014118746 A JP2014118746 A JP 2014118746A JP 5945563 B2 JP5945563 B2 JP 5945563B2
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layer
metal
layers
patterned
manufacturing
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JP2015070262A (ja
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世豪 孫
世豪 孫
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旭徳科技股▲ふん▼有限公司
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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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Description

本発明は、パッケージ構造およびその製造方法に関する。特に、本発明はパッケージキャリア（package carrier）およびその製造方法に関する。
技術背景
チップパッケージの目的は、露出されたチップを保護し、チップの接点密度（contact density）を減少させ、チップに好ましい熱散逸を提供することにある。チップは、ワイヤボンディング（wire bonding）またはフリップチップボンディング（flip chip bonding）によりキャリアに電気接続されることから、チップ上のボンディングパッド（bonding pad）がキャリアの接点に電気接続されることができ、その結果、チップパッケージが形成される。従って、チップの接点は、次の階層である外部デバイスの接点分配に適合するよう、パッケージキャリアを介して再分配されることができる。
一般的に、パッケージキャリアを形成するために、コア誘電体層がしばしばコア材としての役割を務め、フルアディティブ法、セミアディティブ法、サブトラクティブ法やその他の方法によって、パターン化回路層とパターン化誘電体層が交互にコア誘電体層上に積み重ねられる。結果として、コアはパッケージキャリアの全体の厚みにおける大きな比率を占める。このため、もしコア誘電体層の厚みの減少に障壁があると、パッケージキャリア全体の厚みを著しく減少させることは難しい。
本発明は、チップを搭載可能なパッケージキャリアを提供することを目的とし、このパッケージキャリアを用いたパッケージ構造の厚みは減少される。また上述のパッケージキャリアの製造方法を提供することを目的とする。
本発明は以下のステップを含むパッケージキャリアの製造方法を提供する。先ず、２つのベース金属層が接合される。次に、２つの支持層が、各ベース金属層上にそれぞれラミネートされる(laminated)。次に、２つの剥離用金属膜が、各支持層上にそれぞれ配置され、各剥離用金属膜は、互いに分離可能な第１金属膜と第２金属膜を含む。次に、２つのパターン化金属層が、各剥離用金属膜上にそれぞれ形成され、各パターン化金属層はチップを搭載可能であり且つチップに電気接続可能である。その後、互いに独立した２つのパッケージキャリアを形成するため、２つのベース金属層が互いから分離される。
本発明は、チップを搭載可能なパッケージキャリアを提供する。パッケージキャリアは、支持層、ベース金属層、剥離用金属膜、及びパターン化金属層を含む。支持層は、第１表面と、第１表面の反対側の第２表面を含む。ベース金属層は支持層の第１表面上に配置される。剥離用金属膜は、支持層の第２表面上に配置される。剥離用金属膜は、互いに分離された第１金属箔と第２金属箔を含み、第２金属箔は支持層に接合される。パターン化金属層は第１金属箔上に配置され、チップはパターン化金属層上に配置されパターン化金属層に電気接続されるよう適合される。
本発明のパッケージキャリアの製造プロセスは、互いに接合された２つのベース金属層上にて対称的に実施される。このため、ベース金属層が分離された後に２つの独立したパッケージキャリアが同時に形成されることから、製造時間が短縮され、製造効率が向上する。加えて、本発明のパッケージキャリアは、チップを搭載しそのチップと電気接続するためにパターン化金属層を採用しており、剥離用金属膜が支持層とパターン化金属層との間に接続されることから、剥離用金属膜の分離可能な特色の採用によって、支持層はモールドプロセスの後に容易に取り除かれることができる。このため、コア誘電体層上に交互に積み重ねられた複数のパターン化回路層とパターン化誘電体層からなる従来のパッケージキャリアと比較し、本発明のパッケージキャリアは、このパッケージキャリアを用いたパッケージ構造の総体的な厚みを薄くすることを可能とする。
本発明の上記特徴と利点をより理解できるように、図面を伴ういくつかの実施形態を以下に詳細に説明する。
本発明の実施形態によるパッケージキャリアの製造ステップを示す概略的断面図である。 本発明の実施形態によるパッケージキャリアの製造ステップを示す概略的断面図である。 本発明の実施形態によるパッケージキャリアの製造ステップを示す概略的断面図である。 本発明の実施形態によるパッケージキャリアの製造ステップを示す概略的断面図である。 本発明の実施形態によるパッケージキャリアの製造ステップを示す概略的断面図である。 本発明の実施形態によるパッケージキャリアの製造ステップを示す概略的断面図である。 本発明の実施形態によるパッケージキャリアの製造ステップを示す概略的断面図である。
図１Ｇに示されるパッケージキャリアにチップを搭載する製造ステップを示す概略的断面図である。 図１Ｇに示されるパッケージキャリアにチップを搭載する製造ステップを示す概略的断面図である。 図１Ｇに示されるパッケージキャリアにチップを搭載する製造ステップを示す概略的断面図である。 図１Ｇに示されるパッケージキャリアにチップを搭載する製造ステップを示す概略的断面図である。
図１Ａから図１Ｇは、本発明の実施形態によるパッケージキャリアの製造ステップを示す概略的断面図である。本実施形態において、パッケージキャリアの製造方法は以下のステップを含む。先ず、図１Ａに示されるように、２つのベース金属層１１０が接合される。本実施形態において、２つのベース金属層１１０は、２つの銅箔でありえ、また２つのベース金属層１１０の辺縁に封止領域を形成するため、２つのベース金属層１１０の辺縁に粘着層１０５を塗布することで接合される。このようにして、２つのベース金属層１１０は、後続処理にて用いられる薬品または試薬の侵入を防ぐために、一時的に互いに接合される。
図１Ｂに示されるように、２つの支持層１２０が、各ベース金属層１１０上にそれぞれラミネートされる。次に、２つの剥離用金属膜１３０が、各支持層１２０上にそれぞれ配置され、各剥離用金属膜１３０には、互いに分離可能な第１金属箔１３２と第２金属箔１３４を含む。本発明のひとつの実施形態において、第２金属箔１３４の厚みは、第１金属箔１３２の厚みよりも実質的に大きい。具体的に述べると、第２金属箔１３４の厚みは約１８μｍであり、第１金属箔１３２の厚みは約５μｍである。ただし、本発明は、本発明の実施形態により制限されると解釈されてはならない。
次に、図１Ｃと図１Ｄに示されるように、図１Ｃに示される２つのパターン化フォトレジスト層１５０が、２つの剥離用金属膜１３０上にそれぞれ形成され、各パターン化フォトレジスト層１５０は、対応する剥離用金属膜１３０の一部を露出する複数の開口１５２を含むことができる。次に、図１Ｄに示されるように、２つのパターン化金属層１４０が、パターン化フォトレジスト層１５０をマスクとして用いることで、開口１５２上にそれぞれ形成されることにより、これら２つのパターン化金属層１４０が開口１５２によって露出された剥離用金属膜１３０の一部を覆う。各パターン化金属層１４０はチップを搭載可能で且つチップと電気接続可能である。本実施形態において、各パターン化金属層１４０は、図１Ｄに示されるチップパッド１４２と複数のボンディングパッド１４４を含むことができる。チップは、例えば、チップパッド１４２上に配置され且つ複数の導電ワイヤによってボンディングパッド１４４に電気接続される。本実施形態において、パターン化金属層１４０は複数の回路を含み、パターン化金属層１４０の各回路の幅は、例えば、１５μｍから３５μｍの間である。つまり、本実施形態のパターン化金属層１４０の回路は、ファイン回路と見ることができる。さらに、上述の方法で形成されたパターン化金属層１４０の厚みは、パターン化フォトレジスト層１５０の厚みに基づき制御することができる。このため、作業者は上記製造方法で形成されたパッケージキャリアの厚みを、パターン化金属層１４０の厚みを制御することで調節できる。当然、その他の実施形態においては、パターン化金属層１４０はエッチング処理といったサブトラクティブ法によって形成することもできる。
加えて、本発明のひとつの実施形態においては、２つのエッチング停止層１６０が、パターン化金属層１４０が形成される前に、開口１５２により露出された剥離用金属膜の一部上にそれぞれ形成される。エッチング停止層１６０は、例えば、ニッケル層であり、電気めっきによりパターン化フォトレジスト層１５０の開口１５２に形成される。
後に、２つの表面処理層１７０が、図１Ｅに示されるように、２つのパターン化金属層１４０の上面にそれぞれ形成される。本実施形態において、各表面処理層１７０は電気めっきされた金層、電気めっきされた銀層、還元金層、還元銀層、電気めっきされたニッケル―パラジウム―金層、化学めっきされたニッケル―パラジウム―金層、または有機半田付け性保存剤（organic solderabilitypreservatives,OSP）層等を含む。当然ながら、本実施形態はこれに制限されるものではない。その後、パターン化フォトレジスト層１５０が取り除かれ、図１Ｆに示される２つのパターン化金属層１４０が、２つの剥離用金属膜１３０上にそれぞれ形成される。
後に、２つのベース金属層１１０の封止領域が分離される。図１Ｇに示されるような互いに独立した２つのパッケージキャリア１００を形成するため、２つのベース金属層１１０は互いから分離される。その結果、上述の製造方法によって形成された各パッケージキャリア１００は、ベース金属層１１０、支持層１２０、剥離用金属膜１３０とパターン化金属層１４０を含む。支持層１２０は、第１表面１２２と、第１表面１２２の反対側の第２表面１２４を含む。ベース金属層１１０は、支持層１２０の第１表面１２２上に配置される。剥離用金属膜１３０は、支持層１２０の第２表面１２４上に配置され、剥離用金属膜１３０は、互いに分離可能な第１金属箔１３２と第２金属箔１３４を含む。第２金属箔１３４は支持層１２０に接合され、パターン化金属層１４０は第１金属箔１３２上に配置される。つまり、第１金属箔１３２と第２金属箔１３４はそれぞれ、パターン化金属層１４０と支持層１２０に接合される。
注目すべきは、本実施形態において、支持層１２０とその上のパターン化金属層１４０は対称的に形成されており、支持層１２０のラミネート処理における構造の歪みを効果的に避けることができる。さらに、本実施形態のパッケージキャリア製造プロセスは、互いに接合された２つのベース金属層上において対称的に実施され、ベース金属層が分離された後、２つのパッケージキャリアが同時に形成されることから、製造時間が短縮され、生産効率が向上される。
図２Ａから図２Ｄは、図１Ｇに示されるパッケージキャリアにチップを搭載する製造ステップを示す概略的断面図である。図２Ａに示されるように、本実施形態にて、上述の製造方法で形成されたパッケージキャリア１００は、チップ２００を搭載可能で且つチップ２００と電気接続可能である。本実施形態において、チップ２００は、例えば、単一チップまたはチップモジュールである。つまり、本実施形態はチップ２００の種類を制限しない。チップ２００はパターン化金属層１４０のチップパッド１４２上に粘着層を介し配置されることができ、チップ２００はパターン化金属層１４０のボンディングパッド１４４に複数の導電ワイヤ２１０により電気接続されることができる。つまり、本実施形態のチップ２００は、ワイヤボンディングによりパターン化金属層１４０に電気接続される。
次に、図２Ｂに示されるように、パッケージキャリア１００上のモールド・コンパウンド(mold compound)２２０を形成するため、モールドプロセスが実施される。モールド・コンパウンド２２０はチップ２００、導電ワイヤ２１０とパターン化金属層１４０を覆い、支持層１２０の第１表面１２２の一部を覆う。その後、図２Ｃに示されるように、第１金属箔１３２と第２金属箔１３４は、支持層１２０を取り除くため互いに分離され、その後、パターン化金属層１４０上に残った第１金属箔１３２といった剥離用金属膜１３０が、パターン化金属層１４０とモールド・コンパウンド２２０の底面を露出するため、エッチングプロセスにより取り除かれる。
ここで、パターン化金属層１４０が形成される前に、エッチング停止層１６０が先ず剥離用金属膜１３０上に形成される。つまり、エッチング停止層１６０は、パターン化金属層１４０と剥離用金属膜１３０との間に位置する。このため、エッチングプロセスにより剥離用金属膜１３０が取り除かれるとき、エッチングプロセスはエッチング停止層１６０にて止まり、パターン化金属層１４０が傷つけられることはない。最後に、図２Ｄに示されるように、パッケージ構造１０を形成するためエッチングストップ層１６０が取り除かれる。本実施形態において、パッケージ構造１０は外部電子デバイスと、例えば、複数のはんだボール２３０により、電気接続する。
言及すべきこととして、チップ２００がパッケージキャリア１００にワイヤボンディングにより電気的に接続されると示されているとはいえ、本発明はチップ２００とパッケージキャリア１００のボンディング方法を制限しない。しかし、その他の実施形態において、チップ２００はフリップチップボンディング技術を介しパターン化金属層１４０に電気的に接続されうる。つまり、チップ２００とパッケージキャリア１００の前記ボンディング方法は単に例示的なものであり、本発明を制限するものとして解釈されてはならない。
本発明のパッケージキャリアの製造プロセスは、互いに接合された２つのベース金属層上にて対称的に実施される。従って、ベース金属層が分離された後、２つの独立したパッケージキャリアが同時に形成されることから、製造時間が短縮され、製造効率が向上する。加えて、本発明のパッケージキャリアは、チップを搭載し且つそのチップと電気接続するためにパターン化金属層を採用しており、剥離用金属膜が支持層とパターン化金属層との間に接続されることから、剥離金属膜の分離可能な特色の採用によって、支持層はモールドプロセスの後に容易に取り除くことができる。このため、コア誘電体層上に交互に積み重ねられた複数のパターン化回路層とパターン化誘電体層からなる従来のパッケージキャリアと比較し、本発明のパッケージキャリアは、このパッケージキャリアを用いたパッケージ構造の総体的な厚みを薄くすることを可能とする。さらに、チップがパターン化金属層上に配置されることから、チップにより発生した熱は、パターン化金属層を介し直接外部環境へ散逸されることができる。つまり、本発明のパッケージキャリアは、パッケージ構造の総体的な厚みを効果的に減少するのみでなく、パッケージ構造の熱散逸効率を向上することができる。
本発明は上記実施形態において説明されているが、本発明の技術思想から離れることなく、説明された実施形態への改変がされうることは、当業者にとって明白である。従って、本発明の範囲は、上記の詳細説明ではなく、添付の請求項によって定義される。
１０ パッケージ構造
１００ パッケージキャリア
１０５ 粘着層
１１０ ベース金属層
１２０ 支持層
１２２ 第１表面
１２４ 第２表面
１３０ 剥離用金属膜
１３２ 第１金属箔
１３４ 第２金属箔
１４０ パターン化金属層
１４２ チップパッド
１４４ ボンディングパッド
１５０ パターン化フォトレジスト層
１５２ 開口
１６０ エッチング停止層
１７０ 表面処理層
２００ チップ
２１０ 導電ワイヤ
２２０ モールド・コンパウンド
２３０ はんだボール

Claims (8)

  1. ２つのベース金属層の間に粘着層により前記２つのベース金属層の辺縁を粘着させて、
    前記２つのベース金属層の間で前記２つのベース金属層の辺縁に封止領域を形成することと、
    ２つの支持層を前記ベース金属層上にそれぞれラミネートすることと、
    ２つの剥離用金属膜を前記支持層上にそれぞれ設け、各前記剥離用金属膜は互いに分離された第１金属箔と第２金属箔を含むことと、
    ２つのパターン化金属層を前記剥離用金属膜上にそれぞれ形成し、各前記パターン化金属層はチップを搭載可能で且つ前記チップと電気接続可能であることと、
    互いに独立したパッケージキャリアを形成するため２つの前記ベース金属層を互いに分離することと
    を含むパッケージキャリアの製造方法。
  2. 前記第２金属箔の厚みが前記第１金属箔の厚みより実質的に大きい、請求項1に記載の製造方法。
  3. 前記剥離用金属膜上に前記パターン化金属層をそれぞれ形成することが、
    ２つのパターン化フォトレジスト層を前記剥離用金属膜上にそれぞれ形成し、前記パターン化フォトレジスト層はそれぞれ前記剥離用金属膜の一部を露出することと、
    ２つのパターン化金属層を、前記パターン化フォトレジスト層をマスクとして用いることにより、前記剥離用金属膜の露出部分上にそれぞれ形成することと、
    前記パターン化フォトレジスト層を取り除くことと
    を含む、請求項1に記載の製造方法。
  4. 前記剥離用金属膜の露出部分上に前記パターン化金属層を形成する前に、２つのエッチング停止層を前記剥離用金属膜の露出部分上にそれぞれ形成することをさらに含む、請求項３に記載の製造方法。
  5. 各前記エッチング停止層が電気めっきされたニッケル層を備える、請求項４に記載の製造方法。
  6. 前記剥離用金属膜の露出部分上に前記パターン化金属層をそれぞれ形成した後、２つの表面処理層を前記パターン化金属層上にそれぞれ形成することをさらに含む、請求項３に記載の製造方法。
  7. 各前記表面処理層が、電気めっきされた金層、電気めっきされた銀層、還元金層、還元銀層、電気めっきされたニッケル―パラジウム―金層、化学めっきされたニッケル―パラジウム―金層、または有機半田付け性保存剤（organic solderability preservatives,OSP）層を含む、請求項６に記載の製造方法。
  8. 前記ベース金属層を分離することが、前記ベース金属層の前記封止領域を分離することを含む、請求項１に記載の製造方法。
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US20150090481A1 (en) 2015-04-02
US9236364B2 (en) 2016-01-12
JP2015070262A (ja) 2015-04-13
TWI474449B (zh) 2015-02-21

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