CN110268511A - 一种三极管的封装方法及三极管 - Google Patents

一种三极管的封装方法及三极管 Download PDF

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Publication number
CN110268511A
CN110268511A CN201780077309.2A CN201780077309A CN110268511A CN 110268511 A CN110268511 A CN 110268511A CN 201780077309 A CN201780077309 A CN 201780077309A CN 110268511 A CN110268511 A CN 110268511A
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China
Prior art keywords
pad
triode
layer
surface metal
chip
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CN201780077309.2A
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English (en)
Inventor
黄冕
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Shenzhen Siptory Technologies Co ltd
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Shenzhen Siptory Technologies Co ltd
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Priority claimed from CN201611202022.1A external-priority patent/CN106783631B/zh
Priority claimed from CN201611205111.1A external-priority patent/CN106601699A/zh
Priority claimed from CN201611202117.3A external-priority patent/CN106783632B/zh
Application filed by Shenzhen Siptory Technologies Co ltd filed Critical Shenzhen Siptory Technologies Co ltd
Publication of CN110268511A publication Critical patent/CN110268511A/zh
Pending legal-status Critical Current

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  • Wire Bonding (AREA)

Abstract

提供了一种三极管的封装方法及三极管,用于解决现有三极管的占用空间大,封装效率低的问题。方法包括:提供载体(10),并在载体的至少一个面上覆盖表面金属层(11);在表面金属层的线路图形区域覆盖抗蚀膜(12);对表面金属层的非线路图形区域进行电镀,形成至少一个第一焊盘(13);在至少一个第一焊盘上焊接芯片(14);在芯片上焊接第二焊盘(15)形成三极管模板;采用复合材料(16)对三极管模板进行塑封处理;在第二焊盘和至少一个第一焊盘的垂直方向上钻盲孔(17),并将盲孔处理成金属化盲孔:对金属化盲孔经过图形制作形成线路闭合回路或非闭合回路,封装出三极管。

Description

PCT国内申请,说明书已公开。

Claims (3)

  1. PCT国内申请,权利要求书已公开。
CN201780077309.2A 2016-12-22 2017-12-21 一种三极管的封装方法及三极管 Pending CN110268511A (zh)

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Families Citing this family (3)

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Publication number Priority date Publication date Assignee Title
CN113571434B (zh) * 2021-06-07 2023-11-17 华宇华源电子科技(深圳)有限公司 一种新型的面板级封装方法及结构
EP4191643A1 (en) 2021-12-02 2023-06-07 Nexperia B.V. Method of forming an interconnect metallisation by panel level packaging and the corresponding device
CN115954284A (zh) * 2023-03-15 2023-04-11 合肥矽迈微电子科技有限公司 一种mosfet芯片的封装工艺

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050006142A1 (en) * 2003-07-09 2005-01-13 Matsushita Electric Industrial Co., Ltd. Circuit board with in-built electronic component and method for manufacturing the same
US8507320B2 (en) * 2008-03-18 2013-08-13 Infineon Technologies Ag Electronic device including a carrier and a semiconductor chip attached to the carrier and manufacturing thereof
US20130256856A1 (en) * 2012-03-27 2013-10-03 Infineon Technologies Ag Multichip Power Semiconductor Device
CN103383921A (zh) * 2012-05-03 2013-11-06 英飞凌科技股份有限公司 半导体封装件及其形成方法
US8637341B2 (en) * 2008-03-12 2014-01-28 Infineon Technologies Ag Semiconductor module
CN103688350A (zh) * 2011-02-23 2014-03-26 德克萨斯仪器股份有限公司 嵌入pcb基板的芯片模块
CN104183567A (zh) * 2014-08-19 2014-12-03 华进半导体封装先导技术研发中心有限公司 薄型封装基板及其制作工艺
CN104576421A (zh) * 2013-10-25 2015-04-29 英飞凌科技股份有限公司 半导体器件和用于制造半导体器件的方法
CN106057749A (zh) * 2015-04-10 2016-10-26 株式会社吉帝伟士 半导体封装件及其制造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01228139A (ja) 1988-03-09 1989-09-12 Fuji Electric Co Ltd 二端子半導体の平形構造
JP4759981B2 (ja) * 2004-11-02 2011-08-31 大日本印刷株式会社 電子部品内蔵モジュールの製造方法
JP5065586B2 (ja) * 2005-10-18 2012-11-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2008103382A (ja) 2006-10-17 2008-05-01 Toshiba Corp 半導体装置及びその製造方法
KR101030356B1 (ko) * 2008-12-08 2011-04-20 삼성전기주식회사 반도체 패키지의 제조 방법
US8201326B2 (en) * 2008-12-23 2012-06-19 Infineon Technologies Ag Method of manufacturing a semiconductor device
US8338231B2 (en) * 2010-03-29 2012-12-25 Infineon Technologies Ag Encapsulated semiconductor chip with external contact pads and manufacturing method thereof
CN102386105B (zh) * 2010-09-01 2016-02-03 群成科技股份有限公司 四边扁平无接脚封装方法及其制成的结构
TWI533380B (zh) * 2011-05-03 2016-05-11 旭德科技股份有限公司 封裝結構及其製作方法
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US20130049214A1 (en) * 2011-08-29 2013-02-28 Infineon Technologies Ag Method of processing at least one die and die arrangement
CN102751254A (zh) 2012-07-18 2012-10-24 日月光半导体制造股份有限公司 半导体封装件、应用其的堆迭封装件及其制造方法
CN103400770B (zh) 2013-08-06 2016-02-24 江苏长电科技股份有限公司 先封后蚀芯片倒装凸点三维系统级金属线路板及工艺方法
TWI474449B (zh) * 2013-09-27 2015-02-21 Subtron Technology Co Ltd 封裝載板及其製作方法
CN103607841B (zh) * 2013-12-04 2016-06-01 江苏长电科技股份有限公司 Smt减法高密度封装多层线路板结构及其制作方法
CN104916597B (zh) * 2014-03-14 2018-06-05 尼克森微电子股份有限公司 晶圆级扇出芯片的封装方法及封装结构
CN106783631B (zh) * 2016-12-22 2020-01-14 深圳中科四合科技有限公司 一种二极管的封装方法及二极管
CN106601699A (zh) * 2016-12-22 2017-04-26 深圳中科四合科技有限公司 一种分立器件的封装方法及分立器件
CN106783632B (zh) * 2016-12-22 2019-08-30 深圳中科四合科技有限公司 一种三极管的封装方法及三极管

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050006142A1 (en) * 2003-07-09 2005-01-13 Matsushita Electric Industrial Co., Ltd. Circuit board with in-built electronic component and method for manufacturing the same
US8637341B2 (en) * 2008-03-12 2014-01-28 Infineon Technologies Ag Semiconductor module
US8507320B2 (en) * 2008-03-18 2013-08-13 Infineon Technologies Ag Electronic device including a carrier and a semiconductor chip attached to the carrier and manufacturing thereof
CN103688350A (zh) * 2011-02-23 2014-03-26 德克萨斯仪器股份有限公司 嵌入pcb基板的芯片模块
US20130256856A1 (en) * 2012-03-27 2013-10-03 Infineon Technologies Ag Multichip Power Semiconductor Device
CN103383921A (zh) * 2012-05-03 2013-11-06 英飞凌科技股份有限公司 半导体封装件及其形成方法
CN104576421A (zh) * 2013-10-25 2015-04-29 英飞凌科技股份有限公司 半导体器件和用于制造半导体器件的方法
CN104183567A (zh) * 2014-08-19 2014-12-03 华进半导体封装先导技术研发中心有限公司 薄型封装基板及其制作工艺
CN106057749A (zh) * 2015-04-10 2016-10-26 株式会社吉帝伟士 半导体封装件及其制造方法

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